JP2005203751A5 - - Google Patents
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- JP2005203751A5 JP2005203751A5 JP2004352242A JP2004352242A JP2005203751A5 JP 2005203751 A5 JP2005203751 A5 JP 2005203751A5 JP 2004352242 A JP2004352242 A JP 2004352242A JP 2004352242 A JP2004352242 A JP 2004352242A JP 2005203751 A5 JP2005203751 A5 JP 2005203751A5
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- Prior art keywords
- integrated circuit
- thin film
- film integrated
- circuit devices
- circuit device
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Claims (16)
前記剥離層上に下地膜を介して複数の薄膜集積回路装置を形成し、
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記剥離層を除去することによって、前記複数の薄膜集積回路装置を分離することを特徴とする薄膜集積回路装置の作製方法。 A release layer is formed on a semiconductor substrate whose surface is oxidized,
A plurality of thin film integrated circuit devices are formed on the release layer via a base film,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
A method for manufacturing a thin film integrated circuit device, wherein the plurality of thin film integrated circuit devices are separated by introducing a gas or a liquid containing halogen fluoride into the groove and removing the release layer.
前記剥離層上に下地膜を介して複数の薄膜集積回路装置を形成し、
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記複数の薄膜集積回路装置の上方に、複数の突起部を有するジグの当該突起部を、前記薄膜集積回路装置毎に一時的に接着し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記剥離層を除去することによって、前記複数の薄膜集積回路装置を分離し、
前記複数の薄膜集積回路装置に接着されたジグを取り外すことを特徴とする薄膜集積回路装置の作製方法。 A release layer is formed on a semiconductor substrate whose surface is oxidized,
A plurality of thin film integrated circuit devices are formed on the release layer via a base film,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
The protrusion of the jig having a plurality of protrusions is temporarily bonded to each of the thin film integrated circuit devices above the plurality of thin film integrated circuit devices .
Introducing a gas or liquid containing halogen fluoride into the groove and removing the release layer, the plurality of thin film integrated circuit devices are separated,
A method for manufacturing a thin film integrated circuit device, comprising: removing a jig bonded to the plurality of thin film integrated circuit devices.
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記下部の単結晶シリコン層の少なくとも薄膜集積回路装置側の表面をエッチングすることによって、前記複数の薄膜集積回路装置を分離することを特徴とする薄膜集積回路装置の作製方法。 A plurality of thin film integrated circuit devices are formed using an SOI substrate including an upper single crystal silicon layer, a layer containing silicon oxide or silicon nitride, and a lower single crystal silicon layer,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
A gas or a liquid containing halogen fluoride is introduced into the groove, and at least the surface of the lower single crystal silicon layer on the thin film integrated circuit device side is etched to separate the plurality of thin film integrated circuit devices. A method for manufacturing a thin film integrated circuit device.
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記複数の薄膜集積回路装置の上方に、複数の突起部を有するジグの当該突起部を、前記薄膜集積回路装置毎に一時的に接着し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記下部の単結晶シリコン層の少なくとも薄膜集積回路装置側の表面をエッチングすることによって、前記複数の薄膜集積回路装置を分離し、
前記複数の薄膜集積回路装置に接着されたジグを取り外すことを特徴とする薄膜集積回路装置の作製方法。 A plurality of thin film integrated circuit devices are formed using an SOI substrate including an upper single crystal silicon layer, a layer containing silicon oxide or silicon nitride, and a lower single crystal silicon layer,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
The protrusion of the jig having a plurality of protrusions is temporarily bonded to each of the thin film integrated circuit devices above the plurality of thin film integrated circuit devices .
Introducing a gas or liquid containing halogen fluoride into the groove and etching at least the surface of the lower single crystal silicon layer on the thin film integrated circuit device side, thereby separating the plurality of thin film integrated circuit devices,
A method for manufacturing a thin film integrated circuit device, comprising: removing a jig bonded to the plurality of thin film integrated circuit devices.
前記ジグの接着は、ＵＶ光によって接着力が低下又は喪失する接着剤を用いて行なうことを特徴とする薄膜集積回路装置の作製方法。 In claim 2 or 4,
The method of manufacturing a thin film integrated circuit device, wherein the bonding of the jig is performed using an adhesive whose adhesive strength is reduced or lost by UV light.
前記複数の薄膜集積回路装置上に耐熱性を有する絶縁膜又はテープを形成することを特徴とする薄膜集積回路装置の作製方法。 In any one of Claims 1 thru | or 6,
A method for manufacturing a thin film integrated circuit device, comprising: forming an insulating film or a tape having heat resistance on the plurality of thin film integrated circuit devices.
前記耐熱性を有する絶縁膜は、シリコンと酸素との結合で骨格構造が構成され、置換基に少なくとも水素を含む材料、若しくは置換基にフッ素、アルキル基、または芳香族炭化水素のうち少なくとも一種を有する材料からなることを特徴とする薄膜集積回路装置の作製方法。 In claim 7,
The insulating film having heat resistance has a skeletal structure composed of a bond of silicon and oxygen, and a material containing at least hydrogen as a substituent, or at least one of fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. A method for manufacturing a thin film integrated circuit device, comprising:
前記剥離層は、シリコンを主成分として含むことを特徴とする薄膜集積回路装置の作製方法。 In claim 1 or 2,
The method for manufacturing a thin film integrated circuit device, wherein the release layer contains silicon as a main component.
前記下地膜は、酸化珪素、窒化珪素又は酸窒化珪素を含むことを特徴とする薄膜集積回路装置の作製方法。 In any one of Claims 1 thru | or 9,
The method for manufacturing a thin film integrated circuit device, wherein the base film contains silicon oxide, silicon nitride, or silicon oxynitride.
前記フッ化ハロゲンは、ＣｌＦ３（三フッ化塩素）であることを特徴とする薄膜集積回路装置の作製方法。 In any one of Claims 1 thru | or 10,
The method for manufacturing a thin film integrated circuit device, wherein the halogen fluoride is ClF 3 (chlorine trifluoride).
前記剥離層上に下地膜を介して複数の薄膜集積回路装置を形成し、
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記剥離層を除去することによって、前記複数の薄膜集積回路装置を分離し、
前記分離された薄膜集積回路装置の周囲にアンテナを形成することを特徴とする非接触型薄膜集積回路装置の作製方法。 A release layer is formed on a semiconductor substrate whose surface is oxidized,
A plurality of thin film integrated circuit devices are formed on the release layer via a base film,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
Introducing a gas or liquid containing halogen fluoride into the groove and removing the release layer, the plurality of thin film integrated circuit devices are separated,
A manufacturing method of a non-contact type thin film integrated circuit device, wherein an antenna is formed around the separated thin film integrated circuit device.
前記複数の薄膜集積回路装置の境界に溝を形成し、
前記溝にフッ化ハロゲンを含む気体又は液体を導入し、前記下部の単結晶シリコン層の少なくとも薄膜集積回路装置側の表面をエッチングすることによって、前記複数の薄膜集積回路装置を分離し、
前記分離された薄膜集積回路装置の周囲にアンテナを形成することを特徴とする非接触型薄膜集積回路装置の作製方法。 A plurality of thin film integrated circuit devices are formed using an SOI substrate including an upper single crystal silicon layer, a layer containing silicon oxide or silicon nitride, and a lower single crystal silicon layer,
Forming a groove at a boundary between the plurality of thin film integrated circuit devices;
Introducing a gas or liquid containing halogen fluoride into the groove and etching at least the surface of the lower single crystal silicon layer on the thin film integrated circuit device side, thereby separating the plurality of thin film integrated circuit devices,
A manufacturing method of a non-contact type thin film integrated circuit device, wherein an antenna is formed around the separated thin film integrated circuit device.
前記フッ化ハロゲンは、ＣｌＦ３（三フッ化塩素）であることを特徴とする非接触型薄膜集積回路装置の作製方法。 In claim 12 or 13,
The method for manufacturing a non-contact thin film integrated circuit device, wherein the halogen fluoride is ClF 3 (chlorine trifluoride).
前記アンテナは、Ａｇ、Ａｕ、Ａｌ、Ｃｕ、Ｚｎ、Ｓｎ、Ｎｉ、Ｃｒ、Ｆｅ、Ｃｏ又はＴｉを含むことを特徴とする非接触型薄膜集積回路装置の作製方法。 In any one of Claims 12 to 14,
The method for manufacturing a non-contact thin film integrated circuit device, wherein the antenna contains Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co, or Ti.
前記アンテナは、可撓性を有する基体上に形成することを特徴とする非接触型薄膜集積回路装置の作製方法。
In any one of Claims 12 thru | or 15,
A method for manufacturing a non-contact thin film integrated circuit device, wherein the antenna is formed over a flexible substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004352242A JP4912586B2 (en) | 2003-12-19 | 2004-12-06 | Method for manufacturing thin film integrated circuit device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003423888 | 2003-12-19 | ||
| JP2003423888 | 2003-12-19 | ||
| JP2004352242A JP4912586B2 (en) | 2003-12-19 | 2004-12-06 | Method for manufacturing thin film integrated circuit device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005203751A JP2005203751A (en) | 2005-07-28 |
| JP2005203751A5 true JP2005203751A5 (en) | 2008-01-24 |
| JP4912586B2 JP4912586B2 (en) | 2012-04-11 |
Family
ID=34829380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004352242A Expired - Fee Related JP4912586B2 (en) | 2003-12-19 | 2004-12-06 | Method for manufacturing thin film integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4912586B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007128433A (en) * | 2005-11-07 | 2007-05-24 | Philtech Inc | Rf powder and its manufacturing method |
| US7736948B2 (en) * | 2005-11-11 | 2010-06-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing a plurality of semiconductor devices and carrier substrate |
| JP2008109116A (en) * | 2006-09-26 | 2008-05-08 | Dainippon Printing Co Ltd | Organic semiconductor element, manufacturing method of the organic semiconductor element, organic transistor array and display |
| JP2008113632A (en) * | 2006-11-07 | 2008-05-22 | Hitachi Ltd | Rfid tag for biological implantation and inserting tool body thereof |
| US8154456B2 (en) | 2008-05-22 | 2012-04-10 | Philtech Inc. | RF powder-containing base |
| US8188924B2 (en) | 2008-05-22 | 2012-05-29 | Philtech Inc. | RF powder and method for manufacturing the same |
| US9490179B2 (en) | 2010-05-21 | 2016-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and semiconductor device |
| US11050144B1 (en) * | 2020-05-08 | 2021-06-29 | W. L. Gore & Associates, Inc. | Assembly with at least one antenna and a thermal insulation component |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000020665A (en) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | Semiconductor device |
| JP4748859B2 (en) * | 2000-01-17 | 2011-08-17 | 株式会社半導体エネルギー研究所 | Method for manufacturing light emitting device |
| JP4524561B2 (en) * | 2001-07-24 | 2010-08-18 | セイコーエプソン株式会社 | Transfer method |
-
2004
- 2004-12-06 JP JP2004352242A patent/JP4912586B2/en not_active Expired - Fee Related
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