JP2005151535A - Terminal apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for realizing a low cost, low power consumption, and a small sized mobile communication terminal system by integrating memory systems and peripheral circuits of a DSP and a CPU. <P>SOLUTION: The mobile communication terminal system is realized by a DSP/CPU core 601 integrated as a single bus master, an integrated external bus interface 606, a DSP/CPU integrated chip 600 provided with an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize the mobile communication terminal system which is low in cost and power consumption, and small in size. However, in conventional techniques: (1) the system with a DSP and a CPU independent of each other requires two external memory systems, though cost reduction, power saving, and downsizing are three very important factors for a mobile communication terminal; (2) two peripheral units for data input/output data are also required for the DSP and the CPU, respectively. Further, extraneous communication overhead occurs between the DSP and the CPU. The aforementioned problems are solved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a terminal device for a mobile communication system such as a digital cellular mobile phone, and particularly data processing such as a programmable microprocessor (hereinafter referred to as CPU) and a digital signal processor (hereinafter referred to as DSP). The present invention relates to a mobile communication baseband system implementation method using an apparatus.

  An outline of processing in a mobile communication system related to the present invention will be described with reference to FIG. FIG. 1 shows a user 102, a communication terminal 101, and a base station 100.

  The user 102 accesses the base station 100 using the communication terminal 101 and receives various services. Since communication with other communication terminals is performed via the base station 100, communication processing between the communication terminal and the base station is essential.

  The communication terminal 101 includes a user interface / system control unit 109 having a user interface function and a system control function, a communication protocol processing unit 110 having a communication protocol processing function, a speech coding / decoding processing function, and a channel coding / decoding processing function. , A coding / decoding processing unit 111 having a modulation / demodulation processing function, an analog front end (AFE), and an AFE / RF circuit unit 105 having an RF circuit. Note that a microphone (MIC) 103 and a speaker (SPK) 104 are connected to the communication terminal 101. The base station 100 includes a system control unit 112 having a system control function, a communication protocol processing unit 113 having a communication protocol processing function, a channel coding / decoding processing function, a code decoding processing unit 114 having a modulation / demodulation function, and an analog front end. (AFE) and an AFE / RF circuit unit 106 having an RF circuit.

  There are roughly two ways in which the communication terminal 101 communicates with the base station 100. One is a case where user data such as voice is exchanged, and the other is a case where control data for system operation is exchanged.

  When exchanging audio data, it is as follows. The audio data input from the microphone (MIC) 103 is converted into digital data, and then compressed by the audio encoding process of the encoding / decoding processing unit 111. The compressed audio data is modulated by the modulation processing of the code decoding processing unit 111 after the information for error correction is added by the channel coding processing of the code decoding processing unit 111. The above processing is performed in the digital domain. The modulated digital sound is converted into analog data by the analog front end (AFE) of the AFE / RF circuit unit 105, and is transmitted from the antenna 107 on the high frequency radio wave by the RF circuit of the AFE / RF circuit unit 105. This radio wave is demodulated once after it is received by the antenna 108 of the base station 100. Then, it is modulated again at the frequency assigned to the communication partner (in the case of frequency division multiplexing), and retransmitted from the base station to the communication partner at the timing of the time slot assigned to the communication partner (in the case of time division multiplexing). .

  Next, a case where control data for system operation is exchanged will be described. In this case, the communication protocol processing unit 110 in the communication terminal 101 and the communication protocol processing unit 113 in the base station 100 exchange data. A virtual logical connection is formed between the two. This virtual logical connection is realized by the following physical connection. For example, when the base station 100 issues an instruction to the communication terminal, it is as follows. The instruction data according to a predetermined protocol is subjected to channel coding processing and modulation processing by the code decoding processing unit 114. Then, the analog data is converted into analog data by the analog front end (AFE) of the AFE / RF circuit unit 106 and transmitted from the antenna 108 on the radio wave by the RF circuit. The radio wave is received by the antenna 107 of the communication terminal 101 and then converted into baseband digital data through the RF circuit of the RF circuit unit 105 and the analog front end (AFE). Subsequently, the encoding / decoding processing unit 111 performs demodulation processing and communication path decoding processing, and passes them to the communication protocol processing unit 110.

  Heretofore, the two methods of communication terminal 101 communicating with base station 100 and the outline of related processing have been described. These related processes can be roughly divided into two types. Voice coding / decoding processing, channel coding / decoding processing, and modulation / demodulation processing are classified as digital signal processing, and are suitable for realization by dedicated hardware or a programmable DSP (Digital Signal Processor). On the other hand, the communication protocol processing is very complicated and is suitable for realization with software using a high-level language such as C language.

  Based on such facts, among the baseband processing of mobile communication terminals, speech coding / decoding processing, channel coding / decoding processing, and modulation / demodulation processing are recently performed by a DSP, and communication protocol processing is performed by a CPU (general purpose CPU). Microprocessors have been proposed (Japan Industrial Technology Center / Seminar document “Latest information on GSM / systems / terminals / services” May 18-19, 1995: “Devices for GSM telephone terminals” Development Trend ", pp. 118-130, Nippon Philips Co., Ltd.).

Japan Industrial Technology Center, Seminar Material "Latest Information on GSM / Systems, Terminals and Services" May 18-19, 1995: "Development Trends of Devices for GSM Telephone Terminals", pp. 118-130, Nippon Philips Co., Ltd.

  FIG. 2 shows an example of a mobile communication terminal configured using a DSP and a CPU (not the above known example itself), which the inventor has examined based on the above known example. This mobile communication terminal is for GSM (Global System for Mobile communications) which is a specification of a digital cellular telephone in Europe. 2 includes a DSP chip 223, a DSP RAM (Random Access Memory) 200, a DSP ROM (Read Only Memory) 201, a CPU chip 227, a baseband analog front end (AFE) 202, and a high frequency modulation / demodulation. 210, power amplifier (PA) 212, antenna 213, duplexer 214, low noise amplifier (LNA) 215, microphone 208, amplifier Amp, speaker 209, drive circuit Dri, frequency synthesizer 216, system timing circuit 219, voltage control System clock 221, 1/4 frequency divider 222, sounder DA converter 231, sounder 230, drive circuit Driver, battery monitoring AD converter 232, battery monitoring circuit 233, battery 234, for CPU RAM 239 for CPU OM238, LCD (liquid crystal driving device and a liquid crystal panel) 237, SIM (Subscriber Identiy Module) 236, and a keyboard 235. A baseband analog front end (AFE) 202 includes a PA (Power AmP) DA converter 203, an I / Q AD / DA converter 204, an AGC (Auto Gain Control) DA converter 205, and an audio AD. A DA converter 206 and an AFC (Auto Frequency Control) DA converter 207 are included. The DSP RAM (200) and the DSP ROM (201) are connected to the DSP chip 223 via the DSP external bus 240.

  The function and operation of this terminal will be briefly described below. At the time of audio transmission, the audio input from the microphone 208 is amplified by the amplifier Amp, then sampled by the audio AD converter 206 and converted into digital data. The sampling rate is 8 kHz and the bit accuracy is 13 bits. The digitized data is sent to the DSP chip 223, subjected to compression coding and communication path coding, and then delivered again to the I / Q DA converter 204 of the analog front end (AFE) 202. Here, the data is modulated and converted into analog data and input to the high frequency modulator / demodulator 210. Then, it is transmitted from the antenna 213 on the RF frequency (up to 800 MHz). Duplexer 214 is used to separate input radio waves and output radio waves. A high frequency sine wave 217 used in high frequency modulation / demodulation is synthesized by a frequency synthesizer 216. The frequency synthesizer 216 is connected to the CPU chip 227 via the signal line 218. The ROM (201) contains a program to be executed by the DSP chip 223, and the RAM (200) is for the work of the DSP chip 223.

  At the time of audio reception, data received by the antenna 213 is input to the high frequency modulator / demodulator 210 via a low noise amplifier (LNA) 215. Here, it is converted into a low-frequency baseband analog signal and passed to the I / Q AD converter 204 of the analog front end (AFE) 202. The data sampled and converted into digital data is sent to the DSP chip 223 for channel decoding and compression decoding.

  Thereafter, the sound is converted into analog data by the audio DA converter 206 and output from the speaker 209. When the user makes a call, the keyboard 235 and the LCD (237) are used. The SIM 236 is a detachable user ID module, and by attaching this to the communication terminal, the terminal can be dedicated to that user. The ROM (238) contains a program to be executed by the CPU chip 227, and the RAM (239) is for work of the CPU chip 227. The battery 234 is a main battery of the entire terminal, and the CPU chip 227 monitors the remaining amount through the battery monitoring circuit 233 and the battery monitoring AD converter 232. When a call is received, the CPU chip 227 sounds the Sounder 230 via the Sounder DA converter 231.

  The basic clock 13 MHz of this terminal is supplied from the voltage control system clock 221. The system timing circuit 219 generates necessary system timing signals 241 and 220 from the basic clock and distributes them within the terminal. The basic clock is also supplied to the DSP chip 223 and the CPU chip 227. It is said that 20 to 50 MIPS (Mega Instructions Per Second) is required for DSP processing in GSM. In FIG. 2, a DSP (Phase Locked Loop) circuit 225 mounted in the DSP chip is used to operate the DSP chip at 52 MHz, which is four times the basic clock 13 MHz. On the other hand, CPU processing in GSM is said to be 1-2 MIPS. Therefore, in FIG. 2, the 1/4 frequency divider 222 generates 3.25 MHz which is a quarter of the basic clock 13 MHz, and the CPU is operated at this rate.

  The basic clock of the terminal, 13 MHz, needs to be strictly matched with the base station master clock, 13 MHz. This is accomplished as follows. First, strict frequency information is received from the base station. Based on this information, the DSP chip 223 controls the voltage control system clock 221 via an AFC (Auto Frequency Control) DA converter 207 to adjust the frequency. In some cases, the base station may instruct the terminal to output radio waves. At this time, the DSP chip 223 drives the DA converter 203 for PA (Power Amp) to adjust the output of the power amplifier (PA) 212.

  Further, the DSP chip 223 adjusts the gain in the high frequency modulator / demodulator via an AGC (Auto Gain Control) DA converter 205 based on the amplitude information of the received signal.

  Communication between the DSP chip 223 and the CPU chip 227 is performed as follows. The DSP chip 223 is connected to the CPU external bus 229 of the CPU chip via a DSP host interface (HIF (Host InterFace)) 224. The CPU chip 227 can freely read and write internal resources of the DSP chip 223 from the DSP host interface (HIF) 224 via the CPU external bus interface 228 and the CPU external bus 229. When the DSP chip 223 wants to contact the CPU chip 227, an INT (INTerrupt) 226 signal is used.

  However, in the conventional technique using two independent DSPs and CPUs as described above, two memory systems are required for the DSP and the CPU. In the known example, all the DSP memories are on-chip. However, this is because the GSM system has just been introduced and the required DSP memory capacity is small so far. In the future, when half-rate speech coding technology is fully adopted as the number of subscribers increases, the terminal needs to support both full rate and half rate. At this time, both speech encoding programs need to be installed in the DSP. Furthermore, because the current full-rate sound quality is poor in the GSM system, enhanced full-rate speech coding is being studied. If this becomes a reality, three speech coding programs must be implemented. Further, a DSP program for added value such as a voice recognition program for voice dialing is likely to be implemented as a communication terminal differentiation technique. In this way, it is not practical in terms of cost to make all DSP programs expected to increase in the future on-chip.

  Therefore, it is considered that an external memory for DSP is inevitable in the future. However, in a mobile communication terminal, cost reduction, power consumption reduction, and size reduction are very important, and therefore, using two external memories is a big problem.

  In addition, two peripheral devices for data input / output are required for the DSP and the CPU. For this reason, there was an extra communication overhead between the DSP and the CPU.

  In view of the above problems, an object of the present invention is to propose a method for realizing a low-cost, low power consumption, small-size mobile communication terminal system by integrating a DSP and CPU memory system and peripheral circuits. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a mobile communication terminal system is realized by a DSP / CPU integrated chip having a DSP / CPU core integrated as one bus master, an integrated external bus interface, and an integrated peripheral circuit interface.

  In addition, in order to speed up the external memory access of the DSP, internal memory and external memory programs and data are arranged according to the processing of the mobile communication terminal.

  Furthermore, a function of transferring a plurality of samples in parallel is used for speeding up the peripheral circuit access of the DSP.

  In generating a program for a microprocessor used in the mobile communication terminal, the address register of the digital signal processor that realizes the DSP function is mapped to a subset of the registers of the central processing unit that realizes the CPU function. Pass arguments to a subset of registers in the processing unit.

  In addition, a mobile communication terminal that exchanges data with a base station and performs wireless communication includes a data processing device that executes a program stored in a memory, an area that stores a program for performing speech encoding processing, and a speech composite An area for storing a program for performing an encryption process, an area for storing a program for performing a channel encoding process, an area for storing a program for performing a channel decoding process, and communication with a base station And a memory having an area for storing a program for performing protocol control and an area for storing a program for performing interface control with a user, each area of the memory being an address of the data processing device Place in space.

  The data processing device includes: a digital signal processor that performs voice encoding processing, voice decoding processing, channel encoding processing, and channel decoding processing; protocol control for communication with a base station; And a central processing unit that executes the interface control of the semiconductor device, and is preferably formed on one semiconductor substrate.

  In order to increase the processing speed of the digital signal processor, an area for storing a program for performing the speech encoding process, an area for storing a program for performing the speech decoding process, and a channel encoding process The area for storing the program for performing the communication and the area for storing the program for performing the communication path complexing process may be stored in a memory built in the data processing apparatus.

  For programs that do not require high-speed processing, that is, the data processing device includes an area for storing a program for performing protocol control for communication with a base station and an area for storing a program for interface control with a user. It may be stored in a memory attached externally.

  The data processing apparatus further includes an analog / digital conversion circuit and a serial input / output circuit that interfaces with the digital / analog conversion circuit in the address space of the central processing unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, there is an advantage that a low-cost, low power consumption, small-size mobile communication terminal system can be realized by integrating a DSP function and CPU function memory system and peripheral circuits.

  In addition, since the internal memory and the external memory that are shared can be arbitrarily distributed between the DSP function and the CPU function, the mounted memory can be used efficiently without waste.

  Further, since there is no extra overhead for communication between the DSP function and the CPU function, the mobile communication terminal system can be configured efficiently.

[DSP / CPU integrated chip]
The tightly coupled DSP / CPU integrated chip on which the present invention is based will be described. Details are described in the previous application by the inventors, Japanese Patent Application No. 7-132906. An example of this tightly coupled DSP / CPU integrated chip is shown in FIG. The DSP / CPU integrated chip 300 surrounded by a dotted line shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique. In FIG. 3, a DSP / CPU integrated chip 300 surrounded by dotted lines, an external RAM (Random Access Memory) 326, an external ROM (Read Only Memory) 327, an external address bus (EA) 325, and an external data bus (ED) 324 are shown. It is shown.

  The DSP / CPU integrated chip 300 includes a DSP / CPU tightly coupled integrated core 305, an internal memory X304, an internal memory Y303, an integrated bus interface 418, a DMAC (Direct Memory Access Controller) 317, an integrated peripheral bus interface 319, a DSP peripheral circuit 322, and a CPU. The peripheral circuit 323 is configured. These components include three types of internal memory address buses (X address bus (XA) 302, Y address bus (YA) 301, I address bus (IA) 314), and three types of internal memory data buses (X data bus). (XD) 315, Y data bus (YD) 316, I data bus (ID) 313), integrated peripheral address bus (PA) 320, and integrated peripheral data bus (PD) 321.

  The DSP / CPU tightly coupled integrated core 305 includes a CPU core 307 and a DSP engine 306. In the CPU core 307, an instruction decoder 308, an ALU (arithmetic logic unit) 309, and a register 310 are main components. The DSP engine 306 has no instruction decoder, and an arithmetic unit such as a sum of products 311 and a register 312 are main components.

  The CPU core 307 reads an instruction from any of the internal memory X304, the internal memory Y303, the external RAM 326, and the external ROM 327, and decodes and executes the instruction by the instruction decoder 308. The DSP engine 306 operates in accordance with instructions from the CPU core 307. That is, when executing a DSP instruction, the CPU core 307 and the DSP engine 306 operate in parallel in a coordinated manner.

  However, what is called DSP here is the ability to execute an FIR filter (Finite Response Filter), which is a basic operation of digital signal processing, at 1 cycle / tap. In general, it is necessary to satisfy the following four conditions simultaneously for this purpose. (1) Multiply-accumulate operations can be executed in one cycle, (2) Two data can be accessed simultaneously from memory in one cycle, (3) Supports repeated instructions without overhead, and (4) Modulo addressing mode Need to be. Details of the DSP function are disclosed as well-known information in, for example, “DSP56116 Digital Signal Processor User's Manual” published by Motorola Inc. 1990. From the above four conditions, a simple sum of products and FPU (Floating Point Unit) cannot be said to be a DSP engine here.

  In addition, what is called a CPU here is a standard microprocessor having an architecture capable of efficiently compiling and executing a program written in a high-level language such as C language. For example, the details are disclosed in the third edition “Hitachi Single-Chip RISC Microcomputer SH7032, SH7034 Hardware Manual” issued in March 1994, Hitachi, Ltd.

  As described above, the DSP / CPU tightly coupled integrated core 305 in FIG. 3 has a standard CPU function capable of efficiently compiling and executing a program written in a high-level language such as C language, and has one cycle of FIR filter. It has a DSP function that can be executed with / tap and is controlled by a single instruction stream. Further, since the DSP / CPU tightly coupled integrated core 305 has only one instruction decoder and control system, it is integrated into one when viewed as a bus master. That is, the peripheral circuit and memory hanging on the bus are shared and integrated by the DSP function and the CPU function. Further, both the program for executing the DSP function and the program for executing the CPU function are arranged in the address space of the CPU core 307. FIG. 3 shows a state where the DSP peripheral circuit 322 and the CPU peripheral circuit 323 are integrated via the integrated peripheral bus interface 319. Examples of the DSP peripheral circuit 322 include a serial input / output circuit. Examples of the CPU peripheral circuit 323 include a parallel input / output circuit, a serial input / output circuit, a timer, and an AD conversion circuit. Since the DSP peripheral circuit 322 and the CPU peripheral circuit 323 are integrated, that is, in a common address space, the DSP peripheral circuit 322 and the CPU peripheral circuit 323 can be used for both the DSP function and the CPU function. FIG. 3 also shows how the external RAM 326 and the external ROM 327 are shared by the DSP function and the CPU function via the integrated external bus interface.

[Independent DSP and CPU chip]
Next, for comparison, FIG. 4 shows an example in which two conventional independent DSPs and CPUs are used. FIG. 4 is created by the inventor based on the known examples described in the prior art, and is not a known example itself. 4 includes a DSP chip 400 surrounded by a dotted line, a CPU chip 413 surrounded by a dotted line, a CPU external RAM 430, and a CPU external ROM 431. When the DSP chip and the CPU chip are simply combined into one chip, two areas surrounded by a dotted line become one integrated circuit.

  The CPU chip 413 includes a CPU core 414, an internal memory 418, a CPU peripheral bus interface 421, a CPU external bus interface 422, a DMAC 423, and CPU peripheral circuits 426 and 427.

  These components are connected via an internal address bus (IA) 419, an internal data bus (ID) 420, a CPU peripheral address bus (PA) 424, and a CPU peripheral data bus (PD) 425. The CPU core includes an instruction decoder 415, an ALU 416, and a register 417 as main components, reads an instruction from any of the internal memory 418, the CPU external RAM 430, or the CPU external ROM 431, and decodes and executes the instruction by the instruction decoder. The CPU external bus interface 422, the CPU external RAM 430, and the CPU external ROM 431 are connected through an external address bus (EA) 428 and an external data bus (ED) 429. The DSP chip 400 includes a DSP core 403, a DSP internal memory X404, a DSP internal memory Y405, a DSP peripheral circuit 406, a CPU / DSP interface 410, a Y address bus (YA) 401, an X address bus (XA) 402, an X data bus (XD 411 and Y data bus (YD) 412. The DSP core 403 includes an instruction decoder 407, an arithmetic unit such as a sum of products 408, and a register 409. The DSP core 403 reads a DSP dedicated instruction from either the DSP internal memory X404 or the DSP internal memory Y405, and decodes and executes the instruction by the instruction decoder 407. Although not shown in FIG. 4, when the DSP has a dedicated external memory, the DSP dedicated instruction may be read from there and decoded by the instruction decoder 407 and executed.

  In FIG. 4, an internal address bus (IA) 419 and an internal data bus (ID) 420 are connected to the CPU / DSP interface 410, but the CPU chip 413 and the DSP chip 400 are configured as separate chips. The CPU / DSP interface 410 is connected to an external address bus (EA) 428 and an external data bus (ED) 429.

  Thus, when the DSP chip and the CPU chip are simply combined into one chip, each memory space and peripheral circuit are completely independent and cannot be accessed from each other.

  The characteristics of the tightly coupled DSP / CPU integrated chip on which the present invention is based have been described. Next, features of the mobile communication terminal realized by using the tightly coupled DSP / CPU integrated chip will be described using an embodiment.

[First embodiment: GSM terminal]
First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows an example of a GSM terminal implemented using a tightly coupled DSP / CPU integrated chip. FIG. 5 has basically the same configuration as FIG. 2 described in detail above. The two independent DSP chips 223 and the CPU chip 227 used in the GSM terminal of FIG. 2 are replaced with one tightly coupled DSP / CPU integrated chip. FIG. 5 shows a DSP / CPU integrated chip 500, an integrated AFE (analog front end) 501, a battery 510, a battery monitoring circuit 509, a sounder 511, a high frequency modulation / demodulation circuit 513, a PA (power amplifier) 514, an antenna 515, a duplexer 516, and an LNA (low noise). Amplifier) 517, microphone 518, speaker 519, frequency synthesizer 533, system timing circuit 520, voltage control system clock 523, and integrated modules 527 to 531 connected to an integrated external bus 526.

  The integrated module includes a DSP / CPU shared external RAM 527, a DSP / CPU shared external ROM 528, an LCD 529, a SIM 530, and a keyboard 531. The DSP / CPU integrated chip 500 is the same as the DSP / CPU integrated chip 300 in FIG. The integrated AFE (analog front end) 501 includes a battery monitoring AD converter 502, a DA converter 503 for Sounder, a DA converter 504 for PA, an AD / DA converter 505 for IQ, and an AD / DA converter 506 for voice. , An AFC DA converter 507 is included.

  Battery 510, battery monitoring circuit 509, sounder 511, drive circuit Driver, high frequency modulation / demodulation circuit 513, PA (power amplifier) 514, antenna 515, Duplexer 516, LNA (low noise amplifier) 517, microphone 518, amplifier Amp, drive circuit Dri, Speaker 519, high frequency sine wave 532, frequency synthesizer 533, system timing circuit 520, system timing signals 521 and 541, signal line 522, voltage control system clock 523, battery monitoring AD converter 502, Sounder DA converter 503, PA DA converter 504 for IQ, AD / DA converter 505 for IQ, DA converter 506 for AGC, AD / DA converter 507 for audio, DA converter 508 for AFC, LCD 529, SIM 530 and keyboard 531 are respectively shown in FIG. Electric Pond 234, battery monitoring circuit 233, sounder 230, driving circuit Driver, high frequency modulation / demodulation circuit 210, PA (power amplifier) 212, antenna 213, Duplexer 214, LNA (low noise amplifier) 215, microphone 208, amplifier Amp, driving circuit Dri, speaker 209, frequency synthesizer 216, system timing circuit 219, system timing signals 220 and 241, signal line 218, voltage control system clock 221, battery monitoring AD converter 232, Sounder DA converter 231, PA DA converter 203, It corresponds to the AD AD / DA converter 204 for IQ, the DA converter 205 for AGC, the AD / DA converter 206 for audio, the DA converter 207 for AFC, the LCD 237, the SIM 236, and the keyboard 235, and the functions and operations are the same. is there. Therefore, since it is the same as that of FIG. 2 demonstrated previously, description of the function and operation | movement of FIG. 5 is abbreviate | omitted. An external RAM 527 and an external ROM 528 are connected to the integrated external bus 526 so that both the CPU function and the DSP function can be accessed.

  FIG. 6 shows details of the relationship among the DSP / CPU integrated chip, the internal memory, and the external memory. In FIG. 6, a DSP / CPU integrated chip 600, an external ROM 611, and an external RAM 612 are connected via an external address bus 609 and an external data bus 610. Also, the DSP / CPU tightly coupled core 601, internal ROM 602, internal RAM 603, and integrated external bus interface 606 are connected to the internal data bus 604 via the internal address bus inside the DSP / CPU integrated chip 600. . Since the DSP / CPU tightly coupled core 601 is integrated as a single bus master, both the DSP function and the CPU function can arbitrarily access any of the internal ROM 602, internal RAM 603, external ROM 611, and external RAM 612. It becomes a feature. Thanks to this configuration, particularly valuable internal memory can be effectively used without waste.

  The DSP / CPU integrated chip 600 is the same as the DSP / CPU integrated chip 300 in FIG. 3 and the DSP / CPU integrated chip 500 in FIG. 5, but those not related to the description are omitted. Therefore, the DSP / CPU tightly coupled core 601 is integrated with the DSP / CPU tightly coupled core 305, the internal bus 604 is integrated with the internal memory data bus ID 313, the internal bus 605 is integrated with the internal memory address bus 605, and the integrated external bus interface 606 is integrated. This corresponds to the external bus interface 318. However, the internal ROM 602 and the internal RAM 603 correspond to the ROM part and the RAM part of the internal memory X304 and the internal memory Y303, respectively.

  The external address bus 609 corresponds to the external address bus (EA) 325, the external data bus 610 corresponds to the external data bus (ED) 324, the external ROM 611 corresponds to the external ROM 327 and the external ROM 528, and the external RAM 612 corresponds to the external RAM 326 and the external RAM 527. The external bus 526 includes both the external address bus 609 and the external data bus 610.

  As described above, in the first embodiment of the present invention, as shown in FIGS. 5 and 6, the external RAM / ROM is completely shared by the DSP and the CPU, so that the DSP dedicated to the DSP existing in FIG. The external bus 240, the external RAM 200, and the external ROM 201 are not necessary. Further, the signals HIF 224 and INT 226 between the DSP chip 223 and the CPU chip 227 are not necessary. That is, the integration can reduce the number of buses, signal lines, and memory chips, so that low cost, low power consumption, and small size can be realized in the mobile communication terminal.

[Second Embodiment: Built-in Cache Memory]
Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the internal RAM of the DSP / CPU integrated chip of the first embodiment is replaced with a cache memory to increase the speed of external memory access.

  In the conventional independent DSP chip, external memories that can be directly connected are limited to SRAM (Static RAM) and ROM. DRAM and RAM / ROM with high-speed access mode could not be connected directly. Further, the accessible data size is limited to 16 bits, and byte (8 bits) access and long word (32 bits) access cannot be performed. This is because the command length and the data length are fixed to 16 bits in the DSP chip used in the mobile communication terminal. This is because 16 bits are sufficient for both the instruction length and data length in speech coding, channel coding and modulation / demodulation processing to which DSP is applied. By limiting the accessible data size to 16 bits, control of external memory access is simplified, and external access can be executed in one cycle if a sufficiently high-speed memory is used.

  On the other hand, some conventional independent CPU chips can directly connect various external memories such as a DRAM and a RAM / ROM having a high-speed access mode.

  For example, it is described in Hitachi, Ltd., March 1994 third edition “Hitachi Single Chip RISC Microcomputer SH7032, SH7034 Hardware Manual”. It is common knowledge that such a CPU chip supports all of byte (8 bits) access, short word (16 bits) access and long word (32 bits) access. This is because it is indispensable for efficiently executing a program written in a high-level language such as C language. However, on the other hand, control of external memory access is complicated, and external access takes at least three cycles.

  As described above, the conventional DSP chip and the CPU chip support different external memory interfaces suitable for respective applications. When the DSP function and the CPU function are integrated as in the present invention, it is desirable to use a conventional CPU type external memory interface. However, there is a problem that external access is slow for the DSP function.

  Therefore, in the second embodiment, the internal RAM of the DSP / CPU integrated chip of the first embodiment is replaced with a cache memory to increase the speed of external memory access. FIG. 7 shows details of the relationship between the DSP / CPU integrated chip, the cache (internal memory), and the external memory when the internal RAM in FIG. 6 is replaced with a cache memory.

  In FIG. 7, a DSP / CPU integrated chip 700, an external ROM 713, and an external RAM 714 are connected via an external address bus 711 and an external data bus 712. Further, a DSP / CPU tightly coupled core 701, an internal ROM 702, a cache (internal RAM) 704, a DMAC 705, and an integrated external bus interface 708 are connected to the DSP / CPU integrated chip 700 via an internal data bus 706 and an internal address bus 707. Is shown. 6 except that a cache (internal RAM) 704 and a cache controller 703 are incorporated in the DSP / CPU integrated chip instead of the internal RAM 704 in FIG. 7 shows the DMAC 705, the DMAC is not shown in FIG. Since this is not necessary for the explanation in FIG. 6, it is simply omitted. As shown in FIG. 3, the DSP / CPU integrated chip has a built-in DMAC. However, the connection relationship between the cache controller 703 and the DMAC 705 is applied only to FIG.

  When the DSP / CPU tightly coupled core 701 accesses an address supported by the cache function, the following occurs. First, the cache 704 checks whether the data at the address is in the cache 704. If there is, the data in the cache 704 is accessed. If there is not, the cache 704 informs the cache control 703, and the cache controller 703 activates the DMAC 705, and from the external memories 713 and 714, a plurality of neighboring data including the address (often in the range of 500B to 1kB) are stored in the cache 704. And supplied to the DSP / CPU tightly coupled core 701.

  Programs and data references are local. In other words, when a certain address is referred to, there is a very high possibility that a neighboring address will be referred to next. Therefore, if the mechanism using the cache is used, the external memories 713 and 714 can be accessed at the same rate as the internal memory on average. Such a cache is disclosed, for example, in the first edition “Supper RISC engine SH7604 hardware manual” issued in September 1994 by Hitachi, Ltd. However, a cache memory such as a microprocessor described in the above manual has a data amount of 16B (1 line size of the cache memory) when there is no corresponding data in the cache memory (in the case of a miss hit). Byte) etc.

  Thus, by replacing the internal RAM of the DSP / CPU integrated chip with the cache memory, the problem that the external access is slow for the DSP function can be solved.

[Third embodiment: arrangement of programs]
Next, a third embodiment of the present invention will be described with reference to FIG. 5, FIG. 6, FIG. 8, and FIG. In the third embodiment, the problem that the external access is slow for the DSP function is solved by considering the allocation of the memory.

  FIG. 6 shows details of the relationship among the DSP / CPU integrated chip, the internal memory, and the external memory in the mobile communication terminal of FIG. Since the DSP / CPU tightly coupled core 601 is integrated as one bus master as already described with reference to FIG. 6, both the DSP function and the CPU function are any of the internal ROM 602, the internal RAM 603, the external ROM 611, and the external RAM 612. Can also be accessed arbitrarily. That is, there is no distinction between the internal memory and the external memory for DSP or CPU, and they are completely shared resources.

  However, when considering application to mobile communication terminals, conscious use of internal memory and external memory is important. FIG. 8 shows an example of proper use. FIG. 8 shows a DSP / CPU integrated chip 800, an internal ROM 801, an internal RAM 802, an external ROM 803, and an external RAM 804. These correspond to the DSP / CPU integrated chip 600, the internal ROM 602, the internal RAM 603, the external ROM 611, and the external RAM 612 of FIG. In the memory arrangement of FIG. 8, programs and fixed data using DSP functions such as voice encoding / decoding, channel encoding / decoding and modulation / demodulation are stored in the internal ROM 801 using CPU functions such as system control, communication protocol, and user interface. A program and fixed data for the program are arranged in the external ROM 803.

  By adopting such a program arrangement, the DSP function does not need to access the external memory, and the problem can be overcome.

  However, a case where the program using the DSP function and the fixed data cannot be stored in the internal ROM 801 may be considered. In such a case, the memory allocation shown in FIG. 9 is effective. FIG. 9 shows a DSP / CPU integrated chip 900, an internal ROM 901, an internal RAM 902, an external ROM 903, and an external RAM 904. These correspond to the DSP / CPU integrated chip 600, the internal ROM 602, the internal RAM 603, the external ROM 611, and the external RAM 612 of FIG. The memory arrangement in FIG. 9 is basically the same as the allocation in FIG. The difference is that in FIG. 9, a portion using a DSP function such as voice encoding / decoding, channel encoding / decoding, and modulation / demodulation, and fixed data, which does not require high-speed access, is arranged in the external ROM 903. is there.

  For example, a large code table of about 10 kilobytes is searched for speech encoding. At this time, codes are read one by one from the code table and processed, but it may take several hundred cycles per code. Therefore, even if this large code table of about 10 kilobytes is placed in the external memory and several cycles are required for access, it is only a few percent overhead. Also included are programs that use DSP functions such as speech coding / decoding, channel coding / decoding, and modulation / demodulation, which are not product-sum operations, but use functions similar to a CPU called housekeeping processing. It is. Such processing part generally has a small processing amount and a large program size. Such a program part may be arranged in the external ROM 903.

  As shown in FIG. 9, the problem that the external memory access is delayed for the DSP function can be solved by locating a part that does not require high speed access in the program and fixed data using the DSP function in the external ROM.

[Fourth embodiment: high-speed access mode memory interface]
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 5, 10A and 10B, and FIG. The fourth embodiment is an example in which a memory supporting a high-speed access mode that has not been used in a conventional DSP is directly connected as an external memory of the DSP / CPU integrated chip of the first and second embodiments.

  Since there are many memories that support the high-speed access mode, an example in which a burst ROM is directly connected will be described here for specific explanation. However, the present invention is not limited to the burst ROM, but includes a memory (synchronous DRAM, synchronous SRAM, etc.) that supports all high-speed access modes. In FIG. 10A, the external address is 20 bits and the external data is 8 bits, but this is also for the purpose of embodying the description, and the present invention is applied to the bit width of any external address and the bit width of any external data.

  FIG. 10A shows the details when the DSP / CPU integrated chip and the external burst ROM in the mobile communication terminal of FIG. 5 are connected. In FIG. 10A, the DSP / CPU integrated chip 1000 and the external burst ROM 1009 are directly connected via an integrated external address bus 1007 and a data bus 1008. These correspond to the DSP / CPU integrated chip 600, the external ROM 611, the external address bus 609, and the data bus 610 of FIG. In the DSP / CPU integrated chip 1000, a DSP / CPU tightly coupled core 1001, an internal ROM 1002, an internal RAM 1003, and an integrated external bus interface 1006 are connected via an internal data bus 1004 and an internal address bus 1005. . These correspond to the DSP / CPU tightly coupled core 601, internal ROM 602, internal RAM 603, integrated external bus interface 606, internal data bus 604, and internal address bus 605 in FIG. Signals for controlling the external burst ROM 1009 from the DSP / CPU integrated chip 1000 include a chip select signal (/ CS2) 1010 and a read signal (/ RD) 1011. These signals are input to the chip enable terminal (/ CE) and output enable terminal (/ OE) of the burst ROM 1009. FIG. 10B shows a time chart of signals between the DSP / CPU integrated chip 1000 and the external burst ROM 1009.

  FIG. 11 shows an example 1100 of a memory map of the DSP / CPU integrated chip. In this memory map 1100, a burst ROM can be directly connected to the chip select (/ CS2) space. That is, when the DSP / CPU tightly coupled core 1001 of FIG. 10A accesses the space of this chip select (/ CS2), the chip select (/ CS2) 1010 becomes active low, and the read signal (/ RD) 1011 is shown in the time chart. Perform the action.

  In the case of accessing 4 consecutive data in the burst ROM, the remaining 3 data can be accessed at a high speed although there is some overhead in accessing the first first data. This will be described with reference to FIG. 10B. After the chip select signal (/ CS2) 1010 goes low and the burst ROM I009 becomes active, four consecutive data using the upper bits A2 to A19 (excluding the lower 2 bits) of the address are simultaneously generated in the burst ROM. Accessed. Thereafter, the four data accessed using the lower two bits A0 and A1 of the address are sequentially read out of the burst ROM. The read data is read into the DSP / CPU integrated chip 1000 at the rising edge of the read signal (/ RD) 1011.

  In the example of FIG. 10B, it takes 6 cycles to read the first data. This is because it includes the time to access the above-mentioned continuous four data at once in the burst ROM. However, the subsequent three data can be read in one cycle. Therefore, the effective access cycle is (6 + 1 * 3) /4=2.25 cycles. Therefore, it is 25% faster than the case where three cycles are required with an ordinary external ROM.

  By directly connecting a memory that supports such a high-speed access mode, it is possible to solve the problem that the external memory access is slow for the DSP function. Further, when the fourth embodiment and the second embodiment using a cache memory are combined, the overhead when the cache memory does not hit can be reduced.

[Fifth Embodiment: DRAM Interface]
Next, a fifth embodiment of the present invention will be described with reference to FIGS. 5, 12A, 12B, 12C and FIG. The fifth embodiment is an example in which a DRAM which has not been used in a conventional DSP is directly connected as an external memory of the DSP / CPU integrated chip of the first and second embodiments.

  FIG. 12A shows an example in which a DRAM (Dynamic RAM) is directly connected as one of external RAMs to add new added value to the mobile communication terminal. FIG. 12A shows the details when the DSP / CPU integrated chip and the external DRAM are connected in the mobile communication terminal of FIG. In FIG. 12A, a DSP / CPU integrated chip 1200 and an external DRAM 1209 are directly connected via an integrated external address bus 1207 and a data bus 1208. These correspond to the DSP / CPU integrated chip 600, the external RAM 612, the external address bus 609, and the data bus 610 of FIG. In the DSP / CPU integrated chip 1200, a DSP / CPU tightly coupled core 1201, an internal ROM 1202, an internal RAM 1203, and an integrated external bus interface 1206 are connected via an internal data bus 1204 and an internal address bus 1205. . These correspond to the DSP / CPU tightly coupled core 601, internal ROM 602, internal RAM 603, integrated external bus interface 606, internal data bus 604, and internal address bus 605 in FIG. Signals for controlling the external DRAM 1209 from the DSP / CPU integrated chip 1200 include a row address selection signal (/ RAS) 1210, a column address selection signal (/ CAS) 1211, and a write signal (/ WR) 1212. These signals are input to corresponding terminals of the external DRAM 1209. 12B and 12C are time charts of signals between the DSP / CPU integrated chip 1200 and the external DRAM 1209. FIG.

FIG. 11 shows an example 1100 of a memory map of the DSP / CPU integrated chip. In this memory map 1100, a DRAM can be directly connected to the chip select (/ CS3) space. That is, when the DSP / CPU tightly coupled core 1201 in FIG. 12A accesses the space of this chip select (/ CS3), a row address selection signal (/ RAS)
1210, a column address selection signal (/ CAS) 1211 and a write signal (/ WR) 1212 perform the operations shown in the time charts of FIGS. 12B and 12C.

  In the present invention, the large capacity DRAM directly connected in this way can be directly accessed from the DSP function. The mobile communication terminal shown in FIG. 5 can easily add added value such as an answering machine function. In the mobile communication terminal, the voice data to be communicated is compressed to 4 kbit / sec to 13 kbit / sec. Therefore, as shown in FIG. 12A, for example, when one 4 Mbit DRAM chip is used, the voice is 5 minutes to 17 minutes. Can be stored.

[Sixth Embodiment: Speeding Up Data Transfer of Peripheral Circuit]
Next, a sixth embodiment of the present invention will be described with reference to FIG. 5, FIG. 13A, 13B and FIG. The sixth embodiment is intended to increase the data transfer speed of the integrated peripheral circuit of the first embodiment.

  In the conventional independent DSP chip, the peripheral circuits are few in number and type and are directly connected to the internal data bus, enabling high-speed data transfer. On the other hand, the conventional independent CPU chip has many peripheral circuits and various types. However, on the other hand, the data transmission rate is low because it is necessary to go through a peripheral circuit interface.

  In the DSP / CPU integrated chip of the present invention, the peripheral circuit for the DSP function is connected to the peripheral circuit for the CPU function via the integrated peripheral circuit interface. For this reason, data transfer of the peripheral circuit for the DSP function may be delayed.

  Therefore, in the sixth embodiment, a plurality of samples are transferred in parallel to achieve high-speed data transfer in the integrated peripheral circuit of the first embodiment.

  FIG. 13A shows details of connection between the DSP / CPU integrated chip 1300 and the integrated baseband AFE 1313 in the mobile communication terminal of FIG. These correspond to the DSP / CPU integrated chip 500 and the integrated AFE 501 in FIG. In particular, FIG. 13A shows only the data transfer portion related to the exchange with the high frequency modulator / demodulator.

  In the DSP / CPU integrated chip 1300, a serial input / output circuit (SIO1) 1301, a serial input / output circuit (SIO2) 1302, and an integrated peripheral bus 1303 are related. These correspond to the DSP peripheral circuit 322, the integrated peripheral address bus (PA) 320, and the integrated peripheral data bus (PD) 321 of FIG. In FIG. 13A, the serial input / output circuit (SIO1) 1301 is used for both input and output, but the serial input / output circuit (SIO2) 1302 is used only for the input function. That is, the DSP / CPU integrated chip 1300 is configured to have one output and two inputs with respect to the integrated baseband AFE 1313.

  In the integrated baseband AFE 1313, a serial interface 1319, a GMSK (Gaussian Minimum Shift Keying) modulator 1316, an I signal DA converter 1318, a Q signal DA converter 1317, an I signal AD converter 1315, and a Q signal AD converter Reference numeral 1314 denotes an element related to the present embodiment. The high-frequency modulator / demodulator and the integrated baseband AFE 1313 exchange I / Q signals that are analog signals.

  The DSP / CPU integrated chip 1300 and the integrated baseband AFE 1313 are connected to signal lines TXD1 (1304), STS1 (1305), STCK1 (1311), RXD1 (1306), SRS1 (1310), SRCK1 (1311), RDX2 (1309), and SRS2. (1308) and SRCK2 (1311). A timing chart of these signal lines is shown in FIG. 13B.

  Further, signals on the signal line 1311 and the signal line 1312 in FIG. 13A are supplied from the system timing circuit 520 in FIG. A signal line 1312 is used to control the serial interface 1319. A signal line 1311 is a basic clock for data transfer, and is supplied to both the DSP / CPU integrated chip 1300 and the integrated baseband AFE 1313.

  Next, details of the transfer will be described. First, consider a case where data is transferred from the DSP / CPU integrated chip 1300 to the integrated baseband AFE 1313. At this time, three signal lines are used, TXD1 (1304), STS1 (1305), and STCK1 (1311). STCK1 (1311) is a basic clock for data transfer supplied from the system timing circuit 520 of FIG. 5 as described above. Here, 16-bit digital data is transferred bit by bit in synchronization with the basic clock. Of course, data of any bit width can be transferred in the same diagram.

  TXD1 (1304) is a 1-bit data bus for transmission. STS1 (1305) is a frame synchronization signal line, and data is sequentially output bit by bit on TXD1 (1304) for 16 clocks from the next clock in which this signal is output as a pulse. The timing at this time is shown in FIG. 13B. 16 bits of data D15 to D0 from the next clock from which the pulse of STS1 (1305) is output are output on TXD1 (1304) one bit at a time in order from the most significant bit D15.

  Next, consider a case where the DSP / CPU integrated chip 1300 receives data from the integrated baseband AFE 1313. Since two signal data of the I signal and the Q signal are received, the I signal is considered first. At this time, three signal lines RXD1 (1306), SRS1 (1310), and SRCK1 (1311) are used.

SRCK1 (1311) is a basic clock for data transfer supplied from the system timing circuit 520 of FIG. 5 as described above. Again, 16-bit digital data is transferred bit by bit in synchronization with the basic clock. Of course, data of any bit width can be transferred in the same diagram. RXD1 (1306) is a 1-bit data bus for reception. SRS1 (1310) is a frame synchronization signal line. This signal is input as a pulse to the DSP / CPU integrated chip 1300, and the data on RXD1 (1304) is sequentially bit by bit for 16 clocks. Entered. The timing at this time is also shown in FIG. 13B.
From the next clock to which the pulse of SRS1 (1306) is input, 16 bits of data D15 to D0 are input from RXD1 (1304) one bit at a time in order from the most significant bit D15. The reception of the Q signal is performed in the same manner as the reception of the I signal. The difference is that the I signal is received by the serial input / output circuit (SIO1) 1301, and the Q signal is received by the serial input / output circuit (SIO2) 1302.

  Next, details of the serial input / output circuit (SIO1) 1301 and the serial input / output circuit (SIO2) 1302 in FIG. 13A will be described with reference to FIG. FIG. 14 shows a portion related to the present embodiment in the DSP / CPU integrated chip. The serial input / output circuit (SIO1) 1301 corresponds to the serial input / output circuit (SIO1) 1424, and the serial input / output circuit (SIO2) 1302 corresponds to the serial input / output circuit (SIO2) 1420.

  14 includes a DSP / CPU tightly coupled core 1400, an internal memory X1401, an internal memory Y1402, an integrated peripheral bus interface 1406, a DMAC 1405, a serial input / output circuit (SIO1) 1424, a serial input / output circuit (SIO2) 1420, and an AND circuit 1429. Has been. The DSP / CPU tightly coupled core 1400, the internal memory X1401, the internal memory Y1402, the integrated peripheral bus interface 1406 and the DMAC 1405 are connected via an internal address bus (IA) 1403 and an internal data bus (ID) (32-bit width) 1404. The serial input / output circuit (SIO1) 1424 and the serial input / output circuit (SIO2) 1420 are connected to the integrated peripheral bus interface 1406 via the integrated peripheral buses 1407, 1408, and 1409.

  The integrated peripheral bus comprises an address bus (PA) 1407 and a 32-bit wide data bus (PD), and the PD bus comprises an upper 16-bit PD (31-16) 1408 and a lower 16-bit PD (15-0) 1409. . In FIG. 14, the serial input / output circuit (SIO1) 1424 is the upper 16-bit PD (31-16) 1408 of the integrated peripheral data bus, and the serial input / output circuit (SIO2) 1420 is the lower 16-bit PD (15-0) of the integrated peripheral data bus. ) 1409. Although not shown, the address bus (PA) 1407 is connected to a serial input / output circuit (SIO1) 1424 and a serial input / output circuit (SIO2) 1420.

  A serial input / output circuit (SIO1) 1424 includes a 16-bit data transmission data register (TDR1) 1427, a 16-bit data reception data register (RDR1) 1428, a parallel / serial converter 1425, and a serial / parallel converter 1426. And a control circuit 1423. Also shown are six (three for each transmission and reception) signal lines RXD1 (1430), SRCK1 (1432), SRS1 (1433), TXD1 (1434), STS1 (1435), and STCK1 (1436) that communicate with the outside of the chip. is there. These signal lines correspond to RXD1 (1306), SRCK1 (1311), SRS1 (1310), TXD1 (1304), STS1 (1305), and STCK1 (1311) in FIG. 13A.

  Details of these signal lines have been described above with reference to FIG. 13A.

  The serial input / output circuit (SIO2) 1420 includes a 16-bit data transmission data register (TDR2) 1415, a 16-bit data reception data register (RDR2) 1416, a parallel / serial converter 1417, and a serial / parallel converter 1418. And a control circuit 1419. Also shown are six (three for each transmission and reception) signal lines TXD2 (1431), SRCK2 (1437), SRS2 (1438), and RXD2 (1439) that communicate with the outside of the chip.

  Among these signal lines, SRCK2 (1437), SRS2 (1438), and RXD2 (1439) correspond to SRCK2 (1307), SRS2 (1308), and RXD2 (1309) in FIG. 13A. Details of these signal lines have also been described above with reference to FIG. 13A. However, in FIG. 13A, this serial input / output circuit (SIO2) 1420 is used only for reception. Therefore, three of these signal lines TXD2 (1431), STS2 (1440), and STCK2 (1441) for transmission are not displayed in FIG. 13A.

  First, a case where data is transmitted using the serial input / output circuit (SIO1) 1424 will be described. The 16-bit width transmission data 1424 is input to the data transmission data register (TDR1) 1427 via the upper 16-bit PD (31-16) 1408 of the integrated peripheral data bus. Then, the data is output bit by bit onto the 1-bit data bus TDX1 (1434) through the parallel / serial converter 1425. The control circuit 1423 controls the output cycle and timing using the signal lines STS1 (1435) and STCK1 (1436).

  Next, a case where two 16-bit data received by the serial input / output circuit (SIO1) 1424 and the serial input / output circuit (SIO2) 1420 are transferred in parallel via the 32-bit bus will be described. In the serial input / output circuit (SIO1) 1424, received data is input bit by bit from the RDX1 (1430). The input circuit and timing are controlled by the control circuit 1423 using the signal lines SRS1 (1433) and SRCK1 (1432). The input bit string is converted into 16-bit width parallel data through the serial / parallel converter 1426 and input to the reception data register 1428. When reception data is input to the reception data register 1428 and preparation for transfer is completed, the control circuit 1423 activates an interrupt signal (INT) 1422 to the DMAC.

  On the other hand, in the serial input / output circuit (SIO2) 1420, received data is input bit by bit from the RDX2 (1439). The input circuit and timing are controlled by the control circuit 1419 using the signal lines SRS2 (1438) and SRCK2 (1437). The input bit string passes through the serial / parallel converter 1418 and is converted into parallel data having a 16-bit width and is input to the reception data register (RDR2) 1416. When reception data is input to the reception data register (RDR2) 1416 and ready for transfer, the control circuit 1419 activates an interrupt signal (INT) 1421 to the DMAC. The AND circuit 1429 takes the logical product of the interrupt signal (INT) 1422 and the interrupt signal (INT) 1421 and interrupts the DMAC 1405. That is, at the time when the DMAC 1405 is interrupted, data to be transferred is prepared in the two 16-bit reception data registers RDR1 (1428) and RDR2 (1416). The DMAC treats two 16-bit received data as one 32-bit data and transfers them to the internal memory X1401 or the internal memory Y1402 via the 32-bit wide integrated peripheral data buses 1408 and 1409 and the 32-bit wide internal data bus 1404. be able to.

  As described above, when the sixth embodiment is used, the transfer rate of the serial input / output circuit can be doubled compared to the case of transferring 16-bit data one by one, and the data transfer of the peripheral circuit for the DSP function is possible. Can solve the problem of slowdown.

[Seventh embodiment]
Next, a seventh embodiment of the present invention will be described with reference to FIG. 5, FIG. 15A, 15B and FIG. The seventh embodiment is a variation of the sixth embodiment. In the sixth embodiment, two serial input / output circuits are used for two received signals. In the seventh embodiment, two received signals are time-division multiplexed and only one serial output circuit is used.

  FIG. 15A shows details of connection between the DSP / CPU integrated chip 1500 and the integrated baseband AFE 1511 in the mobile communication terminal of FIG. These correspond to the DSP / CPU integrated chip 100 and the integrated AFE 501 in FIG. FIG. 15A also shows only the data transfer portion related to the exchange with the high frequency modulator / demodulator.

  In the DSP / CPU integrated chip 1500, a serial input / output circuit SIO 11502 and an integrated peripheral bus 1501 are related. These correspond to the DSP peripheral circuit 422, the integration address bus (PA) 320, and the integration data bus (PD) 321 in FIG. In FIG. 15A, the serial input / output circuit SIO11502 is used for both input and output. The DSP / CPU integrated chip 1500 is configured to have one output and one output with respect to the integrated baseband AFE 1511.

  The integrated baseband AFE 1511 includes a serial interface 1505, a GMSK (Gaussian Minimum Sift Keying) modulator 1514, an I signal DA converter 1516, a Q signal DA converter 1515, an I signal AD converter 1513, and a Q signal AD converter. Reference numeral 1512 denotes an element related to the present embodiment. The high frequency modulator / demodulator and the integrated baseband AFE 1511 communicate with each other by an I signal and a Q signal which are analog signals.

  The DSP / CPU integrated chip 1500 and the integrated baseband AFE 1511 are connected via signal lines TXD1 (1503), STS1 (1504), STCK1 (1509), RXD1 (1508), SRS1 (1507), SRCK1 (1509) and IQFLAG (1506). Connected. A timing chart of these signal lines is shown in FIG. 15B. Further, signals on the signal line 1509 and the signal line 1510 in FIG. 15A are supplied from the system timing circuit 520 in FIG. A signal line 1510 is used to control the serial interface 1505. A signal line 1509 is a basic clock for data transfer, and is supplied to both the DSP / CPU integrated chip 1500 and the integrated baseband AFE 1511.

  Next, details of the transfer will be described. The case of transferring data from the DSP / CPU integrated chip 1500 to the integrated baseband AFE 1511 is exactly the same as the example of FIG.

  Next, consider a case where the DSP / CPU integrated chip 1500 receives data from the integrated baseband AFE 1511. Two signal data of an I signal and a Q signal are received. In FIG. 15A, these two signals are time-division multiplexed. Four signal lines RXD1 (1508), SRS1 (1507), SRCK1 (1509), and IQFLAG (1506) are used at this time. SRCK1 1509 is a basic clock for data transfer supplied from the system timing circuit 520 of FIG. 5 as described above. Also in this case, 16-bit digital data is transferred bit by bit in synchronization with the basic clock. Of course, data of any bit width can be transferred in the same diagram. RXD1 (1508) is a 1-bit data bus for reception. SRS1 (1507) is a frame synchronization signal line. This signal is input as a pulse to the DSP / CPU integrated chip 1500, and the data on RXD1 (1508) is sequentially bit by bit for 16 clocks. Entered.

  The timing at this time is also shown in FIG. 15B. In the timing chart, an I signal is input first and then a Q signal is input. First, 16 bits of data I15 to 10 are input from RXD1 (1508) one bit at a time in order from the most significant bit I15 from the next clock to which the first pulse of SRS1 (1507) is input. Then, 16-bit data Q15 to Q0 from the next clock to which the second pulse of SRS1 (1507) is input are input from RXD1 (1508) one bit at a time in order from the most significant bit Q15. . IQFLAG (1506) is used to identify the data being transferred by RXD1 (1508). In FIG. 15A, IQFLAG (1506) is at a high level while the I signal is being transferred.

  Next, details of the serial input / output circuit (SIO1) 1502 in FIG. 15A will be described with reference to FIG. FIG. 16 shows a portion related to the present embodiment in the DSP / CPU integrated chip. The serial input / output circuit (SIO1) 1502 corresponds to the serial input / output circuit (SIO1) 1631.

  FIG. 16 includes a DSP / CPU tightly coupled core 1600, an internal memory X 1601, an internal memory Y 1602, an integrated peripheral bus interface 1606, a DMAC 1605, and a serial input / output circuit SIO 11631. The DSP / CPU tightly coupled core 1600, the internal memory X1601, the internal memory Y1602, the integrated peripheral bus interface 1606, and the DMAC 1605 are connected via an internal address bus (IA) 1603 and an internal data bus (ID) (32-bit width) 1604. The serial input / output circuit (SIO1) 1631 is connected to the integrated peripheral bus interface 1606 via the integrated peripheral buses 1607, 1608, and 1609. The integrated peripheral bus comprises an address bus (PA) 1607 and a 32-bit data bus (PD), and the PD bus comprises an upper 16-bit PD (31-16) 1608 and a lower 16-bit PD (15-0) 1609. .

  The serial input / output circuit (SIO1) 1631 includes two 16-bit data transmission data registers TDRU (1629) and TDRL (1630), two 16-bit data reception data registers RDRU (1614), and RDRL (1615). ) Two multiplexers (MUL) 1628 and 1616, a parallel / serial converter 1627, a serial / parallel converter 1617, and a control circuit 1619. The data transmission data register (TDRU) 1629 and the data reception data register (RDRU) 1614 are connected to the upper 16-bit PD (31-16) 1608 of the integrated peripheral data bus, and the data transmission data register (TDRL) 1630 and the data The reception data register (RDRL) 1615 is connected to the lower 16 bits PD (15-0) 1609 of the integrated peripheral data bus. 7 exchanges (3 transmissions STS1 (1625), STCK1 (1624), TDX1 (1626), 3 receptions SRS1 (1620), SRCK1 (1621), RXD1 (1623) and IQFLAG (1622) ) Signal lines are also shown. Details of these signal lines have been described above with reference to FIG.

  First, a case where data is transmitted using the serial input / output circuit (SIO1) 1631 will be described. First, two 16-bit width transmission data are input to two 16-bit width data transmission data registers TDRU (1629) and TDRL (1630) via a 32-bit integrated peripheral data bus PD (31-0). The

  The TDRU (1629) is input via the upper 16-bit PD (31-16) 1608 and the TDRL (1630) is input via the lower 16-bit PD (15-0) 1609. Subsequently, the multiplexer 1628 selects which of the two transmission data registers is to be transmitted. The selected 16-bit width data passes through the parallel / serial converter 1627 and is output bit by bit on the 1-bit data bus TDX1 (1626). The output cycle and timing are controlled by the control circuit 1619 using the signal lines STS1 (1625) and STCK1 (1624).

  Next, a case where two 16-bit data (I signal data and Q signal data) received by the serial input / output circuit (SIO1) 1631 are transferred in parallel via a 32-bit bus will be described. In the serial input / output circuit (SIO1) 1631, received data is input bit by bit from (RDX1) 1623. The control circuit 719 controls the input cycle and timing using the signal lines SRS1 (1620) and SPCK1 (1621). The input bit string passes through the serial / parallel converter 1617 and is converted into parallel data having a 16-bit width and is input to one of the two reception data registers. Which is input is selected by a multiplexer (MUL) 1616. A control signal for switching the multiplexer (MUL) 1616 is generated by the control circuit 719 based on IQFLAG (1622). Thus, for example, I signal data is input to RDRU (1614) and Q signal data is input to RDRL (1615).

  When the reception data is input to the two reception data registers RDRU (1614) and RDRL (1615) and ready for transfer, the control circuit 719 activates an interrupt signal (INT) 1618 to the DMAC to the DMAC (1605). Interrupt. The DMAC treats two 16-bit received data as one 32-bit data, and either the internal memory X (1601) or the internal memory Y via the 32-bit wide integrated peripheral data buses 1608 and 1609 and the 32-bit wide internal data bus 1604. (1602).

  As described above, when the seventh embodiment is used, the transfer rate of the serial input / output circuit can be doubled as compared with the case of transferring 16-bit data one by one, and the data transfer of the peripheral circuit for the DSP function is possible. Can solve the problem of slowdown.

[Eighth Embodiment: Power Amplifier Control]
Next, an eighth embodiment of the present invention will be described with reference to FIGS. 5, 2, 17A and 17B, FIG. 18, FIG. 19, and FIGS. The conventional GSM mobile communication terminal shown in FIG. 2 has a communication overhead between the DSP and the CPU, and the efficiency of the system configuration has been a problem. The present embodiment shows that the DSP function and the CPU function are integrated in the configuration of the first embodiment, so there is no overhead and the mobile communication terminal system can be configured efficiently.

  In this embodiment, the case of RF amplifier power amplifier control is taken as a specific example. The GSM mobile communication terminal shown in FIGS. 5 and 2 is obliged to control the output of the power amplifier of the RF unit based on an instruction from the base station. In the case of this power amplifier control, communication overhead between the DSP and the CPU frequently occurs in the conventional configuration.

  First, the outline of this overhead will be described with reference to FIG. 1 and FIG. The processing on the communication terminal side of the mobile communication system has already been described with reference to FIG.

  FIG. 18 shows how this processing is realized in the present invention and the conventional example. In a conventional example using two independent DSPs and a CPU, user interface processing, system control and communication protocol processing are realized by a CPU chip, and speech encoding / decoding processing, channel encoding / decoding processing, modulation / demodulation processing, and the like are performed. It was realized with a DSP chip. In order to transmit / receive data to / from the base station, it is necessary to use channel coding / decoding and modulation / demodulation processing realized by a DSP chip. Therefore, the CPU chip needs to communicate with the DSP chip every time data related to communication protocol processing needs to be exchanged with the base station. This communication overhead is illustrated in the conventional example of FIG.

  In the case of output control of the power amplifier of the RF unit, the protocol processing program executed by the CPU chip needs to access the DA converter 203 for controlling the power amplifier PA in FIG. However, physically, the DA converter 203 for PA control is connected to the DSP chip, and the CPU chip needs to communicate with the DSP chip every time it is necessary.

  However, in the present invention, all digital processing such as user interface processing, system control and communication protocol processing, speech coding / decoding processing, channel coding / decoding processing and modulation / demodulation processing is realized by the DSP / CPU integrated chip. Therefore, as shown in FIG. 18, the CPU chip has no overhead between DSP chips, and the system can be configured efficiently.

  This overhead will be described in more detail with reference to FIGS. 20A and 20B. In the GSM mobile communication terminal shown in FIGS. 5 and 2, first, instruction data for output control of the power amplifier of the RF unit is sent from the base station.

  In the conventional example of FIG. 20A, this received data is sent to the DSP chip. FIG. 20A shows the subsequent processing as a flowchart.

First, the DSP chip subjects the received data to demodulation processing and communication path decoding processing. Subsequently, the DSP chip interrupts the CPU chip in order to pass the transmitted data to the protocol processing. At that time, the interrupted CPU chip temporarily stops the program being executed, saves the internal state, and receives received data from the DSP chip. Thereafter, the CPU chip executes a protocol processing program to decode the received data, knows that it is an instruction for output control of the power amplifier, and extracts the control data. The CPU chip then interrupts the DSP chip to access the power amplifier PA control DA converter connected to the DSP chip. At that time, the interrupted DSP chip temporarily stops the program being executed, saves the internal state, and receives an instruction and control data for driving the PA control DA converter from the CPU chip. The DSP chip drives a DSP peripheral circuit for an analog front end AFE that incorporates a PA control DA converter to control the output of the power amplifier. The above is the processing flow in the conventional example. The overhead part is shaded.
On the other hand, in the case of the present invention using the DSP / CPU integrated chip shown in the flowchart of FIG. 20B, this overhead portion is not necessary at all. This is because the DSP function and the CPU function are integrated, so there is no need for communication between the DSP process and the CPU process, and the DSP and CPU peripheral circuits are integrated and the DSP peripheral circuit can be directly accessed from the CPU function.

  Next, details of direct access to the DSP peripheral circuit from this CPU function will be described with reference to FIGS. 17A and 19. FIG. That is, an example in which a protocol processing program executed by the CPU directly accesses the power amplifier PA control DA converter will be described in detail.

  FIG. 17A shows only a portion where the joint portion between the DSP / CPU integrated chip 500 and the DA converter 504 for power amplifier PA control in the communication terminal of FIG. 5 is enlarged and related. In the DSP / CPU integrated chip 1712, a serial input / output circuit SIO 1713, a BIT I / O circuit 1714, and an integrated peripheral bus are related. In the integrated baseband AFE 1700, a serial interface 1701, a power ramping RAM 1703, and a DA converter 1502 for PA control signals are elements related to this embodiment. The Power Ramping RAM 1703 incorporates an output waveform as sample data. FIG. 17A shows a case where the number of samples is six, but of course any number is possible. An example of a waveform 1704 represented by six pieces of built-in data is also shown in FIG. 15A. The integrated baseband AFE 1700 controls the power amplifier with a PA control signal that is an analog signal. The output waveform built in the power ramping RAM 1703 is converted into an analog signal as a PA control signal 1705 and output at the timing specified by the transfer activation signal 1706.

  FIG. 19 shows the timing specified by the transfer activation signal 1706 in FIG. 17A and the required output waveform of the power amplifier. The GSM communication system is a time division system in which one frame (4.615 ms) is composed of 8 time slots (577 us). Transmission is activated for one time slot in one frame (8 time slots).

  Therefore, the timing indicated by Tx in FIG. 19 is the timing specified by the transfer activation signal 1706 in FIG. 17A. Incidentally, Rx in FIG. 19 is a reception timing. The required output waveform of the power amplifier is shown below FIG. As shown in the figure, in the GSM communication system, not only the amplitude of the output waveform but also the rising and falling slopes are strictly defined. The Power Ramping RAM 1703 in FIG. 17A is used to satisfy this definition.

  Returning to FIG. 17A, the description will be continued. The DSP / CPU integrated chip 1712 and the integrated baseband AFE 1700 are connected via signal lines TXD 1710, STS 1709, STCK 1708, and / CTRL 1711.

  A timing chart of these signal lines is shown in FIG. 17B. The signals 1708, 1707 and 1706 in FIG. 17A are supplied from the system timing circuit 520 in FIG. A signal line 1707 is used to control the serial interface 1701. A signal line 1708 is a basic clock for data transfer, and is supplied to both the DSP / CPU integrated chip 1712 and the integrated baseband AFE 1700.

  Next, details of writing data into the power ramping RAM 1703 will be described. The basics of transferring data from the DSP / CPU integrated chip 1712 to the integrated baseband AFE 1700 are the same as those described with reference to FIGS. 13A, 13B, 15A, and 15B. The difference is that this time we need an address that specifies which of the six entries in Power Ramping RAM 1703 to write. For this purpose, FIG. 17A uses a format in which the first 10 bits of the transfer data length of 16 bits are data and the latter 6 bits are addresses. Of course, these specific bit lengths are temporarily set for clarity of explanation, and may actually be any number of bits. There are four signal lines TXD 1710, STS 1709, STCK 1708, and / CTRL 1711 used for the transfer. STCK 1708 is a basic clock for data transfer supplied from the system timing circuit 520 of FIG. 5 as described above. Here, 16-bit digital data is transferred bit by bit in synchronization with the basic clock. Of course, data of any bit width can be transferred in the same diagram. TXD 1710 is a 1-bit data bus for transmission. An STS 1709 is a frame synchronization signal line, and data is sequentially output on the TXD 1710 bit by bit for 16 clocks from the next clock from which this signal is output as a pulse.

  The timing at this time is shown in the lower part of FIG. 17B. 10 bits of data D9 to D0 and 6 bits of addresses A5 to A0 are consecutive from the next clock from which the pulse of STS 1709 is output, and one bit at a time for each clock in order from the most significant bit D9 on the TXD 1710 Is output. Note that the / CTRL 1711 signal is used to distinguish from the normal transfer mode described with reference to FIGS. 13A and 13B and FIGS. 15A and 15B. When the / CTRL 1711 signal is active, 10-bit data is written to the internal resource of the integrated baseband AFE 1700 specified by the 6-bit address. When data is written in the six entries of the power ramping RAM 1703, six 16-bit data having the corresponding six addresses and data may be transferred according to the above procedure.

  As described above, in the case of power amplifier control, processing requiring a DSP function such as product-sum operation is not included at all. Nevertheless, in the conventional example, the DSP chip is interrupted only to access the DSP peripheral circuit. According to the present invention, since the CPU function can directly access the peripheral circuit for DSP, such a useless overhead does not occur.

[Ninth embodiment: ASIC circuit]
Next, a ninth embodiment of the present invention will be described with reference to FIGS. The ninth embodiment is an example in which a high-speed dedicated circuit is added to the DSP / CPU integrated chip on which the first embodiment is based.

  The embodiments so far have been premised on general-purpose and standard DSP / CPU integrated chips. However, it is necessary to incorporate a high-speed dedicated circuit (ASIC circuit Application Specific Integrated Circuit) in order to efficiently realize a system specialized for an application. In the present embodiment, how this is configured in the framework of the present invention will be described. As an example of the ASIC circuit, an AD converter, a DA converter, a serial interface circuit, and the like in the integrated AFE 501 in FIG. 5 can be considered.

  FIG. 21 shows a portion of the DSP / CPU integrated chip related to this embodiment, an external memory, and an external bus. 21 shows a DSP / CPU tightly coupled core 2100, an internal memory X 2102, an internal memory Y 2103, an integrated peripheral bus interface 2116, a DMAC 2101, an integrated external bus interface 2118, an integrated ASIC bus interface 2117, a standard DSP peripheral circuit 2104, and a standard CPU. A peripheral circuit 2105 and an ASIC circuit 2106 are included. The DSP / CPU tightly coupled core 2100, DMAC 2101, internal memory X 2102, internal memory Y 2103, integrated peripheral bus interface 2116, integrated ASIC bus interface 2117 and integrated external bus interface 2118 are connected via an internal address bus 2109 and an internal data bus 2108. Connected. The standard DSP peripheral circuit 2104 and the standard CPU peripheral circuit 2105 are connected to an integrated peripheral bus interface 2116 via an address bus PA 2110 and a data bus PD 2111.

  The ASIC circuit 2106 is connected to the integrated ASIC bus interface 2117 via an address bus AA 2112 and a data bus AD 2113. The external memory 2107 is connected to the integrated external bus interface 2116 via an address bus EA 2114 and a data bus ED 2115. In the configuration of FIG. 21, an integrated ASIC bus interface 2117 is connected to the internal bus in parallel with the integrated peripheral bus interface 2116. The integrated ASIC bus interface 2117 does not need to support various peripheral circuits and can be realized with a simple structure at high speed. In some cases, the ASIC circuit 2106 may be directly connected to the internal bus.

  By preparing a high-speed and simple integrated ASIC bus interface independent of the standard integrated peripheral bus interface in this way, it is possible to incorporate a high-speed dedicated circuit and efficiently realize a system specialized for the application. Can do.

[Tenth embodiment]
Finally, a tenth embodiment of the present invention will be described with reference to FIG. 3, FIG. 22, FIG. 23, and FIG. The present embodiment relates to a compiler creation method for efficiently passing data from a high-level language such as C language executed by the CPU function to an assembler program executed by the DSP function in the DSP / CPU integrated chip.

  FIG. 3 shows the internal structure of a DSP / CPU tightly coupled core on which the present invention is based. As described above, the CPU core 307 and the DSP engine 306 operate in parallel when the DSP function is executed. That is, the CPU core 307 functions as an address calculator of the DSP engine 306.

  FIG. 22 is an enlarged view of a portion related to the present embodiment in the CPU core 307 of FIG. FIG. 22 shows a CPU core 2203 and three internal address buses IA 2202, XA 2201 and YA 2200. In the CPU core 2203, 16 registers 2209 (R0 to R15), SFT (shifter) 2210, ALU 2211, add-ALU (auxiliary ALU) 2212 and program counter 2204 are shown. When the DSP function is executed, four registers R4, R5, R6, and R7 out of the 16 registers 2209 are used for data access via the internal address buses XA 2201 and YA 2200. R4 and R5 are connected to an address bus XA 2201, and R6 and R7 are connected to an address bus YA 2200.

  How this CPU core functions as an address calculator of the DSP engine will be described with reference to FIG. In order to explain the DSP function, an example of a simple product-sum operation is taken here. In the upper part of FIG. 24, an assembler expression 2400 of the product-sum operation realized by the DSP function is shown. The center of FIG. 24 shows the hardware in the DSP / CPU integrated chip used at this time. These are XMEM (internal memory X) 2413, YMEM (internal memory Y) 2412, four CPU core registers (R4 2415, R5 2414, R6 2411 and R7 2410), four DSP engine registers (X0 2416, Y0 2409, M0 2407 and A0 2405), DSP engine multiplier 2408 and DSP engine ALU 2406.

  Four arrows 240, 2402, 2403, and 2404 indicate the related hardware of the assembler representation 2400 of the product-sum operation. The assembler representation 2400 is divided into four parts that specify parallel operation, and four arrows 2401, 402, 2403, and 2404 correspond to each of them. The first part specifies addition, and the contents of A0 2405 and the contents of M0 2407 are added and stored in A0 2405. The second part specifies multiplication, and the contents of X0 2416 and the contents of Y0 2409 are multiplied and stored in M0 2407. The third part designates reading of data from the internal memory X, and the XMEM (internal memory X) 2413 is accessed by using the contents of R5 as an address, and the read data is stored in X0. The fourth part designates the reading of data from the internal memory Y, accesses the YMEM (internal memory Y) 2412 using the contents of R6 as an address, and stores the read data in Y0.

  As described above, in the present embodiment, four of the CPU core registers (R4 2415, R5 2414, R6 2411 and R7 2410) are used as address pointers for the DSP engine. In particular, R4 2415 and R52414 are used as pointers for the internal memory X, and R6 2411 and R7 2410 are used as pointers for the internal memory Y for parallel access.

  Next, consider that the assembler program shown in FIG. 24 is called from FIG. In FIG. 23, this assembler program is called as mac_sss. The program of FIG. 23 is a simple one that takes the product sum of two arrays having four elements. In a DSP program starting with this example, it is natural to pass as the argument the start address of the array for which product-sum is to be executed. Therefore, it is effective to assign the first four arguments of the function to the four CPU core registers used as the address pointer of the DSP engine as a method of passing arguments by the compiler. As a result, in the example of FIG. 23, the leading addresses of the two arrays that take the product-sum are passed to R5 and R6. As is apparent from FIG. 24, R5 and R6 can be used immediately for parallel access of the memory as X and Y pointers, respectively, which is efficient.

  As described above, the assembler program that receives the arguments efficiently uses the DSP function by the register allocation method for the high-level language compiler that allocates the first four arguments of the function to the four CPU core registers used as the address pointer of the DSP engine. Can be executed.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and various modifications can be made without departing from the scope of the invention. It is also possible to combine or replace the embodiments.

1 is a basic configuration diagram of a mobile communication system. It is a block diagram of a GSM mobile communication terminal using a DSP and a CPU. It is a block diagram of a DSP / CPU integrated chip that is tightly coupled. It is the block diagram which put DSP and CPU into one chip simply. It is a block diagram of the GSM mobile communication terminal of the 1st Example of this invention. FIG. 3 is an internal / external memory connection configuration diagram in the first embodiment of the present invention. It is a DSP / CPU integrated chip block diagram which carried the cache of 2nd Example of this invention. It is a figure which shows the basic form of the memory allocation in the mobile communication terminal application of the 3rd Example of this invention. It is a figure which shows the extended form of the memory allocation in the mobile communication terminal application of the 3rd Example of this invention. It is a figure which shows the connection of DSP / CPU integrated chip at the time of connecting burst ROM of the 4th Example of this invention directly. It is a figure which shows the time chart of DSP / CPU integrated chip at the time of connecting burst ROM of the 4th Example of this invention directly. It is a figure which shows an example of the memory map of a DSP / CPU integrated chip. It is a figure which shows the connection of DSP / CPU integrated chip at the time of connecting DRAM of 5th Example of this invention directly. It is a figure which shows the time chart by DSP / CPU integrated chip at the time of connecting DRAM of 5th Example of this invention directly. It is a figure which shows another time chart by DSP / CPU integrated chip at the time of connecting DRAM of the 5th Example of this invention directly. It is a figure which shows the connection of DSP / CPU integrated chip and AD / DA converter for I / Q signals in the 6th Example of this invention. Figure and time chart. It is a figure which shows the time chart by the DSP / CPU integrated chip and AD / DA converter for I / Q signals in the 6th Example of this invention. It is a block diagram of the serial input / output circuit of the 6th Example of this invention. It is a figure which shows the connection of DSP / CPU integrated chip and AD / DA converter for I / Q signals in the 7th Example of this invention. Wow and time chart. It is a time chart by the DSP / CPU integrated chip and AD / DA converter for I / Q signals in the 7th example of the present invention. It is a figure which shows the structure of the serial input / output circuit of the 7th Example of this invention. It is a figure which shows the connection of DSP / CPU integrated chip and the DA converter for power amplifier control in the 8th Example of this invention. And time chart. It is a figure which shows the time chart by DSP / CPU integrated chip and the DA converter for power amplifier control in the 8th Example of this invention. It is a figure which shows the overhead in the conventional GSM mobile communication terminal using DSP and CPU. It is a figure which shows the timing and output waveform of power amplifier control in a GSM mobile communication system. It is a figure which shows the overhead in power amplifier control. It is a figure which shows power amplifier control of the 8th Example of this invention. It is a figure which shows the structure of the DSP / CPU integrated chip provided with the integrated ASIC bus interface of the 9th Example of this invention. It is a figure which shows the structure of CPU in a DSP / CPU integrated chip. It is a figure which shows the example of C program explaining the 10th Example of this invention. It is a figure which shows the hardware relevant to the assembler program explaining the 10th Example of this invention.

Explanation of symbols

100 base station 101 communication terminal 223 DSP chip 227 CPU chip

Claims (3)

A microcomputer and an external memory;
The microcomputer is
A CPU capable of executing each instruction of calculation, internal memory access and data transfer in one cycle;
A DSP that includes an arithmetic unit that operates in accordance with the CPU and can execute acyclic filter operations in one cycle per tap;
A plurality of buses connected to the CPU and the DSP;
A plurality of internal memories connected to the plurality of buses and accessed by addresses supplied from the CPU;
An external bus interface circuit connected to the plurality of buses and capable of controlling access to an external memory by an address supplied from the CPU;
The external memory is a terminal device connected to the external bus interface circuit of the microcomputer and having a program storage area for performing communication protocol control with a base station. The terminal device according to claim 1, wherein data is exchanged with the base station by wireless communication. The CPU has a CPU core register; the DSP has a DSP register;
The CPU reads data from the internal memory using data set in the CPU core register as an address, stores the read data in the DSP register, and the arithmetic unit inputs the data stored in the DSP register. Item 1. The terminal device according to Item 1.

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