JPH11252001A - Digital communication terminal equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of terminal equipment and power consumption by avoiding the use of a high-speed clock signal at all the time by adopting a DSP-CPU connecting chip and adopting respectively suitable clock frequencies at the time of digital signal processing, equipment control and base station switching or at the time of soundless voices. SOLUTION: A DSP-CPU integrated chip 301 is used for housing a DSP core 423 and a CPU core 321 while sharing an instruction decoder 322 and for housing a clock signal generating circuit 313 together. To the DSP core 324 and the CPU core 321, an internal clock signal 113 at high speed in the case of digital signal processing to operate both the cores and at low speed in the case of following equipment control to use only the CPU core 321 is supplied from the generating circuit 313. Time dividing operation for alternately repeating this operation is adopted, the internal clock signals 113 at plural optimum frequencies are supplied, and the state of consuming no power at the time of base station switching or the like can be provided. Thus, the number of IC chips and power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal suitable for application to a communication system for communicating with a base station using a radio frequency band, and more particularly to a digital communication for transmitting and receiving a digitized signal. Related to terminals.

[0002]

2. Description of the Related Art As an example of a conventional digital communication terminal, a catalog [BC94-00] of AT & T Microelectronics, USA
FIG. 9 shows a terminal described in 6GSM "GSM Hardware Platform" (issued in February, 1994). The terminal uses digital signal processing (DSP) for audio signals.
Signal Processor) 103 performs equipment control (communication protocol control with base station and operation control of each component in terminal)
Is performed by a CPU (Central Processing Unit) 102. The CPU 102 includes a microprocessor (μ Proces
sor).

The DSP 103 and the CPU 102 have different I
Since the hardware is separated by C chips,
It can be defined as separable Two Engines, and the DSP 103 operates with the optimal high-speed clock signal, and the CPU 102 operates in parallel with the optimal low-speed clock signal. To enable such parallel operation, Japanese Patent Application Laid-Open No.
No. 02274 and a known frequency multiplication P
An LL (Phase Locked Loop) circuit is used as the clock signal generation circuit 112 built in the DSP 103. The clock signal generation circuit 112 outputs a high-speed clock signal 113 to be multiplied by a frequency of the system clock signal 111 and supplied to the DSP 103. On the other hand, the CPU 102 is supplied with a system clock signal 111 which is a low-speed clock signal.

However, in this conventional technique, a separation type two
Since Engines are used, each of the DSP 103 and the CPU 102 requires an internal instruction decoder. There is a problem that the chip size and the power consumption increase due to the two instruction decoders, and the terminal size and the power consumption increase.

[0005]

Recently, DSPs and CPUs have been developed.
And the instruction decoder of the CPU
An integrated Single Engine IC that substitutes the P instruction decoder was developed by Hitachi, Ltd. [for example, in the US magazine “Proceedings of The Processing Application Co.”
nference at DSP ^X '96 ”pp. 645-652 (1
(Issued March 996)).

Therefore, if an IC having this integrated instruction decoder is used in a terminal, the chip size and power consumption can be reduced, and the size and power consumption of the terminal can be reduced. However, in this case, since the DSP is controlled by the instruction decoder of the CPU, it is impossible to separate and supply the clock signal in which the low-speed clock signal is supplied to the CPU on the one hand and the high-speed clock signal is supplied to the DSP on the other hand during the DSP operation. It has been found that both the CPU and the DSP must be supplied with a high-speed clock signal. That is, it is impossible to cause the integrated Single Engine to perform the parallel operation of the low-speed clock operation of the CPU and the high-speed clock operation of the DSP as in the case of the terminal using the separated Two Engines. Using a high-speed clock signal for device control by the CPU is a waste of power, and there is a problem that it is difficult to reduce power consumption of the terminal.

It is an object of the present invention to solve the above-mentioned problems of the prior art, and to provide a new digital communication terminal capable of reducing the number of IC chips and reducing power consumption.

[0008]

The object of the present invention is to provide a C
The instruction decoder of the PU is substituted for the instruction decoder of the DSP, the same clock signal is supplied to both the DSP and the CPU, and the frequency (first frequency) of the clock signal when both the DSP and the CPU are operating is set to the CPU. It is possible to solve the problem effectively by setting the frequency higher than the frequency (second frequency) of the clock signal during only the operation. The digital signal processing can be performed by operating both the DSP and the CPU, and then the device control can be performed by operating only the CPU, and a time-division operation that repeats this can be adopted. The same optimal clock signal supply as in the case of the conventional separated Two Engines, which supplies a clock signal of
This is possible with e.

As described above, it is possible to employ an IC in which a DSP and a CPU are integrated, and it is also possible to employ clock signals suitable for digital signal processing and device control, thereby reducing the size and consumption of the terminal. The power can be reduced.

It is desirable that the DSP receive a command for reducing power consumption from the instruction decoder when the CPU starts controlling the device. Upon receiving this command, the DSP keeps a standby state (power is supplied but operation is stopped), keeps little power consumption, or switches to a power supply stop state and consumes no power. Can be kept. On the other hand, during execution of signal processing by the DSP, most of the CPU performs instruction decoding and address calculation for operating the DSP.
The PU continues operation without stopping.

Further, when the CPU executes the operation of switching the base station in communication to another base station, it may be necessary to add time for the switching operation. In such a case, it is desirable to set the clock signal frequency during operation of both the DSP and the CPU to a third frequency higher than the first frequency. The period of both operations is shortened, so that a margin of time is generated and the additional time can be secured.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the digital communication terminal according to the present invention will be described below in more detail with reference to some embodiments shown in the drawings. The same symbols used in FIGS. 1 to 9 indicate the same or similar objects.

[0013]

<Embodiment 1> In FIG. 1, reference numeral 301 denotes a DSP.
DSP-CPU integrated IC chip containing a CPU and 30
2 is the main part of the chip (hereafter, the main part is called “core”
DSP-CPU integrated core, 324 is DSP
A core, 321 is a CPU core, and 313 is a clock generation circuit in the IC chip 301.

In FIG. 1, 322 and 323 denote CPUs.
An instruction decoder and an address generation circuit in the core 321, 325, 326, and 327 are operation registers, a product-sum operation unit, and an arithmetic operation unit in the DSP core 324, respectively, and 303 is an internal ROM (Read) in the integrated core 302. Only Memory) 131 and internal SRAM (Static Random Access Memory) 132, DS
An internal bus for transmitting and receiving signals between the P core 324 and the CPU core 321; a direct connection bus for transmitting and receiving signals directly between the DSP core 324 and the internal ROM 131 and the internal SRAM 132; An external memory interface 311 for exchanging signals between the external ROM 121 and the external SRAM 122 installed outside the 301 and the integrated core 302 via the internal bus 303, and an audio signal AD / DA (Analog t
o Digital / Digital to Analog) converter 106 and an input / output interface (hereinafter referred to as “SIO”) for transmitting and receiving digital voice transmission / reception signals, and 312 is a modem AD / DA
SI for exchanging digital modulation / demodulation signals with converter 107
O and 305 are a clock signal generation circuit 313 and SIOs 311, 3
A peripheral bus 304 for exchanging signals between the internal core 302 and the integrated core 302, a bus control unit 304 for connecting the internal bus 303 to the peripheral bus 305, and 315 and 316, respectively, SIO 31
5 shows an interrupt signal supplied to the CPU core 321 from 1, 312.

Further, in FIG. 3, reference numerals 331 to 334 are connected between the clock signal generation circuit 313 and the peripheral bus DS 305;
Clock signal generation circuit 313 under the control of DSP core 321
2 shows a digital signal processing identification register, a radio status register, a transmission voice status register, and a reception voice status register for generating the internal clock signal 113 having various frequencies. Other configurations are the same as those of the conventional terminal. The frequency of the system clock signal 111 is 1
3 MHz was adopted. The clock signal is used to set the operation timing of each part of the terminal and needs to have stability. As a generating circuit, the temperature control crystal oscillator (T
CXO) 101.

In the above configuration, at the time of transmission, the audio signal from the microphone 104 is converted into a digital audio signal by the audio signal AD / DA converter 106 and then converted to a digital audio signal.
After receiving digital signal processing (speech compression, adding error correction code, etc.) by the SP-CPU integrated core 302, the modem D
A call transmission signal. The signal is subjected to modem processing by a modem AD / DA converter 107, turned into a radio frequency signal by a high frequency (hereinafter, “RF”) modulator / demodulator 108, power-amplified by an RF unit 109, and transmitted from an antenna 110. You. At the time of reception, the received signal from the antenna 110 goes through the reverse to become an audio signal and is supplied to the speaker 105.
The signal output from the modem AD / DA converter 107 at the time of reception includes power monitor data for measuring the radio field intensity from the base station in addition to the modem AD call reception signal. The digital modulation / demodulation signal is a collective term for these and the modem DA call transmission signal.

Next, the DSP-CPU integrated IC chip 301
, The instruction decoder 322 decodes the operation instruction of the DSP core 324 and the operation instruction of only the CPU core 321,
In the case of an operation instruction of the P core 324, a control signal is given to the DSP core 324. The address generation circuit 323 generates addresses of the internal ROM 131 and the internal SRAM 132. Further, a PLL circuit having a variable multiplication rate is employed as the clock signal generation circuit 313. The system clock signal 111 supplied to the clock signal generation circuit 313 is multiplied or divided to become an internal clock 113, which is supplied to each block in the chip. The multiplication rate is set by the registers 331 to 334, and details thereof will be described later.

The digital communication terminal of this embodiment is a GSM (Groupe Special) which is an international standard system for mobile communication.
Mobile). When the digital communication terminal of this embodiment is in a talking state as a GSM terminal, the CPU-DSP integrated chip 30
1 executes digital signal processing and device control (communication protocol control and operation control of each component in the terminal) with a cycle of one voice frame of 20 ms.

Digital signal processing is processing for converting a digital audio signal and a digital modulation / demodulation signal. On the transmitting side, voice coding processing (compression), channel coding processing (error correction code addition), modulation processing, and on the receiving side, demodulation and equalization processing, channel decoding processing (code error correction), voice decoding processing (decompression) ). These make heavy use of arithmetic operations and product-sum operations. In digital signal processing, 1
It is required to have a real-time property that data for a frame must be processed within one frame. For this reason,
The CPU core 321 drives the DSP core 324 at high speed to realize digital signal processing. Furthermore, programs and data required for digital signal processing are several tens of kW each.
(Word), which is of the order of several kW, the entire amount can be stored in the internal ROM 131 and the internal SRAM 132, and performance is not sacrificed for access to the external memory. For this reason, it is effective to set the multiplication rate of the clock generation circuit 313 as high as possible within a range in which the CPU-DSP integrated core 302 can operate in order to realize a necessary processing amount.

On the other hand, since the programs and data required for controlling the devices reach hundreds of kW and tens of kW, respectively, most of them must be provided in the external ROM 121 and the external SRAM 122. Low power external memories generally have long access times. Therefore, in the device control, the processing is limited by the access speed of the external ROM 121 or the external SRAM 122. However, real-time control is not required in device control, and the processing amount is not so large. Therefore, it is effective to set the clock signal frequency to a value equal to or lower than a value that can be accessed by an external memory in one cycle. Thus, unnecessary power consumption during device control can be avoided.

Similarly, the external SRAM 122 and the internal SRAM 1
The external SRAM 12 can also be used for data transfer between 32
Since the processing is rate-determined at the access speed of 2, it is effective to set a similarly low clock signal frequency.

One voice frame (201) taking these into consideration
FIG. 2 shows the flow of digital signal processing and device control in the system. The CPU-DSP integrated core 302 first
The modem AD call receiving signal data output from the modem AD / DA converter 107 for the voice frame is stored in the external SRAM 122, and then the stored data is transferred to the internal SRAM 132 (process 401). Thereafter, demodulation and equalization processing (402), channel decoding processing (403), and audio decoding processing (404) are performed. The digital audio reception signal data for which digital signal processing has been completed is temporarily stored in the internal SRAM 132 and then sent to the audio signal AD / DA converter 106.

Subsequently, the process proceeds to the transmission process, where the CPU-DS
The P integration core 302 temporarily stores digital voice transmission signal data for one voice frame in the internal SRAM 132, and performs voice coding processing (405), channel coding processing (406), and modulation processing (405) on the stored data. 407). The data after the completion of the modulation processing 407 is transmitted to the modem AD / DA converter 107.
This is input modem DA call transmission signal data, which is temporarily stored in the internal SRAM 132,
Transferred to M122 (process 408), and then modem AD / DA
Sent to converter 107.

Next, in order to compare the power (strength) of the radio wave arriving from the communicating base station, the process proceeds to the detection of the power of the radio wave arriving from the surrounding base station. The power of the incoming radio wave from the communicating base station is calculated by analyzing the amplitude of the received signal. The power of an incoming radio wave from a nearby base station is detected by monitoring a slot in which the nearby base station is communicating with another terminal. For this purpose, the CPU-DSP integrated core 302 stores the power monitor data for one voice frame output from the modem AD / DA converter 107 in the external SRAM 122 and then transfers it to the internal SRAM 132 (process 409). Subsequently, the power detection processing (41) is performed using the power monitor data transferred to the internal SRAM 132.
Perform 0). Thereafter, a process (213) of device control (communication protocol control and operation control of each component in the terminal) is performed. Thereafter, until the start of the next audio frame, the CPU-DS
P integrated core 302 sleeps (stops operation) from CPU 321
Upon receiving the command, the sleep state 411 is entered.

The amount of data transmitted and received in the above transmission and reception is 2500 W for one audio frame. This is one voice frame of the data of the digital modulation / demodulation signal transmitted and received between the modem AD / DA converter 107 and the CPU-DSP integrated core 302, and employs a four-fold oversampling method in which four samples correspond to one symbol. This is the amount of data that can be obtained. Also, audio signal AD / DA converter
The data amount of the digital voice transmission / reception signal transmitted and received between the CPU 106 and the CPU-DSP integrated core 302 is 160 W for one voice frame in each of the transmission and reception. This is obtained by subjecting an audio signal to 8 KHz sampling, and one symbol corresponds to one sample.

FIG. 2 also shows a change in the multiplication rate of the internal clock 113 generated by the clock signal generation circuit 313. The CPU core 321 sets the digital signal processing identification register 331 to “1” at the start of the demodulation and equalization processing 402 and sets it to “0” at the end of the modulation processing 407. Also, it is set to “1” again at the start of the power detection process 410 and is set to “0” again at the end of the process. As a result, during the execution of the digital signal processing, the internal clock signal 113 becomes 52 MHz, which is obtained by multiplying the 13 MHz system clock signal 111 by four. on the other hand,
Each of the periods during the execution of the device control, the execution of the external SRAM transfer process, and the sleep state is 6.5 MHz obtained by dividing the system clock signal 111 of 13 MHz by １ ／.

Further, the CPU core 321 gives a command for reducing power consumption to the DSP core 324 as a control signal at the end of the modulation processing 407 and at the end of the power detection processing 410. Upon receiving the command, the DSP core 324 operates a clock signal switch (not shown) inside the DSP core 324 to operate the DSP core 324.
The supply of the clock signal to the inside is stopped, and a standby state is entered. In the standby state, although the power is supplied, the operation is stopped, and a low power consumption state where almost no power is consumed is set. In addition to the above-described stop of the supply of the clock signal, it is possible to cut off the power supply by a power consumption reduction command. In this case, there is no power supply, so that power is not consumed.

The data transfer in the IC chip 301 is
In addition to those shown in FIG. 2, an audio signal AD / DA converter that generates 1 W at a periodic interval of 8 KHz for each of transmission and reception.
There is data transfer between 106 and internal SRAM 132. Furthermore,
A frame called a radio frame (described later, 26 radio frames are placed for every 6 voice frames) is used in the RF modulator and demodulator 108 and the RF unit 109, and its period is 120/26 (= 4.615) ms. A / D converter 107 and an external SRAM 122 which occur once each time
During burst transfer of digital modulation / demodulation signal data. In the burst transfer, a total of data is 625 W in a quadruple oversampling method in which four samples correspond to one symbol. The burst transfer is started by interrupt signals 315 and 316 provided from the SIOs 311 and 312 to the CPU core 321. CPU-DS in sleep state 411
The P-integrated core 302 stops its operation and operates only in the periphery. At this time, when the interrupt signals 315 and 316 occur, the CP
The U-DSP integrated core 302 is activated, and the data transfer is realized. After the end of the predetermined processing, the apparatus enters the sleep state again.

The radio frame includes an RF unit 109 and an RF unit.
This is a basic operation cycle of the modem 108. One radio frame is divided into 8 time slots by a time division multiple access (TDMA) system, and one of the radio frames is transmitted to the terminal, one is transmitted to the reception time slot, and the other is transmitted to the reception time slot. Is assigned to the power monitoring time slot. The remaining other time slots are allocated to another terminal. 26 of radio frames
Constitute one multi-frame of 120 ms, to which six audio frames are synchronized. The modem AD call reception signal data is transmitted every time the reception time slot ends.
Burst transfer is performed according to the path of / DA converter 107 → SIO 312 → external SRAM 122. The power monitor data is similarly transferred every time the power monitoring time slot ends. On the other hand, the modem DA call transmission signal data is burst-transferred along the route of the external SRAM 122 → SIO312 → modem AD / DA converter 107 before the start of the transmission time slot. The digital modulation / demodulation signal data is equivalent to four radio frames (4 × 625 W) for one voice frame (2500 W).
Is equivalent to

Next, the operation of the digital communication terminal in the case of performing a handover process, which is a process of switching a base station in communication with another base station in the vicinity in GSM, will be described. Prior to the description, FIG. 3 shows a schematic flow of the handover process. In the figure, the terminal is described as “MS” and the base station is described as “BSS”. The base station BSS-A with which the terminal MS is communicating is connected to another base station BSS in the vicinity.
-B.

First, over four multi-frames (501), the CPU core 321 analyzes the modem AD call reception signal data transmitted from the modem AD / DA converter 107 via the SIO 312, thereby obtaining the peripheral The base station recognizes a base station code (BSIC: Base Station Identifier Code), then measures and averages the power from the power monitor data from each base station, and arranges them in descending order (511). Next, the power and the error rate are measured and averaged from the power monitor data from the base station BSS-A (512). Subsequently, these measurement results are put on the control channel and the base station BSS-A
(513). If the base station BSS-A determines that the base station BSS-B has the highest power based on the received measurement results, it transmits a handover command (Hand Over-command) to the terminal MS. When the command is received (514), the terminal MS switches the synthesizer frequency and the power amplifier output to the specified values (51).
Five). When the connection between the base station BSS-B and the terminal MS is established, the terminal MS receives an access complete signal from the base station BSS-B (516). Correspondingly, the terminal MS sets the base station B
Access Complete Acknowledge (Access C)
Opelte Ack) signal is transmitted (517), and the handover process ends.

The base station switching after receiving the above handover command is performed during communication connection, and the processing is performed as equipment control processing. Therefore, the processing amount of device control increases. If the increase in the processing amount cannot be absorbed in the sleep state 411 shown in FIG. 2, only the clock signal during the digital signal processing is increased. The reason why only the same clock signal is used is that even if the clock signal during the device control process is increased, the processing performance is limited by the external memory access speed, so that the processing performance does not increase. In the present embodiment, the PLL multiplication factor of the clock signal generation circuit 313 during digital signal processing is increased from 4 to 9/2.

The raising of the multiplication rate is performed in the following procedure in anticipation of the occurrence of a handover. If the result of the power measurement (511) from the peripheral base station exceeds the result of the power measurement (512) from the communicating base station and the error rate from the communicating base station exceeds a predetermined value, the CPU Core 32
1 sets the wireless status register 332 to '1'. At this time, the multiplication rate is 9/9, which is close to the maximum at which the chip 301 can operate.
Doubled to prepare for handover. Upon completion of the handover process, the CPU core 321 sets the wireless status register 332 to “0”. At this time, the multiplication factor is returned to four times. FIG. 4 shows a change in the multiplication rate of the PLL 313 in one voice frame when the radio status register 332 is set to “1” and when it is set to “0”. The processing time of the digital signal processing is shortened by the clock signal speed-up, and a longer time for controlling the equipment is secured.

One method is to always set the multiplication rate during baseband signal processing to a value (9/2 times) compatible with handover regardless of whether or not a handover process has occurred. However, when the clock signal generation circuit 313 is operated at high speed, power consumption is large. In particular, rational number multiplication involves a larger number of PLL circuit parts operating than integer multiplication, and consumes much power. Therefore, it is effective to operate the clock signal generation circuit 31 at high speed only when a handover occurs.

Next, the operation of the digital mobile communication terminal when silence is detected during a call will be described. Prior to this,
FIG. 5 shows a schematic flow of the silence detection processing set in GSM. Silence detection processing in GSM is VAD
(Voice Activity Detection) processing.

Silence detection processing is performed at the beginning of the audio encoding processing 405 in the digital signal processing 212.
The DSP core 324 and the CPU core 321 perform a silent detection process on the digital audio transmission signal data. As a result, when a silent state of transmission is detected, the DSP core 324 and the CPU core 321 perform audio encoding of the background noise and convert the encoded background noise into HO (Hang). Over) Frame 1
Send as 111. The silence state is for four voice frames (110
1) When continuing, the DSP core 324 and the CPU core 321
The background noise during this period is averaged, and the average value is calculated as SID
(Silence Descriptor) frame. DS
The P core 324 and the CPU core 321 accumulate the digital audio transmission signal data for one audio frame (160 W) as an audio encoding input buffer and then perform the audio encoding process 405, so that the audio encoding process 405 includes four audio frames. Minutes (110
It is implemented until the next frame of 1). Channel coding 406
Since the modulation process 407 includes an interleave process, the process is further performed until the next two frames (1102). Next, only the control channel is transmitted until the presence of sound is detected again or until background noise is updated (1103) after 480 ms. During the transmission of the control channel, the voice coding process 405 is only the silence detection process, and the channel coding 406 and the modulation process 407 are only for the control channel. Therefore, the processing load is greatly reduced.

During this period, after the SID frame is formed, the transmission voice state register 333 is kept in the period (1103) until the next voice detection is performed or full voice coding is restarted for updating background noise. Set to '1'.

The receiving side performs demodulation / equalization processing 402 and channel decoding processing 403 only up to the SID frame 1121.
Thereafter, the demodulation / equalization process 402 and the channel decoding process 403 are performed only on the control channel during a period until the voice or SID frame is received again (1131). The audio decoding process 404 is interrupted at the frame next to the SID frame (1121), and continues to output the fixed background noise of the audio decoding output buffer until a voiced or SID frame is received again (1132). Therefore, during this period, demodulation and equalization processing
The loads of 402, channel decoding processing 403, and audio decoding processing 404 are greatly reduced.

Thereafter, after the SID frame is decoded, the next sound frame arrives, or the full demodulation and equalization processing 402 and the channel decoding processing 403 for updating background noise are performed.
During the period (1132) until the operation is resumed (1132), the reception voice state register 334 is set to '1'.

The reduction of the processing load upon detection of silence as described above is reflected in a decrease in the clock signal frequency during digital signal processing.
The power consumption of the clock signal generation circuit 313 was reduced.
FIG. 6 shows a change in the multiplication rate in one audio frame when the transmission audio state register 333 is set to “1” and when the reception audio state register 334 is set to “1”. Utilizing the reduction of the processing amount on the transmission side and the reception side, respectively, the multiplication rate during digital signal processing is increased from 4 times to 3 times.
It has been reduced twice.

Although the present embodiment is directed to an audio signal, the present invention is not limited to this, and the present invention can be applied to other signals such as a video signal and a facsimile signal, and similar effects can be obtained.

<Embodiment 2> Digital signal processing period 212
(See FIG. 4), a digital communication terminal adapted to a case where it is required to increase the speed of an internal clock signal to a range that cannot be achieved by a predetermined rational number multiplication is shown in FIG.
Shown in In the figure, reference numeral 701 denotes a system clock signal 1
Oscillator that generates a clock signal that is asynchronous to 11, 702
Indicates an input clock switching register that switches a signal input to the clock signal generation circuit 313 to the system clock signal 111 or an asynchronous clock signal. Switching register 70
2 performs a switching operation under the control of the CPU core 321.

As described above, the frequency of the internal clock signal obtained by rationalizing the system clock signal of 13 MHz by 9/2 times is 58.5 MHz. On the other hand, CPU-
If the DSP integrated chip 301 can operate up to 60 MHz, it is effective to obtain a higher frequency.
59.3125 MHz with rational number multiplication of / 16 times, 147
By multiplying the rational number by a factor of / 32, it becomes 59.197875 MHz. However, when such complicated multiplication is performed by the PLL circuit, the circuit scale and power consumption are further increased.

For this reason, a 13.33 MHz clock signal that is asynchronous with the 13 MHz system clock signal 111 is used, and the clock signal is multiplied by 9/2 to obtain 60 MHz. However, since clock signals that are not synchronized with each other are used in the wireless device, harmonics of the asynchronous clock signal or product components of the system clock signal 111 and the asynchronous clock signal may occur as interference noise in the transmission / reception band. There is. In that case, the TDMA shown in FIG.
System transmission time slot 802, reception time slot 803
In addition, an asynchronous clock signal is used while avoiding the period of the power monitoring time slot 804. The switching register 70
The control for 2 is performed by the CPU core 321 writing “1” or “0” to the switching register 702.
If '1', the system clock signal 111 is selected,
If '0', the asynchronous clock signal is selected.

[0045]

According to the present invention, it is possible to employ an IC chip in which a DSP and a CPU are integrated, and to employ a clock frequency suitable for each of digital signal processing and device control. Therefore, it is possible to reduce the size of the terminal and the power consumption because the constant use of the high-speed clock signal is avoided. In addition, since it is possible to adopt a clock frequency suitable for switching between base stations or when there is no sound, the power consumption of the terminal can be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a digital communication terminal according to a first embodiment of the present invention.

FIG. 2 is a time system diagram for explaining a processing flow of digital signal processing and device control of the first embodiment.

FIG. 3 is a time system diagram for explaining processing at the time of base station switching according to the first embodiment.

FIG. 4 is a time system diagram for explaining a time increment secured at the time of base station switching.

FIG. 5 is a time system diagram for explaining a processing operation to be performed when a sound of the first embodiment is silent.

FIG. 6 is a time system diagram for explaining a change in an internal clock frequency during a processing operation performed when there is no sound;

FIG. 7 is a circuit configuration diagram for explaining a second embodiment of the present invention.

FIG. 8 is a time system diagram for explaining an internal clock frequency according to the second embodiment.

FIG. 9 is a circuit diagram illustrating a conventional digital communication terminal.

[Explanation of symbols]

106 ... Audio signal AD / DA converter, 107 ... Modem AD / D
A converter, 111: system clock signal, 113: internal clock signal, 301: DSP-CPU integrated chip, 302: DS
P-CPU integrated core, 313 ... clock signal generation circuit, 321
... CPU core, 322 ... Instruction decoder, 324 ... DSP core,
331: Baseband signal processing identification register, 332: Wireless status register, 333: Transmit audio status register, 334: Receive audio status register, 701: Asynchronous clock signal generation circuit, 7
02 ... Input clock switching register.

Claims (5)

[Claims] 1. A signal processing unit (hereinafter referred to as "DSP") for performing digital signal processing of a signal to be transmitted and received,
In a digital communication terminal including a central processing unit (hereinafter referred to as a “CPU”) for controlling various devices including a communication protocol control and a clock signal generation circuit, an instruction decoder for controlling the DSP and the CPU includes a DSP. And a single instruction decoder shared by both the CPU and the CPU.
The same clock signal is supplied to both the P and the CPU, and the first frequency of the clock signal when both the DSP and the CPU are operating is higher than the second frequency of the clock signal when only the CPU is operating. A digital communication terminal characterized by being set high. 2. The digital communication terminal according to claim 1, wherein the DSP enters a low power consumption state upon receiving a power consumption reduction command from the CPU while the CPU is executing device control. 3. The clock signal generating circuit according to claim 1, wherein the clock signal frequency during the operation of both the DSP and the CPU is changed from the first frequency during a period in which the CPU executes an operation of switching a base station in communication to another base station. The digital communication terminal according to claim 1, wherein the third frequency is set to a higher third frequency. 4. The clock signal generating circuit according to claim 1, wherein when the signal to be transmitted and received is continuously lower than a predetermined level for a predetermined period, the clock signal frequency at the time of operating both the DSP and the CPU is lower than the first frequency. 2. The digital communication terminal according to claim 1, wherein the frequency is set to a predetermined frequency. 5. When the communication with the base station is performed by a time division multiple access method, the clock signal generating circuit includes a DSP and a CPU during a period other than the transmission / reception time slot allocated to the terminal. The clock signal frequency at the time of both operations is set to a fifth frequency higher than the third frequency, and the clock signal of the fifth frequency is asynchronous with the clock signal of the third frequency. The digital communication terminal according to claim 3, wherein: