JP2005136098A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily separate a wafer from a support substrate while preventing the cracking of the wafer, after processing the rear face of the wafer in such a state that the support substrate is bonded to the front face of the wafer, in manufacturing a semiconductor device such as an IGBT which has a thin thickness by back-grinding the rear face of the wafer. <P>SOLUTION: The support substrate 70 is bonded to the front face of the wafer 60 via a double-sided adhesive sheet 50 which can be peeled off by heat-foaming. In such a state, the rear face of the wafer 60 is ground and etched to make the wafer 60 thin, and thereafter a central portion 61 of the wafer is cut out from the peripheral portion 62 of the wafer by irradiating a laser beam along the periphery of the wafer 60. The peripheral portion 62 of the wafer is bonded to the support substrate 70 by a poorly separated part 54 created by the deterioration of the adhesive sheet 50 at the time of etching. Then, the central portion 61 of the wafer is separated from the support substrate 70 by heating. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element having a thin device thickness by grinding and etching the back surface of a wafer with a support substrate attached to the surface of the wafer.

  2. Description of the Related Art Conventionally, an integrated circuit (IC) in which a large number of transistors, resistors, and the like are connected to form an electric circuit and integrated on one chip is often used in a main part of a computer or a communication device. Among such ICs, those including power semiconductor elements are called power ICs. One of power semiconductor elements is an insulated gate bipolar transistor (hereinafter referred to as IGBT).

  An IGBT is a voltage-driven type element that has a low on-voltage and high-speed switching characteristics. The range of applications has expanded from industrial fields such as inverters to consumer devices such as microwave ovens. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.

  The IGBT has a punch-through (hereinafter referred to as PT) type, a non-punch-through (hereinafter referred to as NPT) type, and a field stop (hereinafter referred to as FS) type, and an n-channel vertical double type. A diffusion structure is the mainstream. Accordingly, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.

The PT-type IGBT is formed using an epitaxial wafer obtained by epitaxially growing an n ⁺ buffer layer and an n ⁻ active layer on a p ⁺ semiconductor substrate. Therefore, for example, in a device with a withstand voltage of 600 V, the thickness of the active layer is about 70 μm, but the total thickness including the substrate is about 200 to 300 μm. In the PT type IGBT, the depletion layer in the n ⁻ active layer reaches the n ⁺ buffer layer.

FIG. 11 is a cross-sectional view showing the configuration of a half cell of an NPT type IGBT having a shallow p ⁺ collector layer with a low dose. In general, an FZ wafer is used to manufacture an NPT type IGBT. An FZ wafer is a wafer cut from a semiconductor ingot manufactured by a floating zone method. As shown in FIG. 11, an n ⁻ semiconductor substrate made of, for example, an FZ wafer is used as an active layer 1, and ap ⁺ base region 2 is selectively formed on the surface side thereof. An n ⁺ emitter region 3 is selectively formed on the surface layer of the base region 2. A gate electrode 5 is formed on the substrate surface via a gate oxide film 4.

The emitter electrode 6 is in contact with the emitter region 3 and the base region 2 and is insulated from the gate electrode 5 by the interlayer insulating film 7. A p ⁺ collector layer 8 and a collector electrode 9 are formed on the back surface of the substrate. In the case of the NPT type, the thickness of the active layer 1 is thicker than that of the PT type, but the entire element is significantly thinner than the PT type element. Since the hole injection rate can be controlled, high-speed switching is possible without performing lifetime control. Further, since an FZ wafer is used instead of an epitaxial wafer, the cost is low.

FIG. 12 is a cross-sectional view showing the configuration of 1/2 cell of FS type IGBT. An FZ wafer may be used for manufacturing the FS type IGBT. As shown in FIG. 12, the element structure on the substrate surface side is the same as the NPT type element shown in FIG. On the back side of the substrate, an n ⁺ buffer layer 10 is provided between the n ⁻ active layer 1 and the p ⁺ collector layer 8. In the case of the FS type, the thickness of the active layer 1 is about 70 μm (withstand voltage 600 V system), which is the same as that of the PT type, and the thickness of the entire element is about 100 to 200 μm. And lifetime control is unnecessary like a non punch-through type.

  Recently, in order to further reduce the total loss, an attempt has been made to thin the wafer and reduce the device thickness as much as possible. For example, in the case of an element having a withstand voltage of 600 V, the thickness of the FS-IGBT is assumed to be about 70 μm. When the breakdown voltage class is lowered, the thickness of the element is further reduced. As a method for manufacturing such a thickness FS-type IGBT or a device similar thereto, a method of polishing an FZ wafer and a method of polishing an epitaxial wafer are known as described below.

FIG. 13 (FIGS. 13-1 to 13-5) is a diagram showing a manufacturing process of an FS type IGBT using a conventional FZ wafer. First, on the surface side of the n ⁻ FZ wafer to be the active layer 1, a surface side element structure portion 11 including a base region, an emitter region, a gate oxide film, a gate electrode, an interlayer insulating film, an emitter electrode, and a passivation film is formed ( Fig. 13-1). The gate oxide film is made of, for example, SiO ₂ . The gate electrode is made of polysilicon, for example. The interlayer insulating film is made of, for example, BPSG. The emitter electrode is made of, for example, an Al—Si film. The Al—Si film is heat-treated at a low temperature of about 400 to 500 ° C. in order to realize a low resistance wiring having a stable bonding property. The passivation film is made of, for example, a polyimide film.

  Next, the back surface of the wafer is ground by combining processing methods such as back grinding, polishing or etching, alone or in combination, so that the wafer has a desired thickness, for example, 70 μm (FIG. 13-2). In the case of etching, it is not strictly grinding, but in this specification, there is no limitation on the means for thinning the wafer. Therefore, grinding is performed including etching.

  Next, for example, phosphorus (P), which is an n-type impurity, and boron (B), which is a p-type impurity, are ion-implanted from the back surface of the wafer, and a heat treatment (annealing) is performed at 350 to 500 ° C. in an electric furnace to form a buffer layer. 10 and the collector layer 8 are formed (FIG. 13-3). Next, a plurality of metals such as aluminum (Al), titanium (Ti), nickel (Ni), and gold (Au) are deposited on the back surface of the wafer, that is, the surface of the collector layer 8 to form the collector electrode 9 (FIG. 13-4).

  Finally, dicing tape 12 is attached to the collector electrode 9 side to perform dicing, and the wafer is cut into a plurality of chips 13 (FIG. 13-5). Each chip 13 is mounted on various devices by having its collector electrode 9 soldered to a fixing member of the device and an aluminum wire electrode fixed to a surface electrode such as an emitter electrode.

FIG. 14 (FIGS. 14-1 to 14-5) is a diagram showing a manufacturing process of an FS type IGBT using a conventional epitaxial wafer. First, an epitaxial wafer is prepared by growing an epitaxial layer to be the active layer 1 on an n ⁺ semiconductor substrate to be the buffer layer 10. Then, on the surface of the epitaxial wafer on the side of the epitaxial layer, a surface side element structure portion 11 including a base region, an emitter region, a gate oxide film, a gate electrode, an interlayer insulating film, an emitter electrode, and a passivation film is formed (FIG. 14-). 1).

The gate oxide film is made of, for example, SiO ₂ . The gate electrode is made of polysilicon, for example. The interlayer insulating film is made of, for example, BPSG. The emitter electrode is made of, for example, an Al—Si film. The Al—Si film is heat-treated at a low temperature of about 400 to 500 ° C. in order to realize a low resistance wiring having a stable bonding property. The passivation film is made of, for example, a polyimide film. The n layer is diffused in the diffusion step when forming the surface-side element structure portion 11. Next, the wafer is made to have a thickness of, for example, 70 μm by back grinding or the like so that the n ⁺ semiconductor substrate has a thickness of, for example, 10 μm (FIG. 14-2).

  Next, boron, which is a p-type impurity, is ion-implanted from the back surface of the wafer and annealed at 350 to 500 ° C. in an electric furnace to form the collector layer 8 (FIG. 14-3). Next, a collector electrode 9 made of a plurality of metal layers such as aluminum (Al), titanium (Ti), nickel (Ni) and gold (Au) is formed on the surface of the collector layer 8 (FIG. 14-4). Finally, the dicing tape 12 is attached to the collector electrode 9 side to perform dicing, and the wafer is cut into a plurality of chips 13 (FIG. 14-5). Each chip 13 is mounted on various devices by having its collector electrode 9 soldered to a fixing member of the device and an aluminum wire electrode fixed to a surface electrode such as an emitter electrode.

  By the way, in recent years, when performing exposure etching processing of a wafer, a wafer is placed on a base film, the wafer is covered with a dry photoresist film, and further covered with a protective film. A technique for forming the film is in practical use. A laser cutting machine that cuts the base film, the photoresist film, and the protective film along the outer edge of the wafer so that the peripheral edge of the dry photoresist film protrudes about 0.2 to 0.3 mm from the peripheral edge of the wafer is proposed. (For example, refer to Patent Document 1).

JP 2001-345252 A

  If an element having a thickness of, for example, about 70 μm is to be manufactured by the above-described conventional manufacturing method, the wafer after back grinding is too thin, and therefore, there is a problem that the wafer is easily broken when ion implantation is performed from the back side of the wafer. Further, when a metal film serving as a collector electrode is vapor-deposited on the back surface of the wafer, the metal film becomes a film having a large compressive stress when viewed from the substrate side.

  Further, there is a problem that the wafer is easily cracked by the stress generated in the wafer during annealing in the electric furnace. Even if the wafer is not cracked, the wafer is greatly warped by the compressive stress, so that there is a problem that dicing becomes difficult. In addition, since the shape of the chip after dicing is distorted, the designed characteristics may not be obtained.

  Therefore, the present applicant joins the support substrate to the surface of the wafer on which the surface element structure portion of the semiconductor element is formed via a double-sided adhesive type adhesive sheet that can be peeled off by UV irradiation or heating. Japanese Patent Application No. 2002-302137 has previously proposed a method in which the back grind and the wafer back surface are processed, and then the adhesive sheet is peeled off by UV irradiation or heating to separate the wafer from the support substrate. According to this method, warpage of the wafer during processing on the wafer back surface and stress acting on the wafer can be suppressed, so that the wafer can be prevented from cracking during processing on the wafer back surface. be able to.

  However, the method for bonding the support substrates described above may cause the following problems. In general, after back grinding, in order to remove the layer having stress caused by grinding on the back side of the wafer, a mixed solution containing a strong acid such as hydrogen fluoride or nitric acid is dropped on the back side of the wafer rotated at high speed to etch the back side of the wafer. To do. In that case, the liquid mixture dripped on the wafer back surface may hang down on the side surface of the laminate including the wafer, the adhesive sheet, and the support substrate.

  In this case, if an adhesive sheet having low resistance to strong acid is used, the wafer edge portion of the adhesive sheet is denatured, and the adhesive force of the wafer edge portion does not become weak even when irradiated with UV or heated. In this case, even if the central portion of the wafer is peeled off from the support substrate by UV irradiation or heating, the wafer edge portion remains adhered to the support substrate, so that stress is generated and the wafer is cracked. Further, if the wafer is forcibly peeled off, the wafer is cracked because the wafer is extremely thin and the mechanical strength is low.

  In addition, when a metal electrode is formed on the back surface of the wafer by vacuum vapor deposition after back grinding, the metal film constituting the electrode may be deposited on the side surface of the laminate composed of the wafer, the adhesive sheet, and the support substrate. is there. In that case, the side surface of the wafer, the side surface of the adhesive sheet, and the side surface of the support substrate are connected by the deposited metal film, so that even if the wafer is detached from the support substrate, the wafer edge portion does not peel off. End up. Therefore, as in the case where the adhesive sheet changes in quality, the wafer breaks when the wafer is detached from the support substrate.

  In order to solve the above-described problems caused by the prior art, the present invention provides a semiconductor device such as an IGBT having a thin device thickness by back grinding the back surface of the wafer. An object of the present invention is to provide a method of manufacturing a semiconductor element that can easily separate a wafer from a support substrate while preventing the wafer from cracking after processing.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to claim 1 includes a step of bonding a support substrate to a surface of a semiconductor wafer, and the state in which the support substrate is bonded. A step of thinning the semiconductor wafer by processing the back side of the semiconductor wafer, a step of separating the peripheral portion of the thinned semiconductor wafer from the central portion, and a wafer central portion separated from the peripheral portion of the wafer from the support substrate And a step of detaching.

  Further, in the method of manufacturing a semiconductor element according to the invention of claim 2, in the invention of claim 1, the adhesive is cured by irradiation with a double-sided adhesive sheet that can be peeled off by heat foaming or UV light. The semiconductor wafer and the support substrate are bonded to each other through a double-sided adhesive sheet that can be peeled off by irradiating the semiconductor wafer and irradiated with a laser beam along the outer periphery of the semiconductor wafer. The wafer central portion is separated from the support substrate by being separated from the portion and heated or irradiated with UV light.

  Further, in the method of manufacturing a semiconductor element according to the invention of claim 3, in the invention of claim 1, the adhesive is cured by irradiation with a double-sided adhesive sheet that can be peeled off by heating foaming or UV light. The semiconductor wafer and the support substrate are bonded to each other through a double-sided adhesive sheet that can be peeled off by processing, the back surface side of the semiconductor wafer is processed to thin the semiconductor wafer, and the peripheral edge portion of the wafer is A step of forming a metal film on the back surface of the thinned semiconductor wafer before separating from the wafer central portion, irradiating a laser beam along the outer periphery of the semiconductor wafer, By removing the semiconductor, the wafer central portion is separated from the wafer peripheral portion, and the wafer central portion is supported by heating or UV light irradiation. Wherein the disengaging from the plate.

  According to the present invention, when the wafer central portion is detached from the support substrate, the central portion of the semiconductor wafer is separated from the peripheral portion, so that the wafer edge portion of the adhesive sheet that joins the wafer and the support substrate is altered. Even if the adhesive force of the wafer edge portion does not become weak, the wafer central portion can be detached from the support substrate. Further, according to the present invention, when the wafer central portion is detached from the support substrate, the central portion of the semiconductor wafer is separated from the peripheral portion, so that the wafer and the support substrate are connected by the metal film covering their side surfaces. Even if this is done, the central portion of the wafer can be detached from the support substrate.

  According to the semiconductor element manufacturing method of the present invention, the wafer can be easily detached from the support substrate while preventing the wafer from cracking. Therefore, there is an effect that a semiconductor element such as an IGBT having a thin device thickness can be easily manufactured.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the embodiment, a case where an IGBT is manufactured by the method of the present invention will be described as an example.

  9 (FIGS. 9-1 to 9-3) and FIG. 10 (FIGS. 10-1 to 10-4) are diagrams showing an outline of the entire process of the method of manufacturing a semiconductor device according to the embodiment of the present invention. It is. First, a method for manufacturing a semiconductor element with a thin device thickness by processing the back surface of the wafer in a state where the support substrate is bonded to the front surface of the wafer will be described with reference to these drawings. Although not particularly limited, an n-doped epitaxial wafer is used here.

First, a gate oxide film such as SiO ₂ and a gate electrode made of polysilicon or the like are deposited on the surface of the epitaxial wafer on which the epitaxial layer 42 is grown, that is, on the surface of the epitaxial layer 42 on the n ⁺ semiconductor substrate 41. Process these. Then, an interlayer insulating film such as BPSG is deposited on the surface and processed to produce an insulated gate structure. Subsequently, a P ⁺ base layer is formed, and an n ⁺ emitter layer is formed therein.

  Then, a surface electrode made of an Al—Si film or the like, that is, an emitter electrode is formed, and heat treatment is performed at about 400 to 500 ° C. to make the Al—Si film a low resistance wiring having stable bonding. Further, a passivation film such as polyimide is laminated on the entire surface, and a surface-side element structure portion 22 similar to the configuration shown in FIG. 12 is completed (FIG. 9-1). In the diffusion process when manufacturing the surface-side element structure portion 22, n-type impurities are diffused into the epitaxial layer 42, and the epitaxial layer 42 becomes an active layer.

  In this specification, the surface of the epitaxial wafer on the side where the surface-side element structure 22 is formed is referred to as the wafer surface, and the opposite surface is referred to as the wafer back surface. 9 and 10, the detailed configuration of the surface-side element structure 22 is not shown.

  Next, the wafer is turned over, and the support substrate 32 is bonded to the surface of the surface-side element structure 22 via the adhesive sheet 31 (FIG. 9-2). Here, for example, a quartz glass wafer that transmits UV light is used as the support substrate 32. The thickness of the support substrate 32 is, for example, 625 μm.

  Further, as the adhesive sheet 31, for example, a high-rigidity UV tape type sheet or a heat-resistant UV tape type sheet that can be peeled off when the adhesive is cured by UV light irradiation, or a heat-foamed tape type sheet that can be peeled off by heating foaming. Use one that does not contain air bubbles during bonding. The thickness of the adhesive sheet 31 is suitably about 100 μm, for example. Moreover, the adhesive sheet 31 has a high heat-resistant temperature, little outgas, and is easy to peel off.

Next, with the support substrate 32 bonded, the back surface of the wafer is ground by back grinding, etching, or the like, so that the entire thickness of the wafer including the surface side element structure portion 22 is a desired thickness, for example, 70 μm, and n ⁺ semiconductor The substrate 41 is left with a thickness of 10 μm, for example (FIG. 9-3). Next, boron, which is a p-type impurity, is ion-implanted from the back surface of the wafer, for example, at a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 20 k to 100 keV, for example.

Thereafter, the back surface of the wafer is irradiated with laser and annealed to form a p ⁺ layer 24 serving as a collector layer (FIG. 10-1). Although not particularly limited, a XeCl pulse laser (wavelength: 308 nm, half-value width: 49 ns, frequency: 100 Hz) is used as the laser here. Then, for example, a single irradiation area is about 1 mm square, and irradiation is performed with 50% to 90% overlap. By this laser annealing, only the p ⁺ layer 24 on the back surface of the wafer can be activated, and heat treatment can be performed regardless of the heat resistant temperature of the adhesive sheet 31. In place of XeCl, YAG2ω, YAG3ω, XeF or KrF may be used.

  Next, a plurality of metals such as aluminum, titanium, nickel, and gold are vapor-deposited on the back surface of the wafer to form a back electrode 25 that serves as a collector electrode (FIG. 10-2). Here, it is appropriate to deposit a metal film by a low temperature sputtering method. The reason is that the heat-resistant temperature of the adhesive sheet 31 is approximately 100 ° C. or less for a high-rigidity UV tape-type sheet, 200 ° C. or less for a heat-resistant UV tape-type sheet, and 150 ° C. or less for a heated foam tape-type sheet. Therefore, it is desirable that the temperature during film formation is 100 ° C. or lower.

  Next, a general dicing tape 26 is attached to the back surface of the wafer. Then, UV light is irradiated from the support substrate 32 side, the adhesive sheet 31 is peeled off at the interface with the passivation film of the surface side element structure portion 22, and the adhesive sheet 31 and the support substrate 32 are removed (FIG. 10-3). At that time, care should be taken not to leave an adhesive residue of the adhesive sheet 31 on the surface side element structure 22. When the adhesive sheet 31 is a heat-foamed tape-type sheet, the adhesive sheet 31 is peeled off by heat foaming instead of UV light irradiation.

  Thereafter, the wafer is cut into a plurality of chips 27 (FIG. 10-4). Although not shown, each chip 27 is soldered to a fixing member such as a wiring board via the back electrode 25. An aluminum wire electrode is fixed to the electrode on the wafer surface side of each chip 27 by an ultrasonic wire bonding apparatus.

According to the above-described method of bonding the support substrate to the wafer, it is possible to suppress the warpage of the wafer and the stress acting on the wafer during the processing on the back surface of the wafer. In addition, by adopting laser annealing instead of electric furnace annealing, which is a source of stress, stress acting on the wafer can be suppressed. Therefore, it is possible to prevent the wafer from cracking during the processing on the wafer back surface. Further, since the warpage of the wafer is reduced, dicing can be easily performed and device characteristics as designed can be obtained. Further, by performing laser annealing, the concentration of the p ⁺ layer 24 can be increased, so that the on-voltage can be reduced.

  When a heat-foamed tape-type sheet is used as the adhesive sheet 31, the support substrate 32 does not need to transmit UV light, and therefore is made of a material that does not transmit UV light, such as metal, ceramic, or hard plastic. May be. In addition, the adhesive sheet 31 may have a UV curable adhesive on both sides, a heat-foamed adhesive on both sides, or a surface on the support substrate 32 side and an element side surface. Each may be a UV curable type and a heated foam type, or vice versa. Further, an NPT type IGBT can be manufactured by a similar manufacturing process. Also, when an FZ wafer is used, an IGBT can be manufactured by a similar manufacturing process.

  Next, a manufacturing process when the present invention is applied to the above-described manufacturing method will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing an example of a state in which a support substrate is bonded to the surface of the wafer via an adhesive sheet in the process corresponding to FIG. 9-2. As shown in FIG. 3, for example, the adhesive sheet 50 has a base material 52 having a rigid base 52 on which one side of a base material 52 is bonded with a heat-foaming tape 51 whose adhesive strength is reduced by heat foaming and can be peeled off. The other surface of 52 has a configuration in which a UV tape 53 that can be peeled off when the adhesive is cured by UV irradiation and the adhesive strength is reduced is attached. Although not particularly limited, the wafer 60 is bonded to the heating foam tape 51, and the support substrate 70 is bonded to the UV tape 53.

  In this state, as shown in FIG. 4, the back surface of the wafer is ground with a grindstone 81 attached to a rotating spindle 80 until the thickness of the wafer 60 approaches a desired thickness. Next, as shown in FIG. 5, spin etching is performed so that the back surface of the wafer is uniformly etched. That is, an etching solution 83 containing a strong acid such as hydrogen fluoride or nitric acid is dropped from the etching solution nozzle 82 onto the back surface of the wafer 60 rotated at a high speed to etch the back surface of the wafer. As a result, the layer having the stress generated by grinding on the back surface of the wafer is removed. This grinding and etching process corresponds to the process shown in FIG.

  During the spin etching, a part of the etching solution 83 dropped on the back surface of the wafer may hang down on the side surface of the laminate including the wafer 60, the adhesive sheet 50, and the support substrate 70. Since the edges of the heat-foamed tape 51 and the UV tape 53 of the adhesive sheet 50 are exposed on the side surfaces of the laminate, the edges of the tapes 51 and 53 may be altered. For example, the edge portion of the heated foam tape 51 may be altered by contact with the etching solution 83, and the adhesive strength may not be reduced even when heated. The same applies to the case of the UV tape 53, and the edge portion of the UV tape 53 may be altered by contact with the etching solution 83, and the adhesive strength may not deteriorate even when irradiated with UV light.

  Thus, if the edge part of the adhesive sheet 50 changes in quality and becomes a poorly peeled part, the peripheral part of the wafer 60 remains bonded to the support substrate 70 when the wafer 60 is later detached from the support substrate 70. As a result, the wafer 60 cannot be easily detached from the support substrate 70. Therefore, as shown in FIGS. 1 and 2, before the wafer 60 is detached from the support substrate 70, the laser beam 84 is irradiated on the inside of the wafer 60 about several mm from the outer periphery of the wafer 60 by using a laser cutting machine (not shown). To do. Then, the laser beam 84 is caused to make a round along the peripheral edge of the wafer 60 with respect to the wafer 60 and cut so as to penetrate the central portion 61 of the wafer 60. 1 is a cross-sectional view taken along line AA in FIG.

  The poorly peeled portion 54 formed by the alteration of the adhesive sheet 50 can be formed only within a few millimeters from the outer periphery of the wafer 60. Therefore, by cutting the inner portion of the wafer 60 about several mm from the outer periphery, the central portion 61 of the wafer 60 is joined to the support substrate 70 by the defective peeling portion 54 of the adhesive sheet 50. 62. The area where the effective chip is formed on the wafer 60 is further inside than the inside of the wafer 60 by several mm from the outer periphery. Therefore, even if the wafer central portion 61 and the wafer peripheral portion 62 are separated by cutting a portion about several millimeters from the outer periphery of the wafer 60, the effective chips formed in the wafer central portion 61 are not damaged. Absent.

  After the wafer central portion 61 is separated from the wafer peripheral portion 62, as shown in FIG. 6, a laminate composed of the wafer 60, the adhesive sheet 50 and the support substrate 70 is placed on a hot plate 85 and heated. The wafer central portion 61 is bonded to the support substrate 70 through an adhesive sheet 50 that has not been altered. Therefore, in the wafer center portion 61, the adhesive force of the heating foam tape 51 is reduced. Thereby, the heating foam tape 51 of the wafer center portion 61 is peeled off, and the wafer center portion 61 is detached from the support substrate 70.

  The step of detaching the wafer central portion 61 from the support substrate 70 corresponds to the step shown in FIG. However, since the wafer 60 is bonded to the heating foam tape 51 here, the wafer 60 is heated without performing UV irradiation. When the wafer 60 is bonded to the UV tape, UV irradiation may be performed instead of heating. In the description here, the wafer central portion 61 is detached from the support substrate 70 in a state where the metal film to be the back electrode is not deposited.

  In the case where the wafer central portion 61 is detached from the support substrate 70 after the metal film to be an electrode is deposited on the back surface of the wafer 60, the operation is as follows. FIG. 7 is a cross-sectional view showing an example of a state in which a metal film 63 serving as a back electrode is deposited in the process corresponding to FIG. 10-2. As shown in FIG. 7, the metal film 63 is deposited not only on the back surface of the wafer 60, but also on the side surface of the laminate composed of the wafer 60, the adhesive sheet 50, and the support substrate 70. Therefore, the wafer 60, the adhesive sheet 50, and the support substrate 70 are connected by the metal film 63 attached to the side surface of the laminate. That is, the edge portion of the wafer 60, the edge portion of the adhesive sheet 50, and the edge portion of the support substrate 70 are in a state of being bonded.

  Also in this case, when the wafer 60 is later detached from the support substrate 70, the peripheral portion of the wafer 60 remains bonded to the support substrate 70, and the wafer 60 can be easily detached from the support substrate 70. It will disappear. Therefore, as shown in FIG. 8, before the wafer 60 is detached from the support substrate 70, a laser cutting machine (not shown) is located just inside the outer periphery of the wafer 60 (however, outside the region where effective chips are formed). ) Is irradiated with the laser beam 84, and the laser beam 84 is caused to circulate around the wafer 60 along the periphery of the wafer 60 and cut so as to penetrate the central portion 61 of the wafer 60.

  In this way, the central portion 61 of the wafer 60 is separated from the peripheral portion 62 of the wafer 60 that is bonded to the adhesive sheet 50 and the support substrate 70 by the metal film 63. Thereafter, the wafer central portion 61 is detached from the support substrate 70 by heating with a hot plate or the like. When the wafer 60 is bonded to the UV tape 53, UV irradiation is performed instead of heating.

  As an example, as the heating foam tape 51, for example, Nitto Denko Corporation No. 3195 can be used. Further, as the UV tape 53, for example, UB-3083D manufactured by Nitto Denko Corporation can be used. Further, when the target to be cut is Si as a laser source of the laser cutting machine, for example, a YAG laser having a wavelength of 1064 nm can be used. Further, when cutting the Si and the metal film to be the electrode, a YAG second harmonic laser having a wavelength of 532 nm can be used.

  With lasers of these wavelengths, it is not possible to cut materials with very good transparency such as glass and quartz. Therefore, if a substrate made of a material having extremely high transparency such as glass or quartz is used as the support substrate 70, the support substrate 70 is repeatedly reused because it is not damaged by laser irradiation when the wafer is cut by the laser. can do. In the manufacturing process described above, since the support substrate 70 is bonded to the UV tape 53, the UV tape 53 can be peeled from the support substrate 70 by irradiation with UV light.

  Further, the support substrate 70 has the same shape as the wafer 60 and may be the same size as the wafer 60 or may be slightly larger than the wafer 60. Although the thickness of the support substrate 70 is not specifically limited, For example, it is about 500-1000 micrometers. The support substrate 70 has sufficient rigidity to support the wafer 60. Further, since the state of the surface of the support substrate 70 (bonding surface with the wafer 60) greatly affects the flatness of the back surface of the wafer 60 after grinding, that is, the ground surface, the in-plane thickness of the surface of the support substrate 70 The variation is preferably 5 μm or less. Considering the above, a material such as quartz, glass, or Si is suitable for the support substrate 70.

  As described above, according to the embodiment, when the wafer 60 is detached from the support substrate 70, the wafer central portion 61 is separated from the wafer peripheral portion 62, so that the wafer 60 and the support substrate 70 are bonded. Even if the wafer edge portion of the adhesive sheet 50 is not deteriorated and the adhesive force of the wafer edge portion is not weakened, the wafer central portion 61 can be easily detached from the support substrate 70. Even if the wafer 60 and the support substrate 70 are connected by the metal film 63 that covers the side surfaces thereof, the wafer central portion 61 can be easily detached from the support substrate 70. Therefore, it is possible to easily manufacture a semiconductor element such as an IGBT having a thin device thickness by removing the wafer central portion 61 from the support substrate 70 while preventing the wafer 60 from cracking.

  In addition, according to the embodiment, since the wafer 60 is cut using a laser cutting machine, a curved line that matches the outer shape of the wafer that cannot be cut by a grinder of a grindstone blade that is usually used for cutting the wafer. Cutting can be performed easily. Furthermore, compared to the case where a wafer having a thickness of 100 μm or less is cut by a dicer with a grindstone blade, there is no phenomenon of chipping of the cut surface (chipping), and no mechanical force is applied, so cracks and the like are hardly generated. There is also an effect.

  In the above, since the surface configuration of the semiconductor element is not limited in the present invention, the surface side element structure portion of the semiconductor element may be a planar type or a trench type. Further, the present invention is not limited to an IGBT having a wafer thickness of 70 μm after back grinding, but includes a step of back grinding the back surface of the wafer to reduce the wafer thickness to 100 μm or less. Applicable to.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device having a thin device thickness, and in particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for the production of power semiconductor elements such as IGBTs used in the industrial field and consumer equipment fields such as microwave ovens, rice cookers or strobes.

It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is a top view for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method concerning embodiment of this invention. It is FIG. (1) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (2) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (The 3) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (4) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (5) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (6) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is FIG. (7) which shows the outline of the whole process of the manufacturing method concerning embodiment of this invention. It is sectional drawing which shows the structure of NPT type IGBT. It is sectional drawing which shows the structure of FS type IGBT. It is a figure (the 1) which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is FIG. (2) which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is FIG. (The 3) which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is FIG. (The 4) which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is FIG. (5) which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure (the 1) which shows the manufacturing process of FS type IGBT using the conventional epitaxial wafer. It is FIG. (2) which shows the manufacturing process of FS type IGBT using the conventional epitaxial wafer. It is FIG. (The 3) which shows the manufacturing process of FS type IGBT using the conventional epitaxial wafer. It is FIG. (The 4) which shows the manufacturing process of FS type IGBT using the conventional epitaxial wafer. It is FIG. (5) which shows the manufacturing process of FS type IGBT using the conventional epitaxial wafer.

Explanation of symbols

31, 50 Adhesive sheet 32, 70 Support substrate 60 Wafer 61 Wafer center portion 62 Wafer peripheral portion 63 Metal film 84 Laser light

Claims (3)

Bonding the support substrate to the surface of the semiconductor wafer;
Processing the back side of the semiconductor wafer while the support substrate is bonded, and thinning the semiconductor wafer;
Separating the peripheral portion of the thinned semiconductor wafer from the central portion;
Separating the wafer center portion separated from the wafer peripheral portion from the support substrate;
The manufacturing method of the semiconductor element characterized by the above-mentioned. The semiconductor wafer and the support substrate are joined via a double-sided adhesive type adhesive sheet that can be peeled off by heat foaming, or a double-sided adhesive type adhesive sheet that can be peeled off when the adhesive is cured by UV light irradiation. ,
By irradiating a laser beam along the outer periphery of the semiconductor wafer, the wafer central portion and the wafer peripheral portion are separated,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer central portion is separated from the support substrate by heating or irradiation with UV light. The semiconductor wafer and the support substrate are joined via a double-sided adhesive type adhesive sheet that can be peeled off by heat foaming, or a double-sided adhesive type adhesive sheet that can be peeled off when the adhesive is cured by UV light irradiation. ,
After thinning the semiconductor wafer by processing the back side of the semiconductor wafer, the method includes a step of forming a metal film on the back surface of the thinned semiconductor wafer before separating the peripheral portion of the wafer from the central portion of the wafer. And
By irradiating a laser beam along the outer periphery of the semiconductor wafer, by removing the metal film and the semiconductor in the irradiated region, the wafer central portion and the wafer peripheral portion are separated,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer central portion is separated from the support substrate by heating or irradiation with UV light.

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