JP2004234438A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control circuit, which realizes a high speed access even though each access is individually requested for each address. <P>SOLUTION: The memory control circuit comprises a counter 26 included in a memory controller 16 and a control signal generator 24. The counter 26 determines whether or not a new access is requested, while a number of the counter is countdown to zero, i.e. a data following an access request is transferred to SDRAM 14, after the access request from a CPU 12 to the memory controller 16 is executed in a single unit transfer mode. If a new access is requested, the counter 26 also determines whether a specified address designated by each access is continuous or not. The control signal generator 24, then, controls a selector 50 and an input and output switching circuit 52 in a manner that the data following each access request is transferred to the SDRAM 14. Consequently, the memory control circuit can realize the same high speed access for the access based on the single unit transfer mode as the access based on a burst mode. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to a memory control circuit, and more particularly to, for example, making a transition to a first state accessible to a memory in response to an access request, accessing the memory that has transitioned to the first state in accordance with the access request, and going to the first state. And a memory control circuit that causes the memory to transition to the inaccessible second state at a specific timing after the transition.
[0002]
[Prior art]
An example of a conventional memory control circuit is disclosed in Patent Document 1. According to this conventional technique, when a CPU (Central Processing Unit) accesses a memory in a burst mode, the lower digit of the first address is set in a counter (counter means). The counter counts up at a timing earlier than the read cycle by the CPU, and data is read from the memory based on the counted lower-order address and the remaining upper-order address, and the read data is latched. (Data holding means). The CPU reads data from this latch. In other words, data is sequentially read out at a timing earlier than the read cycle by the CPU, and so to speak, the data is pre-read, so that higher-speed access is possible.
[0003]
[Patent Document 1]
JP-A-9-34827
[0004]
[Problems to be solved by the invention]
On the other hand, depending on the configuration of the CPU, access may be performed in the single transfer mode even when access in the burst mode is possible, in other words, even when continuous addresses in the memory are accessed. Since the operation of the CPU in the single transfer mode is simpler than the operation in the burst mode, the single transfer mode is frequently used in a CPU having a relatively simple configuration without a cache memory, for example. However, in the single transfer mode, an access request is issued individually for each address, and accesses are individually executed in accordance with the access requests. Therefore, so-called overhead increases, and as a result, the access speed decreases. On the other hand, the above-described conventional technique is based on the premise of the burst mode, and cannot exert the above-described effects in the single transfer mode.
[0005]
Therefore, a main object of the present invention is to provide a memory control circuit capable of realizing high-speed access even when an access request is individually issued for each address.
[0006]
[Means for Solving the Problems]
According to a first aspect, a transition is made to a first state in which a memory can be accessed in response to an access request, a memory that has transitioned to the first state is accessed in accordance with the access request, and a specific timing after the transition to the first state. A memory control circuit for causing the memory to transition to a second state in which the memory is inaccessible, wherein when a specific access request that satisfies a specific condition is issued before a specific timing arrives, an access unit that accesses the memory in accordance with the specific access request; The memory control circuit is characterized in that the specific condition includes an address condition that an access destination address according to the access request and an access destination address according to the specific access request are continuous with each other.
[0007]
A second invention is a digital camera including the memory control circuit according to the first invention.
[0008]
[Action]
According to the present invention, the memory transitions to the first state in response to the access request, and is accessed according to the access request. When the specific timing after the transition to the first state arrives, the memory transitions to the inaccessible second state. However, when a specific access request that satisfies a specific condition, specifically, a condition that an address following an access destination address according to an access request issued earlier is set as an access destination before a specific timing arrives, is issued. The access means executes an access according to the specific access request, following an access to the memory executed according to the previous access request.
[0009]
In one embodiment of the present invention, when the specific access request is issued before the specific timing has arrived, the specific timing is delayed by the delay unit.
[0010]
Specifically, after the transition to the first state, the clock is counted by the counting means. When the count value of the counting means indicates a specific value, the timing is set as the specific timing. The delay unit delays the specific timing by temporarily disabling the counting unit.
[0011]
【The invention's effect】
According to the present invention, when a specific access request that satisfies a specific condition is issued when the memory is in the first accessible state, the specific access is performed following the access to the memory executed in accordance with the previous access request. Access according to the request is performed. That is, even when an access request is individually issued for each address, if a specific condition is satisfied, access is performed continuously, and as a result, high-speed access is realized.
[0012]
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0013]
【Example】
Referring to FIG. 1, a memory access circuit 10 of this embodiment is applied to a digital camera, and includes a CPU 12, an SDRAM 14 as a main storage device, and a memory controller 16 which controls access to the SDRAM 14 by the CPU 12. Including. The CPU 12 and the memory controller 16 are integrally formed by an ASIC (Application Specific IC) 18.
[0014]
An ADDR (Address) signal, a WRITE signal, a READYin signal, a TRANS signal, a SEL signal, a READYout signal, a WDATA signal, and an RDATA signal are exchanged between the CPU 12 and the memory controller 16. Among these, the ADDR signal is a 32-bit signal provided from the CPU 12 to the memory controller 16, and the ADDR signal specifies an access destination address in the SDRAM 14 by the CPU 12.
[0015]
The WRITE signal is one of the control signals, and is provided from the CPU 12 to the memory controller 16. Whether this WRITE signal is at the “H (high)” level or the “L (low)” level indicates which of the CPU 12 is instructing data writing (writing) or reading (reading). You. Specifically, when the WRITE signal is at “H (high)” level, it indicates data writing, and when it is at “L (low)” level, it indicates data reading.
[0016]
The READYin signal is also a control signal provided from the CPU 12 to the memory controller 16, and the READYin signal indicates whether or not the CPU 12 is in a so-called command waiting (standby) state as viewed from the memory controller 16. For example, when the READYin signal is at “H” level, it indicates that the CPU 12 is in a command waiting state, in other words, when a command is given, the CPU 12 can operate immediately in response to the command. On the other hand, when the READYin signal is at the “L” level, it indicates that the CPU 12 is executing some processing and cannot accept another command.
[0017]
The TRANS signal is a signal indicating a data transfer method, and is given from the CPU 12 to the memory controller 16. When the CPU 12 accesses in the single transfer mode, the TRANS signal indicates information "NON (Non Sequence)" described later. After the information "NON", information "IDOL" is shown. When accessing in the burst mode, the TRANS signal first indicates information "NON", and thereafter, information "SEQ (Sequence)" is continuously indicated by the number corresponding to the burst length.
[0018]
The SEL signal is a so-called chip select signal for the memory controller 16 of the CPU 12, and is an active "H" signal here. That is, when issuing an access request to the memory controller 16, the CPU 12 sets this SEL signal to “H” level.
[0019]
The READYout signal is a control signal provided from the memory controller 16 to the CPU 12, and is a signal indicating whether or not the memory controller 16 is in a state capable of receiving an access request from the CPU 12. Specifically, when the READYout signal is at “H” level, the memory controller 16 is in a state where it can accept an access request from the CPU 12, and when it is at “L” level, it cannot accept the access request. The state is indicated.
[0020]
The WDATA signal is a 32-bit (1 word) signal representing data to be written to the SDRAM 14, and is given from the CPU 12 to the memory controller 16. The RDATA signal is a 32-bit signal representing data read from the SDRAM 14 and is given from the memory controller 16 to the CPU 12.
[0021]
On the other hand, the memory controller 16 and the SDRAM 14 (ASIC 18) are connected to each other via an address bus 100, a control bus 102, and a data bus 104.
[0022]
By the way, the CPU 12 in this embodiment has a relatively simple configuration without a built-in cache memory. When an access in the burst mode is possible, in other words, a continuous address in the SDRAM 14 is set as an access destination. In some cases, access may be made in the single transfer mode. Although not shown in the figure, in this embodiment, a so-called external cache memory is provided.
[0023]
Here, if the memory access circuit 10 individually accesses each address in response to the access request in the single transfer mode, the overhead increases as described above, and the access as the entire memory access circuit 10 is performed. Speed decreases. Therefore, even when an access request is made in the single transfer mode, the memory access circuit 10 according to the present embodiment performs the following high-speed access to realize the same high-speed access as in the burst mode when continuous addresses are specified as access destinations. It is configured as follows.
[0024]
That is, the memory controller 16 includes a REQ (Request) signal generation circuit 20, an ACCESS signal generation circuit control 22, a control signal generation circuit 24, a counter 26, a READY signal generation circuit 28, an ACK (Acknowledgment) signal generation circuit 30, and an address converter 32. , Flip-flop (F / F) 34, latch circuit 36, three flip-flop groups 38, 40, 42, three latch circuit groups 44, 46, 48, selector 50, and input / output switching circuit 52. Further, input / output switching circuit 52 includes an output gate circuit group 54 and an input gate circuit group 56.
[0025]
The flip-flop group 38 to which the ADDR signal is input is constituted by the same number (32) of flip-flops as the number of bits of the ADDR signal, and the latch circuit to which the output signal of the flip-flop group 38 is input. The group 44 also includes the same number (32) of latch circuits. Each of the latch circuit groups 46 and 48 to which the WDATA signal is input is constituted by the same number (32) of latch circuits as the number of bits of the WDATA signal. The flip-flop group 40 to which a signal is input via the selector 50 is also configured by the same number of flip-flops. Further, the flip-flop group 42 that outputs the RDATA signal is also configured by the same number (32) of flip-flops as the number of bits of the RDATA signal. Each of the output gate circuit group 54 and the input gate circuit group 56 is also composed of 32 gate circuits.
[0026]
Referring to FIG. 2, the operation of memory controller 16 when writing data to SDRAM 14 in response to an access request in the single transfer mode from CPU 12 will be described. The CPU 12, the SDRAM 14, and the memory controller 16 (circuits 20 to 56) operate in synchronization with a system clock signal (hereinafter, referred to as a CLK signal) which is a rectangular wave signal output from an oscillation circuit (not shown).
[0027]
For example, it is assumed that an access request is issued from the CPU 12 to the memory controller 16 at a certain rising time t0 of the CLK signal shown in FIG. Specifically, the TRANS signal in FIG. 2B indicates “NON”, the SEL signal in FIG. 2C is at “H” level, and the READYin signal in FIG. H level. At this time, the WRITE signal is at the “H” level as shown in FIG. 2E, and the ADDR signal represents an arbitrary address “A” as shown in FIG. 2F.
[0028]
The TRANS signal, the SEL signal, and the READYin signal are input to the REQ signal generation circuit 20 in the memory controller 16, and the REQ signal generation circuit 20 receives the REQ signal and sets the active "L" REQ signal as shown in FIG. The signal is output for one clock period of the CLK signal. The REQ signal is input to the READY signal generation circuit 28, and the READY signal generation circuit 28 receives this REQ signal and outputs an "L" level READYout signal as shown in FIG. This READYout signal is input to the CPU 12, whereby the CPU 12 recognizes that the memory controller 16 cannot receive a new access request.
[0029]
The REQ signal is also input to the ACCESS signal generation circuit 22. The ACCESS signal generation circuit 22 receives the REQ signal, and more specifically, receives the REQ signal at "L" level, and As shown in (i), at the rising time t1 of the CLK signal following the time t0, an active ACCESS signal is output. That is, the ACCESS signal is asserted. As will be described later, this asserted state is continued until a series of access processing by the memory controller 16 ends.
[0030]
Further, the REQ signal is also input to the latch circuit group 44, and the latch circuit group 44 latches the output signal of the flip-flop group 38 in synchronization with the rise of the REQ signal. As a result, the above-mentioned address “A” represented by the ADDR signal delayed by one clock of the CLK signal by the flip-flop group 38 is held in the latch circuit group 44.
[0031]
The REQ signal is also input to the latch circuit 36, and the latch circuit 36 latches the output signal of the flip-flop 34 in synchronization with the rise of the REQ signal. The WRITE signal is input to the flip-flop 34, whereby the “H” level WRITE signal is held in the latch circuit 36.
[0032]
At time t1, as shown in FIG. 2 (j), the CPU 12 outputs a WDATA signal "D0" corresponding to the above-mentioned address "A". Then, this WDATA signal is input to two latch circuit groups 46 and 48, respectively.
[0033]
The ACCESS signal output from the ACCESS signal generation circuit 22 is input to the ACK signal generation circuit 30. As shown in FIG. 2 (k), the ACK signal generation circuit 30 outputs an active “L” ACK signal at the second rising time t2 of the CLK signal from the rising of the ACCESS signal. That is, the ACK signal is asserted. The assertion of the ACK signal at the second rising edge of the CLK signal from the rising edge of the ACCESS signal is determined in advance when the memory controller 16 is designed.
[0034]
The ACK signal is input to the READY signal generation circuit 28, and in response to the assertion of the ACK signal, the READY signal generation circuit 28, as shown in FIG. At time t3, the READYout signal is set to the “H” level. As a result, the CPU 12 recognizes that the memory controller 16 is ready to accept the access request. In addition, in response to the READYout signal becoming “H” level, the CPU 12 sets the READYin signal to “H” level as shown in FIG.
[0035]
The ACK signal is also input to the counter 26. In response to the assertion of the ACK signal, the counter 26 sets itself to a value of "3" as an initial value at a time point t3 as shown in FIG. As will be described later, the memory controller 16 of this embodiment is designed so that when writing data to the SDRAM 14, an active command is issued to the SDRAM 14 and then a write command is issued 3 clocks after the CLK signal. The value “3” is set as the initial value of the counter 26 for the purpose of the design. The counter 26 decrements the set value by “1” at every rise of the CLK signal, that is, counts down, and stops the counting operation when the count value becomes “0”.
[0036]
The count value of the counter 26 is input to the control signal generation circuit 24, and when the initial value “3” is set as the count value, in other words, after the ACK signal is asserted, At the next rising edge t3 of the CLK signal, the above-mentioned active (Actv) command is issued as shown in FIG. Then, after issuing this active command, the above-mentioned write (Write) command is issued three clocks after the CLK signal. The command issued by the control signal generation circuit 24 is input to the SDRAM 14 via the control bus 102.
[0037]
The READYout signal output from the above-described READY signal generation circuit 28 is also input to the latch circuit group 46. The latch circuit group 46 latches the WDATA signal at the rising edge time t4 of the CLK signal next to the time point t3 when the READYout signal goes to the “H” level. As a result, the data “D0” corresponding to the address “A” is held by the latch circuit group 46 as shown in FIG. At this time point t4, the count value of the counter 26 becomes “2”.
[0038]
At time t4 (strictly, slightly later than time t4), the CPU 12 issues an access request to the memory controller 16 specifying the address "A + 4 (byte)" following the address "A" as a write destination. It is assumed that this access request is recognized at the rising edge t5 of the CLK signal following the timing t4. Specifically, at time t5, the TRANS signal in FIG. 2B indicates “NON”, the SEL signal in FIG. 2C is at “H” level, and the READYin signal in FIG. Are at "H" level, and the WRITE signal is at "H" level.
[0039]
These TRANS signal, SEL signal and READYin signal are input to the REQ signal generation circuit 20 as described above, whereby the REQ signal generation circuit 20 recognizes that an access request has been issued. However, the REQ signal generation circuit 20 is also supplied with the ACCESS signal from the ACCESS signal generation circuit 22. When the ACCESS signal is asserted, that is, when the ACCESS signal is asserted, that is, the access processing for the previous access request is performed. If the access has not been completed, the REQ signal is not output even if a new access request is issued (not set to “L” level).
[0040]
The above-described TRANS signal, SEL signal and READYin signal are also input to the counter 26, whereby the counter 26 also recognizes that a new access request has been made from the CPU 12. The ADDR signal from the CPU 12 and the ADDR signal according to the previous access request from the latch circuit group 44 are also input to the counter 26, and the counter 26 compares these ADDR signals with each other. It is determined whether the specified address “A” by the previous access request and the specified address “A + 4” by the current access request are continuous.
[0041]
Here, when the counter 26 determines that the designated address “A” by the previous access request and the designated address “A + 4” by the current access request are consecutive addresses, and that the count value of the counter 26 is not “0”. , The counting operation is suspended as shown in FIG. Then, at a rising time point t6 of the CLK signal subsequent to the time point t5, a control signal for enabling the latch circuit group 48 is generated. Thus, the data “D1” corresponding to the address “A + 4” is held by the latch circuit 48 as shown in FIG.
[0042]
The time point t6 corresponds to a timing three clocks after the CLK signal from the issuance of the above-mentioned active command from the control signal generation circuit 24. Therefore, the control signal generation circuit 24 issues a write command in accordance with this timing. At the same time, the control signal generation circuit 24 outputs the output signal (WD-0 signal) of the latch circuit group 46 to the selector 50, flip-flop group 40, input / output switching circuit 52 (output gate circuit group 54) and data bus 104. The selector 50 and the input / output switching circuit 52 are controlled so as to be input to the SDRAM 14 via the selector 50. As a result, the data "D0" according to the first access request is transferred to the SDRAM 14, as shown in FIG. The ADDR signal held in the above-described latch circuit group 44, that is, an ADDR signal according to the first access request is input to the SDRAM 14 via the address converter 32 and the address bus 100. Therefore, the data "D0" input to the SDRAM 14 is written to the area of the address "A" specified by the first access request.
[0043]
Then, at the rising time point t7 of the CLK signal following the time point t6, the control signal generation circuit 24 outputs the output signal (WD-1 signal) of the latch circuit group 48 to the selector 50, the flip-flop group 40, and the input / output switching circuit 52 ( The selector 50 and the input / output switching circuit 52 are controlled so as to be input to the SDRAM 14 via the output gate circuit group 54) and the data bus 104. As a result, the data "D1" according to the second access request is transferred to the SDRAM 14, as shown in FIG. At this time, since the control signal generation circuit 24 does not issue any command, the write destination address is updated by one word (= 4 bytes) in the SDRAM 14 as in the normal burst mode, and the address "A + 4" is written. Is specified. Therefore, the data “D0” according to the second access request is written to the area of the address “A + 4” according to the second access request.
[0044]
At this time point t7, the count value of the counter 26 becomes “0”. This count value is also input to the ACK signal generation circuit 30, and the ACK signal generation circuit 30 recognizes that the count value has become “0” at the next rising edge t8 of the CLK signal. Then, at this time t8, the ACK signal is negated to the “H” level as shown in FIG.
[0045]
Further, in response to the count value of the counter 26 becoming “0”, the control signal generation circuit 24 issues a burst stop (BST) command at time t8 as shown in FIG. The issuance of the burst stop command is also transmitted to the ACCESS signal generation circuit 22.
[0046]
In response to the issuance of the burst stop command, the ACCESS signal generation circuit 22 negates the ACCESS signal to the “L” level at a rising time t9 of the next CLK signal after the time t8. At the same time, the control signal generation circuit 24 issues a precharge (PALL) command. Thus, a series of access processing ends.
[0047]
As can be understood from the above description, according to this embodiment, after the access request based on the single transfer mode is made, the data (in accordance with the access request) is kept until the count value of the counter 26 becomes “0”. Until D0) is transferred to the SDRAM 14, new access requests are made. If the addresses specified by these access requests are consecutive, the data (D0 and D1) according to each access request is burst. It is transferred continuously as in the mode. That is, the same high-speed access as in the burst mode can be realized for an access request in the single transfer mode.
[0048]
If the memory controller 16 individually accesses the SDRAM 14 in response to, for example, an individual access request from the CPU 12, the data "D1" according to the above-mentioned second access request will be denoted by reference numeral 200 in FIG. As shown, the data "D0" according to the first access request is transferred at a timing delayed by several clocks of the CLK signal after the transfer. That is, high-speed access as in this embodiment cannot be realized.
[0049]
In this embodiment, the case where data is written from the CPU 12 to the SDRAM 14 has been described, but the same applies to the case where data is read from the SDRAM 14 to the CPU 12. However, in this case, the data read from SDRAM 14 is transferred to CPU 12 via data bus 104, input / output switching circuit 52 (input gate circuit group 56) and flip-flop group 42.
[0050]
In this embodiment, the case where two data (D0 and D1) are continuously transferred has been described. However, more data can be continuously transferred. However, in this case, the same number of latch circuit groups as the latch circuit group 46 or 48 is required as the number (continuous number) of data to be continuously transferred.
[0051]
Furthermore, in this embodiment, the case where the present invention is applied to a digital camera has been described, but it goes without saying that the present invention can be applied to electronic devices other than the digital camera.
[0052]
Further, the CPU 12 and the memory controller 16 are formed integrally by the ASIC 18, but may be configured separately.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.
FIG. 2 is a timing chart showing an operation of each main part at the time of data writing in the embodiment of FIG.
[Explanation of symbols]
10 Memory access circuit
12 ... CPU
14 ... SDRAM
16 ... Memory controller
20 REQ signal generation circuit
24 ... Control signal generation circuit
26 ... Counter
46, 48 ... Latch circuit group

Claims (4)

In response to an access request, a transition is made to a first state in which a memory is accessible, the memory that has transitioned to the first state is accessed according to the access request, and the memory is accessed at a specific timing after the transition to the first state. In a memory control circuit that causes the state to transition to the inaccessible second state,
An access unit for accessing the memory according to the specific access request when a specific access request satisfying a specific condition is issued before the specific timing arrives,
The memory control circuit, wherein the specific condition includes an address condition that an access destination address according to the access request and an access destination address according to the specific access request are continuous with each other. 2. The memory control circuit according to claim 1, further comprising delay means for delaying said specific timing when said specific access request is issued before said specific timing arrives. A counting unit that counts a clock after the transition to the first state;
The specific timing is a timing at which the count value of the counting means indicates a specific value,
3. The memory control circuit according to claim 2, wherein said delay means temporarily disables said counting means. A digital camera comprising the memory control circuit according to claim 1.

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