JP2003271095A - Driving circuit for current control element and image display device - Google Patents
Driving circuit for current control element and image display deviceInfo
- Publication number
- JP2003271095A JP2003271095A JP2002070730A JP2002070730A JP2003271095A JP 2003271095 A JP2003271095 A JP 2003271095A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2003271095 A JP2003271095 A JP 2003271095A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- control element
- current control
- drive
- drive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 72
- 230000003071 parasitic effect Effects 0.000 claims description 52
- 230000005669 field effect Effects 0.000 claims description 37
- 238000007599 discharging Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0847—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
Landscapes
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electronic Switches (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、有機ＥＬ（Elec
tro Luminescence) 素子等の電流制御素子を発光させる
ための電流制御素子の駆動回路及びこれを用いた画像表
示装置に関する。TECHNICAL FIELD The present invention relates to an organic EL (Elec
The present invention relates to a current control element drive circuit for causing a current control element such as a tro Luminescence) element to emit light, and an image display device using the same.
【０００２】[0002]
【従来の技術】有機ＥＬディスプレイ等のように、電流
制御によって駆動される発光素子（電流制御素子）の駆
動回路を、平面状に多数配置して形成されている画像表
示装置では、各電流制御素子に流れる電流の制御は、駆
動回路において、駆動トランジスタのゲート−ソース間
の保持容量に対して、信号線から選択ゲートトランジス
タを介して、電流制御素子の表示輝度に応じた電流が流
れるようにプログラムされた信号電荷を書き込んで、そ
の信号電荷を表示期間中、保持することによって行われ
る。2. Description of the Related Art In an image display device such as an organic EL display in which a large number of drive circuits for light emitting elements (current control elements) driven by current control are arranged in a plane, each current control is performed. The current flowing through the element is controlled so that the current corresponding to the display brightness of the current control element flows from the signal line to the storage capacitor between the gate and source of the drive transistor through the selection gate transistor in the drive circuit. This is performed by writing programmed signal charges and holding the signal charges during the display period.
【０００３】図１５は、第１の従来例の電流制御素子の
駆動回路の構成を示したものであって、特開平８−２３
４６８３号公報に開示されているものである。この従来
例の電流制御素子の駆動回路は、図１５に示すように、
電源線１１と接地線１２と信号線１３との間に接続され
た、選択ゲートトランジスタ１４と、保持容量１５と、
駆動トランジスタ１６と、電流制御素子１７と、寄生容
量１８とからなっている。選択ゲートトランジスタ１４
は、Ｎチャネル電界効果トランジスタからなり、ゲート
電極を選択線（不図示）に接続され、ドレイン電極を信
号線１３に接続され、ソース電極を駆動トランジスタ１
６のゲート電極に接続されている。保持容量１５は、駆
動トランジスタ１６のゲート電極と電源線１１との間に
接続されている。駆動トランジスタ１６は、Ｐチャネル
電界効果トランジスタからなり、ゲート電極を選択ゲー
トトランジスタ１４のソース電極と保持容量１５の一端
に接続され、ソース電極を電源線１１に接続され、ドレ
イン電極を電流制御素子１７のアノードに接続されてい
る。電流制御素子１７は、駆動トランジスタ１６のドレ
イン電極と接地線１２との間に接続され、駆動トランジ
スタ１６の電流ＩＬに応じた輝度で発光する。寄生容量
１８は、電流制御素子１７の両端の寄生容量である。FIG. 15 shows the configuration of a drive circuit for a current control element of the first conventional example, which is disclosed in Japanese Patent Laid-Open No. 8-23.
It is disclosed in Japanese Patent No. 4683. As shown in FIG. 15, the drive circuit of the current control element of this conventional example is as follows.
A select gate transistor 14 connected between the power supply line 11, the ground line 12 and the signal line 13, a storage capacitor 15;
It is composed of a drive transistor 16, a current control element 17, and a parasitic capacitance 18. Select gate transistor 14
Is an N-channel field effect transistor, the gate electrode is connected to a selection line (not shown), the drain electrode is connected to the signal line 13, and the source electrode is connected to the drive transistor 1.
6 gate electrodes. The storage capacitor 15 is connected between the gate electrode of the drive transistor 16 and the power supply line 11. The drive transistor 16 is composed of a P-channel field effect transistor, has a gate electrode connected to the source electrode of the selection gate transistor 14 and one end of the storage capacitor 15, a source electrode connected to the power supply line 11, and a drain electrode connected to the current control element 17. Connected to the anode of. The current control element 17 is connected between the drain electrode of the drive transistor 16 and the ground line 12, and emits light with a brightness corresponding to the current IL of the drive transistor 16. The parasitic capacitance 18 is a parasitic capacitance at both ends of the current control element 17.
【０００４】図１５に示された従来の電流制御素子の駆
動回路では、選択期間中に、選択ゲートドライバ（不図
示）からロウ（行）方向に出力された選択信号が、選択
された行の各駆動回路の選択ゲートトランジスタ１４の
ゲート電極に与えられて、該当する行の選択ゲートトラ
ンジスタ１４が導通状態になることによって、駆動ドラ
イバ（不図示）からカラム（列）方向に出力された信号
電圧ＶＤＡＴＡが、選択された信号線１３を経て、駆動
トランジスタ１６のゲート−ソース間に印加される。駆
動回路が選択期間から非選択期間に切り替えられると、
選択ゲートトランジスタ１４が導通状態から非導通状態
になる。このとき、駆動トランジスタ１６のゲート−ソ
ース間電圧ＶＧＳは、保持容量１５によって保持されて
いるため、非選択期間（保持期間）中も、駆動トランジ
スタ１６は、書き込まれた信号電圧に応じた電流ＩＤＳ
を、電流制御素子１７に供給し続ける。In the conventional drive circuit of the current control element shown in FIG. 15, the selection signal output from the selection gate driver (not shown) in the row direction during the selection period is applied to the selected row. A signal voltage output from a drive driver (not shown) in the column direction by being applied to the gate electrode of the select gate transistor 14 of each drive circuit and turning on the select gate transistor 14 of the corresponding row. VDATA is applied between the gate and source of the drive transistor 16 via the selected signal line 13. When the drive circuit is switched from the selected period to the non-selected period,
The selection gate transistor 14 changes from the conductive state to the non-conductive state. At this time, since the gate-source voltage VGS of the driving transistor 16 is held by the holding capacitor 15, the driving transistor 16 keeps the current IDS corresponding to the written signal voltage even during the non-selection period (holding period).
Is continuously supplied to the current control element 17.
【０００５】図１６は、駆動トランジスタの特性がばら
ついているときのＩＤＳ−ＶＧＳ特性を示したものであ
る。駆動トランジスタのＩＤＳ−ＶＧＳ特性は、個々の
トランジスタによってばらつきがあり、特にしきい値の
ばらつきが大きい。そのため、駆動トランジスタのゲー
ト−ソース間電圧ＶＧＳとして、同一の信号電圧ＶＤＡ
ＴＡが与えられた場合でも、駆動トランジスタの出力電
流ＩＤＳは、個々のトランジスタによって、ＩＬ１，Ｉ
Ｌ２又はＩＬ３のようにばらつく。ドレイン−ソース間
電流ＩＤＳは、そのまま電流制御素子１７に流れるた
め、各駆動回路に同じ信号電圧ＶＤＡＴＡを入力して
も、電流制御素子１７に流れる電流にばらつきが生じる
ことになる。さらに、非選択期間中も、駆動トランジス
タ１６のゲート−ソース間電圧ＶＧＳは、保持容量１５
によって保持されるため、信号電圧ＶＤＡＴＡが同じ場
合でも、駆動トランジスタ１６のばらつきに基づいて、
駆動回路によって異なる電流が電流制御素子１７に流れ
続ける。このため、同一信号電圧を書き込んでも、各電
流制御素子の発光輝度にばらつきが発生するという問題
があった。FIG. 16 shows the IDS-VGS characteristics when the characteristics of the drive transistor vary. The IDS-VGS characteristics of the drive transistor vary depending on the individual transistor, and the threshold variation in particular is large. Therefore, the same signal voltage VDA is used as the gate-source voltage VGS of the driving transistor.
Even when TA is applied, the output current IDS of the drive transistor is IL1, I
It varies like L2 or IL3. Since the drain-source current IDS flows through the current control element 17 as it is, even if the same signal voltage VDATA is input to each drive circuit, the current flowing through the current control element 17 varies. Further, even during the non-selection period, the gate-source voltage VGS of the drive transistor 16 remains at the storage capacitor 15
Therefore, even if the signal voltage VDATA is the same,
Different currents continue to flow in the current control element 17 depending on the drive circuit. Therefore, even if the same signal voltage is written, there is a problem in that the emission brightness of each current control element varies.
【０００６】このような、駆動トランジスタのしきい値
ばらつきによって生じる駆動電流のばらつきを防止する
ための方法として、下記の文献に記載されたものが提案
されている。
SID' 99,pp.11-14 ; A Polysilicon Active Matrix Org
anic Light EmittingDiode Display with Integrated D
rivers, R.dawson et alAs a method for preventing such a variation in the drive current caused by a variation in the threshold value of the drive transistor, the method described in the following documents has been proposed. SID '99, pp.11-14; A Polysilicon Active Matrix Org
anic Light Emitting Diode Display with Integrated D
rivers, R.dawson et al
【０００７】図１７は、第２の従来例の電流制御素子の
駆動回路の構成を示したものである。この従来例の電流
制御素子の駆動回路は、図１７に示すように、電源線１
１と接地線１２と信号線１３との間に接続された、選択
ゲートトランジスタ１４Ａと、保持容量１５と、駆動ト
ランジスタ１６と、電流制御素子１７と、寄生容量１８
と、デカップリング容量１９と、スイッチングトランジ
スタ２０，２１とからなっている。選択ゲートトランジ
スタ１４Ａは、Ｐチャネル電界効果トランジスタからな
り、ゲート電極を選択線（不図示）に接続され、ソース
電極を信号線１３に接続され、ドレイン電極をデカップ
リング容量１９の一端に接続されている。保持容量１５
は、駆動トランジスタ１６のゲート電極と電源線１１と
の間に接続されている。駆動トランジスタ１６は、Ｐチ
ャネル電界効果トランジスタからなり、ゲート電極をデ
カップリング容量１９の他端と保持容量１５の一端に接
続され、ソース電極を電源線１１に接続され、ドレイン
電極をスイッチングトランジスタ２１のソース電極に接
続されている。FIG. 17 shows the configuration of a drive circuit for the current control element of the second conventional example. As shown in FIG. 17, the drive circuit of the current control element of this conventional example has a power supply line 1 as shown in FIG.
1, the selection gate transistor 14A, the storage capacitor 15, the drive transistor 16, the current control element 17, and the parasitic capacitance 18 which are connected between the ground line 12, the ground line 12, and the signal line 13.
And a decoupling capacitor 19 and switching transistors 20 and 21. The selection gate transistor 14A is formed of a P-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a source electrode connected to the signal line 13, and a drain electrode connected to one end of the decoupling capacitor 19. There is. Storage capacity 15
Are connected between the gate electrode of the drive transistor 16 and the power supply line 11. The drive transistor 16 is a P-channel field effect transistor, and has a gate electrode connected to the other end of the decoupling capacitor 19 and one end of the storage capacitor 15, a source electrode connected to the power supply line 11, and a drain electrode connected to the switching transistor 21. It is connected to the source electrode.
【０００８】電流制御素子１７は、スイッチングトラン
ジスタ２１のドレイン電極と接地線１２との間に接続さ
れていて、駆動トランジスタ１６の電流に応じた輝度で
発光する。寄生容量１８は、電流制御素子１７の両端の
寄生容量である。デカップリング容量１９は、選択ゲー
トトランジスタ１４Ａのドレイン電極と駆動トランジス
タ１６のゲート電極間に接続されていて、これらの間を
直流的に分離する。スイッチトランジスタ２０は、Ｐチ
ャネル電界効果トランジスタからなり、ゲート電極をリ
セット線（不図示）に接続され、ソース電極を駆動トラ
ンジスタ１６のゲート電極に接続され、ドレイン電極を
駆動トランジスタ１６のドレイン電極に接続されてい
る。スイッチングトランジスタ２１は、Ｐチャネル電界
効果トランジスタからなり、ゲート電極をリセット線に
接続され、ソース電極を駆動トランジスタ１６のドレイ
ン電極に接続され、ドレイン電極を電流制御素子１７の
一端に接続されている。The current control element 17 is connected between the drain electrode of the switching transistor 21 and the ground line 12, and emits light with a brightness corresponding to the current of the drive transistor 16. The parasitic capacitance 18 is a parasitic capacitance at both ends of the current control element 17. The decoupling capacitor 19 is connected between the drain electrode of the selection gate transistor 14A and the gate electrode of the drive transistor 16 and separates them from each other in terms of direct current. The switch transistor 20 includes a P-channel field effect transistor, a gate electrode thereof is connected to a reset line (not shown), a source electrode thereof is connected to a gate electrode of the driving transistor 16, and a drain electrode thereof is connected to a drain electrode of the driving transistor 16. Has been done. The switching transistor 21 is composed of a P-channel field effect transistor, has a gate electrode connected to the reset line, a source electrode connected to the drain electrode of the drive transistor 16, and a drain electrode connected to one end of the current control element 17.
【０００９】図１８は、第２の従来の電流制御素子の駆
動回路の動作を説明するタイミングチャートである。以
下、図１７，図１８を用いて、第２の従来例の電流制御
素子の駆動回路の動作を説明する。この従来例の電流制
御素子の駆動回路では、選択期間が始まる前に、電流制
御素子１７の寄生容量１８を放電し、駆動トランジスタ
１６のドレイン電圧ＶＤを接地線電位にしておく必要が
ある。また、信号線１３の電圧を電源線１１の電圧ＶＤ
Ｄにしておく。選択期間が開始されたとき、ロウ方向の
選択信号を選択線に与えることによって、選択ゲートト
ランジスタ１４Ａをオンにし、リセットドライバ（不図
示）からリセット信号をリセット線に与えることによっ
て、スイッチングトランジスタ２０をオンにし、スイッ
チングトランジスタ２１をオフにすると、駆動トランジ
スタ１６のゲート電極とドレイン電極とを電気的に接続
した状態で、保持容量１５に蓄積された電荷の放電が開
始される。この状態で、充分、時間が経過すると、駆動
トランジスタ１６のゲート電圧ＶＧがしきい値ＶＴまで
降下する。その後、スイッチングトランジスタ２０をオ
フにして、駆動トランジスタ１６のゲート電極をフロー
ティングにする。FIG. 18 is a timing chart for explaining the operation of the drive circuit for the second conventional current control element. The operation of the drive circuit for the current control element of the second conventional example will be described below with reference to FIGS. 17 and 18. In the drive circuit of the current control element of this conventional example, it is necessary to discharge the parasitic capacitance 18 of the current control element 17 and set the drain voltage VD of the drive transistor 16 to the ground line potential before the selection period starts. In addition, the voltage of the signal line 13 is set to the voltage VD of the power line 11.
Leave it as D. When the selection period is started, a selection signal in the row direction is applied to the selection line to turn on the selection gate transistor 14A, and a reset signal is applied from the reset driver (not shown) to the reset line to turn on the switching transistor 20. When the switching transistor 21 is turned on and the switching transistor 21 is turned off, discharge of the charge accumulated in the storage capacitor 15 is started in a state where the gate electrode and the drain electrode of the drive transistor 16 are electrically connected. In this state, when a sufficient time has passed, the gate voltage VG of the drive transistor 16 drops to the threshold value VT. After that, the switching transistor 20 is turned off and the gate electrode of the drive transistor 16 is floated.
【００１０】次に、信号線１３からの入力電圧が、電源
線１１の電圧ＶＤＤから書き込み電圧ＶＤＡＴＡに切り
替えられると、駆動トランジスタ１６のゲート−ドレイ
ン間電圧ＶＧＳは、デカップリング容量１９の容量値Ｃ
Ｄと、保持容量１５の容量値ＣＳとの容量分割によっ
て、下式で与えられるようになる。
ＶＧＳ＝ＶＧ−ＶＤＤ
＝ＶＴ＋ＣＤ・（ＶＤＡＴＡ−ＶＤＤ）／（ＣＳ＋ＣＤ） …（１）
トランジスタのドレイン−ソース間電流値は、一般に、
（ＶＧＳ−ＶＴ）の関数で表されるが、上式からわかる
ように、（ＶＧＳ−ＶＴ）がＶＤＡＴＡで決まるので、
駆動トランジスタ１６のしきい値にばらつきがあって
も、それが補正される。Next, when the input voltage from the signal line 13 is switched from the voltage VDD of the power supply line 11 to the write voltage VDATA, the gate-drain voltage VGS of the drive transistor 16 changes to the capacitance value C of the decoupling capacitance 19.
By the capacitance division of D and the capacitance value CS of the storage capacitor 15, it is given by the following equation. VGS = VG-VDD = VT + CD * (VDATA-VDD) / (CS + CD) (1) Generally, the drain-source current value of a transistor is
It is expressed by the function of (VGS-VT), but as can be seen from the above equation, (VGS-VT) is determined by VDATA, so
Even if the threshold value of the driving transistor 16 varies, it is corrected.
【００１１】しかしながら、この従来例では、１画素に
対して４個のトランジスタが必要になるだけでなく、保
持容量のほかに、デカップリング容量が必要になる。従
って、画素の開口率が低下して、製造プロセス的にも困
難になるという問題がある。また、デカッップリング容
量ＣＤの値が小さいと、書き込み電圧ＶＤＡＴＡをより
大きくしなければならないので、ＣＤ＞ＣＳにすること
が望ましいが、そのためには、デカッップリング容量Ｃ
Ｄを形成するためのチップ面積が大きくなるという問題
もある。さらに、選択期間前における電流制御素子の寄
生容量の放電に時間がかかり、寄生容量放電の操作が複
雑になるという欠点も持っている。However, in this conventional example, not only four transistors are required for one pixel, but also decoupling capacitance is required in addition to the storage capacitance. Therefore, there is a problem in that the aperture ratio of the pixel is lowered and it becomes difficult in the manufacturing process. Further, when the value of the decoupling capacitance CD is small, the write voltage VDATA must be made larger, so it is desirable that CD> CS, but for that purpose, the decoupling capacitance C
There is also a problem that the chip area for forming D becomes large. Furthermore, there is a drawback in that it takes time to discharge the parasitic capacitance of the current control element before the selection period, and the operation of discharging the parasitic capacitance becomes complicated.
【００１２】[0012]
【発明が解決しようとする課題】この発明は上述の事情
に鑑みてなされたものであって、最小限の素子構成で、
駆動トランジスタのしきい値ばらつきを補正することが
可能な、電流制御素子の駆動回路及び画像表示装置を提
供することを目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and has a minimum element configuration,
An object of the present invention is to provide a drive circuit for a current control element and an image display device capable of correcting the threshold variation of the drive transistor.
【００１３】[0013]
【課題を解決するための手段】上記課題を解決するた
め、請求項１記載の発明は電流制御素子の駆動回路に係
り、第１の電源線と第２の電源線との間に直列に接続さ
れた駆動トランジスタと電流制御素子と、上記駆動トラ
ンジスタと電流制御素子の接続点と上記駆動トランジス
タのゲート電極との間に接続された保持容量と、信号線
と上記駆動トランジスタのゲート電極との間に接続され
た選択ゲートトランジスタとを備え、上記駆動回路の選
択期間に、選択ゲートトランジスタをオンにして上記信
号線から第１の信号電圧を入力し、上記保持容量に書き
込まれた信号電荷を上記駆動トランジスタを経て放電し
たのち、上記信号線から第２の信号電圧を入力して上記
保持容量に保持し、上記駆動回路の非選択期間に、上記
選択ゲートトランジスタをオフにして上記駆動トランジ
スタを経て上記電流制御素子に電流を流すことを特徴と
している。In order to solve the above-mentioned problems, the invention according to claim 1 relates to a drive circuit for a current control element, which is connected in series between a first power supply line and a second power supply line. Between the drive transistor and the current control element, the storage capacitor connected between the connection point of the drive transistor and the current control element and the gate electrode of the drive transistor, and the signal line and the gate electrode of the drive transistor. And a selection gate transistor connected to the selection circuit, the selection gate transistor is turned on during the selection period of the drive circuit to input a first signal voltage from the signal line, and the signal charge written in the storage capacitor is supplied to the storage capacitor. After discharging through the drive transistor, the second signal voltage is input from the signal line and held in the storage capacitor, and the selection gate transistor is held in the non-selection period of the drive circuit. Clear the data through the driving transistor is characterized by supplying a current to said current control element.
【００１４】また、請求項２記載の発明は、請求項１記
載の電流制御素子の駆動回路に係り、上記駆動回路の選
択期間の初期に、上記信号線にリセット信号電圧を入力
することによって、上記保持容量及び上記電流制御素子
の寄生容量に蓄積されている電荷をリセットすることを
特徴としている。The invention according to claim 2 relates to the drive circuit for the current control element according to claim 1, wherein the reset signal voltage is input to the signal line at the beginning of the selection period of the drive circuit. It is characterized in that the electric charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset.
【００１５】また、請求項３記載の発明は、請求項１記
載の電流制御素子の駆動回路に係り、上記駆動回路の選
択期間の初期に、上記駆動トランジスタをオンにし、上
記第１の電源線をリセット信号電圧とすることによっ
て、上記保持容量及び上記電流制御素子の寄生容量に蓄
積されている電荷をリセットすることを特徴としてい
る。The invention according to claim 3 relates to the drive circuit for the current control element according to claim 1, wherein the drive transistor is turned on at the beginning of the selection period of the drive circuit, and the first power supply line is turned on. Is used as a reset signal voltage to reset the charges accumulated in the storage capacitor and the parasitic capacitance of the current control element.
【００１６】また、請求項４記載の発明は、請求項１乃
至３のいずれか一に記載の電流制御素子の駆動回路に係
り、上記選択ゲートトランジスタと駆動トランジスタと
が、Ｎチャネル電界効果トランジスタからなることを特
徴としている。The invention according to claim 4 relates to the drive circuit of the current control element according to any one of claims 1 to 3, wherein the select gate transistor and the drive transistor are N-channel field effect transistors. It is characterized by becoming.
【００１７】また、請求項５記載の発明は、請求項１乃
至３のいずれか一に記載の電流制御素子の駆動回路に係
り、上記選択ゲートトランジスタと駆動トランジスタと
が、Ｐチャネル電界効果トランジスタからなることを特
徴としている。The invention according to claim 5 relates to the drive circuit for the current control element according to any one of claims 1 to 3, wherein the select gate transistor and the drive transistor are P-channel field effect transistors. It is characterized by becoming.
【００１８】また、請求項６記載の発明は、請求項１記
載の電流制御素子の駆動回路に係り、上記駆動トランジ
スタのゲート電極とソース電極との間にスイッチングト
ランジスタを備え、上記駆動回路の非選択期間又は選択
期間の初期に、上記スイッチングトランジスタをオンに
することによって、上記保持容量及び上記電流制御素子
の寄生容量に蓄積されている電荷をリセットすることを
特徴としている。According to a sixth aspect of the present invention, there is provided a drive circuit for a current control element according to the first aspect, wherein a switching transistor is provided between a gate electrode and a source electrode of the drive transistor, and the drive circuit is not connected. It is characterized in that the charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor at the selection period or at the beginning of the selection period.
【００１９】また、請求項７記載の発明は、請求項１記
載の電流制御素子の駆動回路に係り、上記駆動トランジ
スタのゲート電極と上記他方の電源線との間にスイッチ
ングトランジスタを備え、上記駆動回路の非選択期間又
は選択期間の初期に、上記スイッチングトランジスタを
オンにすることによって、上記保持容量及び上記電流制
御素子の寄生容量に蓄積されている電荷をリセットする
ことを特徴としている。The invention according to claim 7 relates to the drive circuit of the current control element according to claim 1, further comprising a switching transistor between the gate electrode of the drive transistor and the other power supply line, The electric charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor at the beginning of the non-selection period or the selection period of the circuit.
【００２０】また、請求項８記載の発明は、請求項６又
は７記載の電流制御素子の駆動回路に係り、選択ゲート
トランジスタと駆動トランジスタとスイッチングトラン
ジスタとが、Ｎチャネル電界効果トランジスタからなる
ことを特徴としている。The invention according to claim 8 relates to the drive circuit for the current control element according to claim 6 or 7, wherein the select gate transistor, the drive transistor and the switching transistor are N-channel field effect transistors. It has a feature.
【００２１】また、請求項９記載の発明は、請求項６又
は７記載の電流制御素子の駆動回路に係り、上記選択ゲ
ートトランジスタと駆動トランジスタとスイッチングト
ランジスタとが、Ｐチャネル電界効果トランジスタから
なることを特徴としている。The present invention according to claim 9 relates to the drive circuit for the current control element according to claim 6 or 7, wherein the select gate transistor, the drive transistor and the switching transistor are P-channel field effect transistors. Is characterized by.
【００２２】また、請求項１０記載の発明は、画像表示
装置に係り、請求項１乃至９のいずれか一記載の電流制
御素子の駆動回路を複数個平面状に配列して、行方向と
列方向とに駆動可能なように構成してなることを特徴と
している。The invention according to claim 10 relates to an image display device, wherein a plurality of drive circuits for driving the current control element according to any one of claims 1 to 9 are arranged in a plane and arranged in rows and columns. It is characterized in that it can be driven in any direction.
【００２３】[0023]
【発明の実施の形態】以下、図面を参照して、この発明
の実施の形態について説明する。説明は、実施例を用い
て具体的に行う。
◇第１実施例
図１は、本発明の第１実施例である電流制御素子の駆動
回路の構成を示す回路図、図２は、本実施例の電流制御
素子の駆動回路の動作を説明するタイミングチャート、
図３は、本実施例における駆動トランジスタのＩＤＳ−
ＶＧＳ特性を示す図、図４は、本実施例における電流制
御素子のＩＬ−ＶＬ特性を示す図、図５は、駆動トラン
ジスタの特性がばらついているときのＩＤＳ−ＶＧＳ特
性を示す図、図６は、駆動トランジスタの特性がばらつ
いているときのＶＧＳの過渡特性を示す図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. First Embodiment FIG. 1 is a circuit diagram showing the configuration of a drive circuit for a current control element according to the first embodiment of the present invention, and FIG. 2 illustrates the operation of the drive circuit for a current control element according to the present embodiment. Timing chart,
FIG. 3 shows the IDS- of the drive transistor in this embodiment.
FIG. 4 is a graph showing VGS characteristics, FIG. 4 is a graph showing IL-VL characteristics of the current control element in the present embodiment, FIG. 5 is a graph showing IDS-VGS characteristics when the characteristics of the drive transistor are variable, and FIG. FIG. 6 is a diagram showing VGS transient characteristics when the characteristics of the drive transistor vary.
【００２４】この例の電流制御素子の駆動回路は、図１
に示すように、電源線１と接地線２と信号線３との間に
接続された、選択ゲートトランジスタ４と、保持容量５
と、駆動トランジスタ６と、電流制御素子７と、寄生容
量８とから概略構成されている。選択ゲートトランジス
タ４は、Ｎチャネル電界効果トランジスタからなり、ゲ
ート電極を選択線（不図示）に接続され、ドレイン電極
を信号線３に接続され、ソース電極を駆動トランジスタ
６のゲート電極に接続されている。保持容量５は、駆動
トランジスタ６のゲート電極とソース電極の間に接続さ
れてる。駆動トランジスタ６は、Ｎチャネル電界効果ト
ランジスタからなり、ゲート電極を選択ゲートトランジ
スタ４のソース電極と保持容量５の一端に接続され、ド
レイン電極を電源線１に接続され、ソース電極を電流制
御素子７のアノードに接続されている。電流制御素子７
は、駆動トランジスタ６のソース電極と接地線２との間
に接続され、駆動トランジスタ６の電流ＩＬに応じた輝
度で発光する。寄生容量８は、電流制御素子７の両端の
寄生容量である。The drive circuit of the current control element of this example is shown in FIG.
As shown in FIG. 3, the select gate transistor 4 and the storage capacitor 5 connected between the power line 1, the ground line 2 and the signal line 3 are connected.
, A drive transistor 6, a current control element 7, and a parasitic capacitance 8. The selection gate transistor 4 is composed of an N-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a drain electrode connected to the signal line 3, and a source electrode connected to the gate electrode of the drive transistor 6. There is. The storage capacitor 5 is connected between the gate electrode and the source electrode of the drive transistor 6. The drive transistor 6 is composed of an N-channel field effect transistor, and has a gate electrode connected to the source electrode of the selection gate transistor 4 and one end of the storage capacitor 5, a drain electrode connected to the power supply line 1, and a source electrode connected to the current control element 7. Connected to the anode of. Current control element 7
Is connected between the source electrode of the drive transistor 6 and the ground line 2, and emits light with a brightness corresponding to the current IL of the drive transistor 6. The parasitic capacitance 8 is a parasitic capacitance at both ends of the current control element 7.
【００２５】次に、図１〜図６を参照して、この例の電
流制御素子の駆動回路の動作を説明する。図２に示すよ
うに、駆動回路の選択期間が開始されると、選択ゲート
トランジスタ４が遮断状態から導通状態に切り替えられ
る。このとき、信号線３に入力される電圧ＶＤＡＴＡ
は、接地線２と同電位の０Ｖとする。この状態では、選
択ゲートトランジスタ４が導通状態であるため、保持容
量５の電荷は、信号線３を介して放電が開始される。同
時に、電流制御素子７の寄生容量８の電荷が、電流制御
素子７を経て放電される。選択期間が開始されてから充
分な時間が経過すると、駆動トランジスタ６のゲート電
圧ＶＧとソース電圧ＶＳがともに０Ｖとなる。駆動トラ
ンジスタ６のゲート−ソース間電圧ＶＧＳはゼロである
ため、駆動トランジスタ６のドレイン−ソース間には電
流が流れない。Next, the operation of the drive circuit of the current control element of this example will be described with reference to FIGS. As shown in FIG. 2, when the selection period of the drive circuit is started, the selection gate transistor 4 is switched from the cutoff state to the conduction state. At this time, the voltage VDATA input to the signal line 3
Is at 0 V, which is the same potential as the ground line 2. In this state, since the selection gate transistor 4 is in the conductive state, the electric charge of the storage capacitor 5 is started to be discharged through the signal line 3. At the same time, the electric charge of the parasitic capacitance 8 of the current control element 7 is discharged through the current control element 7. When a sufficient time has passed since the start of the selection period, both the gate voltage VG and the source voltage VS of the drive transistor 6 become 0V. Since the gate-source voltage VGS of the drive transistor 6 is zero, no current flows between the drain-source of the drive transistor 6.
【００２６】次に、信号線３の入力電圧が０ＶからＶＡ
に切り替えられる。信号線３が０ＶからＶＡに切り替え
られた直後には、駆動トランジスタ６のゲート−ソース
間電圧ＶＧＳは、保持容量５の容量値ＣＳと電流制御素
子７の寄生容量８の容量値ＣＬとから、次式のようにな
る。
ＶＧＳ＝ＶＡ×ＣＬ／（ＣＳ＋ＣＬ） …（２）
一方、駆動トランジスタ６のソース電圧ＶＳは、次式の
ようになる。
ＶＳ＝ＶＡ×ＣＳ／（ＣＳ＋ＣＬ） …（３）Next, the input voltage of the signal line 3 changes from 0V to VA.
Can be switched to. Immediately after the signal line 3 is switched from 0V to VA, the gate-source voltage VGS of the drive transistor 6 is calculated from the capacitance value CS of the storage capacitor 5 and the capacitance value CL of the parasitic capacitance 8 of the current control element 7. It becomes like the following formula. VGS = VA × CL / (CS + CL) (2) On the other hand, the source voltage VS of the drive transistor 6 is expressed by the following equation. VS = VA × CS / (CS + CL) (3)
【００２７】ただし、このとき、駆動トランジスタ６の
ゲート−ソース間電圧ＶＧＳは、図３に示す駆動トラン
ジスタのＩＤＳ−ＶＧＳ特性において、しきい値電圧Ｖ
Ｔよりも大きいことが必要である。また、電流制御素子
７の端子間電圧ＶＬ、すなわち、駆動トランジスタ６の
ソース電圧ＶＳは、図４に示す電流制御素子７の電圧−
電流特性において、順方向の立ち上がり電圧ＶＯＦＦよ
りも小さいことが必要である。すなわち、
ＶＧＳ＞ＶＴ …（４）
ＶＳ＜ＶＯＦＦ …（５）At this time, however, the gate-source voltage VGS of the driving transistor 6 is the threshold voltage VGS in the IDS-VGS characteristics of the driving transistor shown in FIG.
It must be greater than T. Further, the voltage VL between the terminals of the current control element 7, that is, the source voltage VS of the drive transistor 6 is the voltage − of the current control element 7 shown in FIG.
In the current characteristic, it is necessary that it is smaller than the forward rising voltage VOFF. That is, VGS> VT (4) VS <VOFF (5)
【００２８】駆動トランジスタ６のゲート−ソース間電
圧ＶＧＳは、しきい値電圧ＶＴよりも大きいため、駆動
トランジスタ６のドレイン−ソース間に電流が流れる。
この駆動トランジスタ６のドレイン−ソース間電流によ
って、電流制御素子７の寄生容量８に電荷が充電され
て、電流制御素子７の端子間電圧ＶＬ、すなわち駆動ト
ランジスタ６のソース電圧ＶＳが上昇する。同時に、駆
動トランジスタ６のゲート電圧ＶＧが一定値ＶＡである
ため、駆動トランジスタ６のゲート−ソース間電圧ＶＧ
Ｓは、減少しながらしきい値電圧ＶＴに近づき、駆動ト
ランジスタ６のソース電圧ＶＳは、（ＶＡ−ＶＴ）に近
づく。Since the gate-source voltage VGS of the drive transistor 6 is higher than the threshold voltage VT, a current flows between the drain-source of the drive transistor 6.
The drain-source current of the drive transistor 6 charges the parasitic capacitance 8 of the current control element 7 to increase the terminal voltage VL of the current control element 7, that is, the source voltage VS of the drive transistor 6. At the same time, since the gate voltage VG of the drive transistor 6 is a constant value VA, the gate-source voltage VG of the drive transistor 6 is
S approaches the threshold voltage VT while decreasing, and the source voltage VS of the drive transistor 6 approaches (VA-VT).
【００２９】この際、駆動トランジスタ６は、ガラス基
板上に形成された薄膜トランジスタ等であるため、図５
に示すように、ドレイン−ソース間電流ＩＤＳと、ゲー
ト−ソース間電圧ＶＧＳとの関係を示すＩＤＳ−ＶＧＳ
特性は、同じドレイン−ソース間電流ＩＤＳに対して、
個々のトランジスタ６ａ，６ｂ及び６ｃの特性に応じ
て、ＶＧＳがＶＴａ，ＶＴｂ及びＶＴｃで示されるよう
に大きくばらつく。そこで図６に示すように、駆動トラ
ンジスタ６ａ，６ｂ及び６ｃのゲート−ソース間電圧Ｖ
ＧＳは、充分な時間が経過すると、信号電圧ＶＡの入力
直後の値ＶＡ×ＣＬ／（ＣＳ＋ＣＬ）から、個々のトラ
ンジスタのしきい値ＶＴａ，ＶＴｂ及びＶＴｃとなり、
それまでの時間も、Ｔａ，Ｔｂ及びＴｃのように異なっ
ている。At this time, since the drive transistor 6 is a thin film transistor or the like formed on the glass substrate, the drive transistor 6 shown in FIG.
As shown in, the IDS-VGS indicating the relationship between the drain-source current IDS and the gate-source voltage VGS.
The characteristics are that for the same drain-source current IDS,
Depending on the characteristics of the individual transistors 6a, 6b and 6c, VGS greatly varies as shown by VTa, VTb and VTc. Therefore, as shown in FIG. 6, the gate-source voltage V of the drive transistors 6a, 6b and 6c is
After a sufficient time has elapsed, GS becomes the threshold values VTa, VTb, and VTc of the individual transistors from the value VA × CL / (CS + CL) immediately after the signal voltage VA is input,
The time until then is also different like Ta, Tb and Tc.
【００３０】そして、充分な時間が経過したとき、駆動
トランジスタ６のドレイン−ソース間には電流が流れな
いようになり、駆動トランジスタ６のゲート−ソース間
電圧ＶＧＳはしきい値電圧ＶＴとなる。
ＶＧＳ＝ＶＴ …（６）
一方、駆動トランジスタ６のソース電圧ＶＳは、次式の
ようになる。
ＶＳ＝ＶＡ−ＶＴ …（７）
ただし、このとき、駆動トランジスタ６のソース電圧Ｖ
Ｓは、図４に示された電流制御素子７のＩＬ−ＶＬ特性
において、電流制御素子７の順方向立ち上がり電圧ＶＯ
ＦＦよりも小さくなるように、容量値ＣＳ，ＣＬを選定
することが必要である。
ＶＳ＜ＶＯＦＦ …（８）When a sufficient time has passed, no current flows between the drain and source of the drive transistor 6, and the gate-source voltage VGS of the drive transistor 6 becomes the threshold voltage VT. VGS = VT (6) On the other hand, the source voltage VS of the drive transistor 6 is expressed by the following equation. VS = VA-VT (7) However, at this time, the source voltage V of the drive transistor 6
S is the forward rising voltage VO of the current control element 7 in the IL-VL characteristic of the current control element 7 shown in FIG.
It is necessary to select the capacitance values CS and CL so as to be smaller than FF. VS <VOFF (8)
【００３１】次に、信号線３に入力する電圧ＶＤＡＴＡ
がＶＡからＶＢに切り替えられる。ここで、ＶＢはＶＡ
と同じ値（非発光状態）、又はＶＡより大きい値（発光
状態）である。ＶＡからＶＢに切り替えたときの電圧差
（ＶＢ−ＶＡ）は、駆動トランジスタ６のゲート−ソー
ス間保持容量５の容量値ＣＳと、電流制御素子７の寄生
容量８の容量値ＣＬとに容量分割して印加される。従っ
て、このときの駆動トランジスタ６のゲート−ソース間
電圧ＶＧＳと、駆動トランジスタ６のソース電圧ＶＳと
は、それぞれ次式のようになる。
ＶＧＳ＝ＶＴ＋（１−ＣＳ／ＣＬ）・（ＶＢ−ＶＡ） …（９）
ＶＳ＝ＶＡ−ＶＴ＋（ＶＢ−ＶＡ）ＣＳ／ＣＬ …（10) Next, the voltage VDATA input to the signal line 3
Is switched from VA to VB. Where VB is VA
Value (non-light emitting state) or a value larger than VA (light emitting state). The voltage difference (VB-VA) when switching from VA to VB is divided into the capacitance value CS of the gate-source holding capacitance 5 of the drive transistor 6 and the capacitance value CL of the parasitic capacitance 8 of the current control element 7. And then applied. Therefore, the gate-source voltage VGS of the drive transistor 6 and the source voltage VS of the drive transistor 6 at this time are respectively expressed by the following equations. VGS = VT + (1-CS / CL). (VB-VA) (9) VS = VA-VT + (VB-VA) CS / CL (10)
【００３２】上式からわかるように、（ＶＧＳ−ＶＴ）
が（ＶＢ−ＶＡ）で決まるので、駆動トランジスタ６の
しきい値にばらつきがあっても、このばらつきが補正さ
れるので、ＶＢとＶＡを適正な値に設定することによっ
て、電流制御素子７に流れる電流値が制御される。As can be seen from the above equation, (VGS-VT)
Is determined by (VB-VA), even if there is a variation in the threshold value of the drive transistor 6, this variation is corrected. Therefore, by setting VB and VA to appropriate values, the current control element 7 can be set. The flowing current value is controlled.
【００３３】次に、選択ゲートトランジスタ４を導通状
態から遮断状態に切り替えることによって、非選択期間
に入る。非選択期間に入ると、駆動トランジスタ６のゲ
ート−ソース間電圧ＶＧＳは、保持容量５によって保持
されるようになる。駆動トランジスタ６のソース電圧Ｖ
Ｓは、駆動トランジスタ６を介して電流制御素子７の寄
生容量８に電荷が充電されるのに応じて上昇し、駆動ト
ランジスタ６のゲート電圧ＶＧも、保持容量５を介して
ゲート−ソース間電圧ＶＧＳを一定に維持したまま、同
時に上昇する。電流制御素子７は、駆動トランジスタ６
のソース電圧ＶＳが、電流制御素子７の順方向の立ち上
がり電圧ＶＯＦＦを超えたとき発光を開始し、以後、非
選択期間が終了するまで、発光し続ける。電流制御素子
７の端子間電圧ＶＬが、駆動トランジスタ６のゲート−
ソース間電圧ＶＧＳによって定まる電流ＩＬを流すのに
充分な電圧に到達すると、駆動トランジスタ６のゲート
電圧ＶＧとソース電圧ＶＳの上昇は停止して一定とな
る。その後は、駆動トランジスタ６のゲート−ソース間
電圧ＶＧＳが保持容量５によって保持されるため、電流
制御素子７に一定電流ＩＬが流れ続ける。Next, the non-selection period is started by switching the selection gate transistor 4 from the conductive state to the cutoff state. In the non-selection period, the gate-source voltage VGS of the drive transistor 6 comes to be held by the holding capacitor 5. Source voltage V of drive transistor 6
S rises in response to the charging of the parasitic capacitance 8 of the current control element 7 via the driving transistor 6, and the gate voltage VG of the driving transistor 6 also passes through the holding capacitor 5 and the gate-source voltage. While maintaining VGS constant, it rises at the same time. The current control element 7 is the drive transistor 6
When the source voltage VS of the current control element 7 exceeds the forward-direction rising voltage VOFF of the current control element 7, light emission starts, and thereafter, light emission continues until the non-selection period ends. The voltage VL between the terminals of the current control element 7 is
When a voltage sufficient to flow the current IL determined by the source-to-source voltage VGS is reached, the rise of the gate voltage VG and the source voltage VS of the drive transistor 6 stops and becomes constant. After that, since the gate-source voltage VGS of the drive transistor 6 is held by the holding capacitor 5, the constant current IL continues to flow in the current control element 7.
【００３４】このように、この例の電流制御素子の駆動
回路では、選択ゲートトランジスタ４と駆動トランジス
タ６との２個のトランジスタと、保持容量５とからなる
最小限の素子構成で、駆動トランジスタ６のしきい値を
補正して、その変化の影響を受けないようにすることが
できる。本実施例によれば、従来例の電流制御素子の駆
動回路と比較して、画素回路を構成する素子数が１／２
となるので、画素の開口率を大きくできるとともに、製
造プロセスが容易になる。また、一般に、電流制御素子
７の寄生容量８の容量値ＣＬは、保持容量５の容量値Ｃ
Ｓより大きいので、より小さな書き込み電圧で、駆動回
路の書き込みを行うことができ、消費電力の点からも有
利である。As described above, in the drive circuit for the current control element of this example, the drive transistor 6 has the minimum element configuration including the two transistors of the selection gate transistor 4 and the drive transistor 6 and the storage capacitor 5. Can be corrected so that it is not affected by the change. According to the present embodiment, the number of elements forming the pixel circuit is 1/2 as compared with the drive circuit of the current control element of the conventional example.
Therefore, the aperture ratio of the pixel can be increased and the manufacturing process is facilitated. Further, generally, the capacitance value CL of the parasitic capacitance 8 of the current control element 7 is the capacitance value C of the storage capacitor 5.
Since it is larger than S, the drive circuit can be written with a smaller write voltage, which is also advantageous in terms of power consumption.
【００３５】図１に示された第１実施例の駆動回路で
は、制御方法を変えることによって、異なる動作を行わ
せることができる。以下においては、この場合の実施例
について説明する。In the drive circuit of the first embodiment shown in FIG. 1, different operations can be performed by changing the control method. An example in this case will be described below.
【００３６】◇第２実施例
図７は、本発明の第２実施例である電流制御素子の駆動
回路の動作を説明するタイミングチャートである。この
例の電流制御素子の駆動回路の構成は、図１に示された
第１実施例の場合と同様であるが、制御方法が異なって
いるため、その動作も異なっている。Second Embodiment FIG. 7 is a timing chart for explaining the operation of the drive circuit for the current control element according to the second embodiment of the present invention. The configuration of the drive circuit of the current control element of this example is the same as that of the first embodiment shown in FIG. 1, but the operation is different because the control method is different.
【００３７】以下、図７を参照して、この例の電流制御
素子の駆動回路の動作を説明する。駆動回路の選択期間
が開始されると、選択ゲートトランジスタ４が遮断状態
から導通状態に切り替えられる。このとき、信号線３に
入力される電圧は、駆動トランジスタ６がオンするのに
充分な大きさの電圧とする。また、これと同時に、電源
線１の電位を０Ｖとする。駆動トランジスタ６がオンし
ているため、電流制御素子７の寄生容量８の電荷が、駆
動トランジスタ６を介して放電される。駆動トランジス
タ６のソース電圧ＶＳがゼロになってから、信号線３の
電圧を接地電位０Ｖにする。選択ゲートトランジスタ４
が導通状態になっているため、保持容量５の電荷が放電
されて、駆動トランジスタ６のゲート電圧ＶＧが０Ｖに
なる。The operation of the drive circuit for the current control element of this example will be described below with reference to FIG. When the selection period of the drive circuit is started, the selection gate transistor 4 is switched from the cutoff state to the conduction state. At this time, the voltage input to the signal line 3 is set to a voltage large enough to turn on the drive transistor 6. At the same time, the potential of the power supply line 1 is set to 0V. Since the drive transistor 6 is turned on, the electric charge of the parasitic capacitance 8 of the current control element 7 is discharged through the drive transistor 6. After the source voltage VS of the drive transistor 6 becomes zero, the voltage of the signal line 3 is set to the ground potential 0V. Select gate transistor 4
Are in a conductive state, the electric charge of the storage capacitor 5 is discharged, and the gate voltage VG of the drive transistor 6 becomes 0V.
【００３８】このあと、電源線１の電圧をもとの電源線
電圧レベルに戻す。駆動トランジスタ６のゲート−ソー
ス間電圧ＶＧＳはゼロであるため、駆動トランジスタ６
のドレイン−ソース間に電流は流れない。次に、信号線
３の入力電圧を０ＶからＶＡに切り替える。以降の動作
は、第１実施例の場合と同様に行われる。After that, the voltage of the power supply line 1 is returned to the original power supply line voltage level. Since the gate-source voltage VGS of the driving transistor 6 is zero, the driving transistor 6
No current flows between the drain and source of the. Next, the input voltage of the signal line 3 is switched from 0V to VA. Subsequent operations are performed in the same manner as in the first embodiment.
【００３９】このように、この例の電流制御素子の駆動
回路では、第１実施例の場合と同様に、選択ゲートトラ
ンジスタ４と駆動トランジスタ６との２個のトランジス
タと、保持容量５とからなる最小限の素子構成で、駆動
トランジスタ６のしきい値を補正して、その変化の影響
を受けないようにすることができるとともに、選択期間
の初期に駆動トランジスタをオンにし、電源線１の電位
を０Ｖにするので、電流制御素子７の寄生容量８の電荷
を駆動トランジスタ６を経て電源線１に放電することが
でき、従って、駆動トランジスタ６のソース電圧の降下
が速いので、選択期間を短縮することが可能になる。As described above, in the current control element drive circuit of this example, as in the case of the first embodiment, the two transistors of the selection gate transistor 4 and the drive transistor 6 and the storage capacitor 5 are provided. The threshold of the drive transistor 6 can be corrected with a minimum element configuration so that it is not affected by the change, and the drive transistor is turned on at the beginning of the selection period to reduce the potential of the power supply line 1. Is set to 0V, the electric charge of the parasitic capacitance 8 of the current control element 7 can be discharged to the power supply line 1 through the driving transistor 6, and therefore the source voltage of the driving transistor 6 drops quickly, so that the selection period is shortened. It becomes possible to do.
【００４０】◇第３実施例
図８は、本発明の第３実施例である電流制御素子の駆動
回路の構成を示す回路図、図９は、本実施例の電流制御
素子の駆動回路の動作を説明するタイミングチャートで
ある。この例の電流制御素子の駆動回路は、図８に示す
ように、電源線１と接地線２と信号線３との間に接続さ
れた、選択ゲートトランジスタ４と、保持容量５と、駆
動トランジスタ６と、電流制御素子７と、寄生容量８
と、スイッチングトランジスタ９とから概略構成されて
いる。Third Embodiment FIG. 8 is a circuit diagram showing the configuration of a drive circuit for a current control element according to a third embodiment of the present invention, and FIG. 9 is an operation of the drive circuit for a current control element according to the present embodiment. 3 is a timing chart for explaining the above. As shown in FIG. 8, the drive circuit of the current control element of this example includes a select gate transistor 4, a storage capacitor 5, and a drive transistor connected between a power line 1, a ground line 2 and a signal line 3. 6, current control element 7, and parasitic capacitance 8
And a switching transistor 9.
【００４１】この例の電流制御素子の駆動回路において
は、電源線１，接地線２，信号線３，選択ゲートトラン
ジスタ４，保持容量５，駆動トランジスタ６，電流制御
素子７及び寄生容量８の構成は、図１に示された第１実
施例の場合と同様であるが、これらに加えて、図８に示
すスイッチングトランジスタ９を有する点が、第１実施
例の場合と異なっている。スイッチングトランジスタ９
は、Ｎチャネル電界効果トランジスタからなり、ゲート
電極を選択線に接続され、ドレイン電極を駆動トランジ
スタ６のソース電極及び保持容量５の一端に接続され、
ソース電極を接地線２に接続されている。In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4, the storage capacitor 5, the drive transistor 6, the current control device 7, and the parasitic capacitance 8 are configured. Is similar to the case of the first embodiment shown in FIG. 1, but is different from the case of the first embodiment in that a switching transistor 9 shown in FIG. 8 is additionally provided. Switching transistor 9
Is an N-channel field effect transistor, the gate electrode is connected to the select line, the drain electrode is connected to the source electrode of the drive transistor 6 and one end of the storage capacitor 5,
The source electrode is connected to the ground line 2.
【００４２】以下、図８，図９を参照して、この例の電
流制御素子の駆動回路の動作を説明する。駆動回路の選
択期間が開始されると、選択線からの制御によって、選
択ゲートトランジスタ４とスイッチングトランジスタ９
が、遮断状態から導通状態に切り替えられる。このと
き、信号線３に入力される電圧は、接地線２と同じ０Ｖ
とする。選択ゲートトランジスタ４とスイッチングトラ
ンジスタ９が導通状態になったことによって、保持容量
５の電荷と、電流制御素子７の寄生容量８の電荷とが放
電されるので、駆動トランジスタ６のゲート電圧ＶＧと
ソース電圧ＶＳが０Ｖとなる。このとき、駆動トランジ
スタ６のゲート−ソース間電圧ＶＧＳは０Ｖなので、駆
動トランジスタ６のドレイン−ソース間には電流が流れ
ない。次に、選択線からの制御によって、スイッチング
トランジスタ９が遮断状態とされるとともに、信号線３
の入力電圧が、０ＶからＶＡに切り替えられる。これ以
降の動作は、第１実施例の場合と同様である。The operation of the drive circuit for the current control element of this example will be described below with reference to FIGS. When the selection period of the drive circuit is started, the selection gate transistor 4 and the switching transistor 9 are controlled by the selection line.
Is switched from the cutoff state to the conduction state. At this time, the voltage input to the signal line 3 is 0 V which is the same as that of the ground line 2.
And Since the selection gate transistor 4 and the switching transistor 9 are brought into conduction, the electric charge of the storage capacitor 5 and the electric charge of the parasitic capacitance 8 of the current control element 7 are discharged, so that the gate voltage VG and the source of the drive transistor 6 The voltage VS becomes 0V. At this time, since the gate-source voltage VGS of the drive transistor 6 is 0 V, no current flows between the drain-source of the drive transistor 6. Next, the switching transistor 9 is turned off by the control from the select line, and the signal line 3
Input voltage is switched from 0V to VA. The subsequent operation is similar to that of the first embodiment.
【００４３】このように、この例の電流制御素子の駆動
回路によれば、第１実施例の場合と同様に駆動トランジ
スタ６のしきい値を補正して、その変化の影響を受けな
いようにすることができる。この際、第１実施例の場合
と比較して、スイッチングトランジスタ９が余分に必要
となるが、スイッチングトランジスタ９による保持容量
５及び電流制御素子７の寄生容量８のリセットを、選択
ゲートトランジスタ４による保持容量５の書き込みと独
立に行うことができるので、リセットの時期を選択する
ことによって、保持容量５及び寄生容量８のリセットを
より確実に行うことができるようになる。As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6 is corrected in the same manner as in the first embodiment so that it is not affected by the change. can do. At this time, the switching transistor 9 is additionally required as compared with the case of the first embodiment, but the resetting of the storage capacitor 5 and the parasitic capacitance 8 of the current control element 7 by the switching transistor 9 is performed by the selection gate transistor 4. Since the writing can be performed independently of the storage capacitor 5, the storage capacitor 5 and the parasitic capacitance 8 can be reset more reliably by selecting the reset time.
【００４４】◇第４実施例
図１０は、本発明の第４実施例である電流制御素子の駆
動回路の構成を示す回路図、図１１は、本実施例の電流
制御素子の駆動回路の動作を説明するタイミングチャー
トである。この例の電流制御素子の駆動回路は、図１０
に示すように、電源線１と接地線２と信号線３との間に
接続された、選択ゲートトランジスタ４と、保持容量５
と、駆動トランジスタ６と、電流制御素子７と、寄生容
量８と、スイッチングトランジスタ１０とから概略構成
されている。Fourth Embodiment FIG. 10 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the fourth embodiment of the present invention, and FIG. 11 is the operation of the drive circuit for the current control element according to the present embodiment. 3 is a timing chart for explaining the above. The drive circuit of the current control element of this example is shown in FIG.
As shown in FIG. 3, the select gate transistor 4 and the storage capacitor 5 connected between the power line 1, the ground line 2 and the signal line 3 are connected.
, A drive transistor 6, a current control element 7, a parasitic capacitance 8, and a switching transistor 10.
【００４５】この例の電流制御素子の駆動回路において
は、電源線１，接地線２，信号線３，選択ゲートトラン
ジスタ４，保持容量５，駆動トランジスタ６，電流制御
素子７及び寄生容量８の構成は、図１に示された第１実
施例の場合と同様であるが、これらに加えて、図１０に
示すスイッチングトランジスタ１０を有する点が、第１
実施例の場合と異なっている。スイッチングトランジス
タ１０は、Ｎチャネル電界効果トランジスタからなり、
ゲート電極を選択線に接続され、ドレイン電極を駆動ト
ランジスタ６のゲート電極及び保持容量５の一端に接続
され、ソース電極を接地線２に接続されている。In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4, the storage capacitor 5, the drive transistor 6, the current control device 7, and the parasitic capacitance 8 are configured. Is similar to the case of the first embodiment shown in FIG. 1, except that the first embodiment has a switching transistor 10 shown in FIG.
This is different from the case of the embodiment. The switching transistor 10 is composed of an N-channel field effect transistor,
The gate electrode is connected to the selection line, the drain electrode is connected to the gate electrode of the drive transistor 6 and one end of the storage capacitor 5, and the source electrode is connected to the ground line 2.
【００４６】以下、図１０，図１１を参照して、この例
の電流制御素子の駆動回路の動作を説明する。駆動回路
の選択期間が開始される前の一定期間、選択線からの制
御によって、スイッチングトランジスタ１０を導通状態
にする。スイッチングトランジスタ１０が導通状態なの
で、駆動トランジスタ６のゲート電圧ＶＧはゼロとな
り、これによって、駆動トランジスタ６のゲート−ソー
ス間電圧ＶＧＳは負の電圧となるため、駆動トランジス
タ６は遮断状態となる。このとき、電流制御素子７の寄
生容量８に蓄積されている電荷は、電流制御素子７を介
して接地線２に放電される。スイッチングトランジスタ
１０が導通状態になってから、充分長い時間が経過する
と、電流制御素子７の寄生容量８に蓄積されていた電荷
はすべて放電されて、駆動トランジスタ６のソース電圧
ＶＳは０Ｖとなる。この期間中、選択ゲートトランジス
タ４は、選択線からの制御によって、遮断状態とされて
いる。The operation of the drive circuit for the current control element of this example will be described below with reference to FIGS. The switching transistor 10 is made conductive by the control from the selection line for a certain period before the selection period of the drive circuit is started. Since the switching transistor 10 is in the conductive state, the gate voltage VG of the drive transistor 6 becomes zero, and the gate-source voltage VGS of the drive transistor 6 becomes a negative voltage, so that the drive transistor 6 is cut off. At this time, the electric charge accumulated in the parasitic capacitance 8 of the current control element 7 is discharged to the ground line 2 via the current control element 7. When a sufficiently long time has passed since the switching transistor 10 was turned on, all the charges accumulated in the parasitic capacitance 8 of the current control element 7 are discharged, and the source voltage VS of the drive transistor 6 becomes 0V. During this period, the selection gate transistor 4 is in the cutoff state by the control from the selection line.
【００４７】次に、駆動回路の選択期間が開始される
と、選択線からの制御によって、スイッチングトランジ
スタ１０が、導通状態から遮断状態に切り替えられる。
次に、選択ゲートトランジスタ４が、選択線からの制御
によって、遮断状態から導通状態に切り替えられる。こ
のとき、信号線３の入力電圧ＶＤＡＴＡとして、ＶＡが
入力されている。これ以降の動作は、第１実施例の場合
と同様である。Next, when the selection period of the drive circuit is started, the switching transistor 10 is switched from the conductive state to the cutoff state by the control from the selection line.
Next, the selection gate transistor 4 is switched from the cutoff state to the conduction state by the control from the selection line. At this time, VA is input as the input voltage VDATA of the signal line 3. The subsequent operation is similar to that of the first embodiment.
【００４８】このように、この例の電流制御素子の駆動
回路によれば、第１実施例の場合と同様に駆動トランジ
スタ６のしきい値を補正して、その変化の影響を受けな
いようにすることができる。この際、第１実施例の場合
と比較して、スイッチングトランジスタ１０が余分に必
要となるが、スイッチングトランジスタ１０による保持
容量５及び電流制御素子７の寄生容量８のリセットを、
選択ゲートトランジスタ４による保持容量５の書き込み
と独立に行うことができるので、リセットの時期を選択
することによって、保持容量５及び寄生容量８のリセッ
トをより確実に行うことができるようになる。As described above, according to the drive circuit of the current control element of this example, the threshold value of the drive transistor 6 is corrected in the same manner as in the first embodiment so that it is not affected by the change. can do. At this time, although the switching transistor 10 is additionally required as compared with the case of the first embodiment, the resetting of the holding capacitance 5 and the parasitic capacitance 8 of the current control element 7 by the switching transistor 10
Since it can be performed independently of the writing of the storage capacitor 5 by the selection gate transistor 4, the storage capacitor 5 and the parasitic capacitance 8 can be reset more reliably by selecting the reset time.
【００４９】以上の各実施例においては，電流制御素子
の駆動回路をすべてＮチャネル電界効果トランジスタに
よって構成したが、駆動回路をＰチャネル電界効果トラ
ンジスタによって構成することも可能である。以下にお
いては、この場合の実施例について説明する。In each of the above embodiments, the drive circuit for the current control element is entirely composed of N-channel field effect transistors, but the drive circuit may be composed of P-channel field effect transistors. An example in this case will be described below.
【００５０】◇第５実施例
図１２は、本発明の第５実施例である電流制御素子の駆
動回路の構成を示す回路図である。この例の電流制御素
子の駆動回路は、図１２に示すように、電源線１と接地
線２と信号線３との間に接続された、選択ゲートトラン
ジスタ４Ａと、保持容量５Ａと、駆動トランジスタ６Ａ
と、電流制御素子７Ａと、寄生容量８Ａとから概略構成
されている。選択ゲートトランジスタ４Ａは、Ｐチャネ
ル電界効果トランジスタからなり、ゲート電極を選択線
（不図示）に接続され、ソース電極を信号線３に接続さ
れ、ドレイン電極を駆動トランジスタ６Ａのゲート電極
に接続されている。保持容量５Ａは、駆動トランジスタ
６Ａのゲート電極とソース電極の間に接続されてる。駆
動トランジスタ６Ａは、Ｐチャネル電界効果トランジス
タからなり、ゲート電極を選択ゲートトランジスタ４の
ドレイン電極と保持容量５Ａの一端に接続され、ソース
電極を電流制御素子７Ａのカソードに接続され、ドレイ
ン電極を接地線２に接続されている。電流制御素子７Ａ
は、電源線１と、駆動トランジスタ６Ａのソース電極の
間に接続され、駆動トランジスタ６Ａの電流ＩＬに応じ
た輝度で発光する。寄生容量８Ａは、電流制御素子７Ａ
の両端の寄生容量である。Fifth Embodiment FIG. 12 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the fifth embodiment of the present invention. As shown in FIG. 12, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
And a current control element 7A and a parasitic capacitance 8A. The selection gate transistor 4A is composed of a P-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a source electrode connected to the signal line 3, and a drain electrode connected to the gate electrode of the drive transistor 6A. There is. The storage capacitor 5A is connected between the gate electrode and the source electrode of the drive transistor 6A. The drive transistor 6A is composed of a P-channel field effect transistor, the gate electrode is connected to the drain electrode of the selection gate transistor 4 and one end of the storage capacitor 5A, the source electrode is connected to the cathode of the current control element 7A, and the drain electrode is grounded. Connected to line 2. Current control element 7A
Is connected between the power supply line 1 and the source electrode of the drive transistor 6A, and emits light with a brightness corresponding to the current IL of the drive transistor 6A. The parasitic capacitance 8A is the current control element 7A.
It is the parasitic capacitance at both ends of.
【００５１】この例の電流制御素子の駆動回路は、図１
に示された第１実施例の場合のＮチャネル電界効果トラ
ンジスタからなる選択ゲートトランジスタ４及び駆動ト
ランジスタ６を、Ｐチャネル電界効果トランジスタから
なる選択ゲートトランジスタ４Ａ及び駆動トランジスタ
６ＡにＰチャネル電界効果トランジスタによって置き替
えたものであって、従って、図１に示された第１実施例
の場合と比べて、電圧の関係が逆になるので、電流の向
きが逆になるが、その動作は、第１実施例の場合と同様
であって、図２に示されたタイミングチャートを適用す
ることができるので、以下においては、詳細な説明を省
略する。The drive circuit of the current control element of this example is shown in FIG.
The selection gate transistor 4 and the driving transistor 6 which are the N-channel field effect transistors in the case of the first embodiment shown in FIG. This is a replacement, and therefore, compared with the case of the first embodiment shown in FIG. 1, since the relationship of the voltage is reversed, the direction of the current is reversed, but the operation is the same as that of the first embodiment. Since the timing chart shown in FIG. 2 can be applied in the same manner as in the case of the embodiment, detailed description will be omitted below.
【００５２】このように、この例の電流制御素子の駆動
回路では、選択ゲートトランジスタ４Ａと駆動トランジ
スタ６Ａとの２個のトランジスタと、保持容量５Ａとか
らなる最小限の素子構成で、駆動トランジスタ６Ａのし
きい値を補正して、その変化の影響を受けないようにす
ることができる。本実施例によれば、第１実施例の場合
と同様に、従来例の電流制御素子の駆動回路と比較し
て、画素回路を構成する素子数を逓減して、画素の開口
率を大きくできるとともに、製造プロセスが容易にな
り、さらに、消費電力が少ない利点がある。As described above, in the drive circuit of the current control element of this example, the drive transistor 6A has the minimum element configuration including the two transistors of the selection gate transistor 4A and the drive transistor 6A and the storage capacitor 5A. Can be corrected so that it is not affected by the change. According to the present embodiment, as in the case of the first embodiment, the number of elements forming the pixel circuit can be gradually reduced and the aperture ratio of the pixel can be increased as compared with the conventional current control element drive circuit. At the same time, there is an advantage that the manufacturing process becomes easy and the power consumption is small.
【００５３】◇第６実施例
この例の電流制御素子の駆動回路の構成は、図１２に示
された第５実施例の場合と同様であるが、制御方法が異
なっているため、その動作も異なっている。この例の電
流制御素子の駆動回路は、第２実施例の場合のＮチャネ
ル電界効果トランジスタからなる選択ゲートトランジス
タ４及び駆動トランジスタ６を、Ｐチャネル電界効果ト
ランジスタからなる選択ゲートトランジスタ４Ａ及び駆
動トランジスタ６Ａによって置き替えたものであって、
従って、第２実施例の場合と比べて、電圧の関係が逆に
なるので、電流の向きが逆になるが、その動作は、第２
実施例の場合と同様であって、図７に示されたタイミン
グチャートを適用することができるので、以下において
は、詳細な説明を省略する。Sixth Embodiment The configuration of the drive circuit for the current control element of this example is the same as that of the fifth embodiment shown in FIG. 12, but the operation is also different because the control method is different. Is different. The drive circuit of the current control element of this example includes the select gate transistor 4 and the drive transistor 6 which are N-channel field effect transistors in the case of the second embodiment, and the select gate transistor 4A and the drive transistor 6A which are P-channel field effect transistors. Replaced by
Therefore, as compared with the case of the second embodiment, the relationship of the voltage is reversed and the direction of the current is reversed, but the operation is the same as that of the second embodiment.
The timing chart shown in FIG. 7 can be applied as in the case of the embodiment, and therefore detailed description thereof will be omitted below.
【００５４】このように、この例の電流制御素子の駆動
回路では、第５実施例の場合と同様に、選択ゲートトラ
ンジスタ４Ａと駆動トランジスタ６Ａとの２個のトラン
ジスタと、保持容量５Ａとからなる最小限の素子構成
で、駆動トランジスタ６Ａのしきい値を補正して、その
変化の影響を受けないようにすることができるととも
に、駆動トランジスタ６Ａのソース電圧の降下が速いの
で、選択期間を短縮することができる。As described above, in the drive circuit for the current control element of this example, as in the case of the fifth embodiment, the two transistors of the selection gate transistor 4A and the drive transistor 6A and the storage capacitor 5A are included. The threshold of the drive transistor 6A can be corrected with the minimum element configuration so that it is not affected by the change, and the source voltage of the drive transistor 6A drops quickly, so that the selection period is shortened. can do.
【００５５】◇第７実施例
図１３は、本発明の第７実施例である電流制御素子の駆
動回路の構成を示す回路図である。この例の電流制御素
子の駆動回路は、図１３に示すように、電源線１と接地
線２と信号線３との間に接続された、選択ゲートトラン
ジスタ４Ａと、保持容量５Ａと、駆動トランジスタ６Ａ
と、電流制御素子７Ａと、寄生容量８Ａと、スイッチン
グトランジスタ９Ａとから概略構成されている。Seventh Embodiment FIG. 13 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the seventh embodiment of the present invention. As shown in FIG. 13, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
, A current control element 7A, a parasitic capacitance 8A, and a switching transistor 9A.
【００５６】この例の電流制御素子の駆動回路において
は、電源線１，接地線２，信号線３，選択ゲートトラン
ジスタ４Ａ，保持容量５Ａ，駆動トランジスタ６Ａ，電
流制御素子７Ａ及び寄生容量８Ａの構成は、図１２に示
された第５実施例の場合と同様であるが、これらに加え
て、図１３に示すスイッチングトランジスタ９Ａを有す
る点が、第５実施例の場合と異なっている。スイッチン
グトランジスタ９Ａは、Ｐチャネル電界効果トランジス
タからなり、ゲート電極を選択線に接続され、ソース電
極を電源線１に接続され、ドレイン電極を駆動トランジ
スタ６Ａのソース電極及び保持容量５Ａの一端に接続さ
れている。In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4A, the storage capacitor 5A, the drive transistor 6A, the current control element 7A and the parasitic capacitance 8A are configured. Is the same as the case of the fifth embodiment shown in FIG. 12, but is different from the case of the fifth embodiment in that it has a switching transistor 9A shown in FIG. 13 in addition to these. The switching transistor 9A is composed of a P-channel field effect transistor, the gate electrode is connected to the selection line, the source electrode is connected to the power supply line 1, and the drain electrode is connected to the source electrode of the drive transistor 6A and one end of the storage capacitor 5A. ing.
【００５７】この例の電流制御素子の駆動回路は、図８
に示された第３実施例の場合のＮチャネル電界効果トラ
ンジスタからなる選択ゲートトランジスタ４，駆動トラ
ンジスタ６及びスイッチングトランジスタ９を、Ｐチャ
ネル電界効果トランジスタからなる選択ゲートトランジ
スタ４Ａ，駆動トランジスタ６Ａ及びスイッチングトラ
ンジスタ９Ａによって置き替えたものであって、従っ
て、図８に示された第３実施例の場合と比べて、電圧の
関係が逆になり、電流の向きが逆になるが、その動作
は、第３実施例の場合と同様であって、図９に示された
タイミングチャートを適用することができるので、以下
においては、詳細な説明を省略する。The drive circuit for the current control element of this example is shown in FIG.
In the case of the third embodiment shown in FIG. 3, the selection gate transistor 4, the driving transistor 6 and the switching transistor 9 which are N-channel field effect transistors, the selection gate transistor 4A which is a P-channel field effect transistor, the driving transistor 6A and the switching transistor 9A, and therefore the voltage relationship is reversed and the current direction is reversed compared to the case of the third embodiment shown in FIG. 8, but the operation is Since the timing chart shown in FIG. 9 can be applied in the same manner as in the case of the third embodiment, detailed description will be omitted below.
【００５８】このように、この例の電流制御素子の駆動
回路によれば、第５実施例の場合と同様に駆動トランジ
スタ６Ａのしきい値を補整して、その変化の影響を受け
ないようにすることができる。この際、第５実施例の場
合と比較して、スイッチングトランジスタ９Ａが余分に
必要となるが、スイッチングトランジスタ９Ａによる保
持容量５Ａ及び電流制御素子７の寄生容量８のリセット
を、選択ゲートトランジスタ４Ａによる保持容量５Ａの
書き込みと独立に行うことができるので、リセットの時
期を選択することによって、保持容量５Ａ及び寄生容量
８Ａのリセットをより確実に行うことができるようにな
る。As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6A is adjusted so as not to be affected by the change, as in the case of the fifth embodiment. can do. At this time, an extra switching transistor 9A is required as compared with the case of the fifth embodiment, but reset of the storage capacitor 5A and the parasitic capacitance 8 of the current control element 7 by the switching transistor 9A is performed by the selection gate transistor 4A. Since the writing can be performed independently of the storage capacitor 5A, the storage capacitor 5A and the parasitic capacitance 8A can be reset more reliably by selecting the reset time.
【００５９】◇第８実施例
図１４は、本発明の第８実施例である電流制御素子の駆
動回路の構成を示す回路図である。この例の電流制御素
子の駆動回路は、図１３に示すように、電源線１と接地
線２と信号線３との間に接続された、選択ゲートトラン
ジスタ４Ａと、保持容量５Ａと、駆動トランジスタ６Ａ
と、電流制御素子７Ａと、寄生容量８Ａと、スイッチン
グトランジスタ１０Ａとから概略構成されている。Eighth Embodiment FIG. 14 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the eighth embodiment of the present invention. As shown in FIG. 13, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
, A current control element 7A, a parasitic capacitance 8A, and a switching transistor 10A.
【００６０】この例の電流制御素子の駆動回路において
は、電源線１，接地線２，信号線３，選択ゲートトラン
ジスタ４Ａ，保持容量５Ａ，駆動トランジスタ６Ａ，電
流制御素子７Ａ及び寄生容量８Ａの構成は、図１２に示
された第５実施例の場合と同様であるが、これらに加え
て、図１４に示すスイッチングトランジスタ１０Ａを有
する点が、第５実施例の場合と異なっている。スイッチ
ングトランジスタ１０Ａは、Ｐチャネル電界効果トラン
ジスタからなり、ゲート電極を選択線に接続され、ソー
ス電極を電源線１に接続され、ドレイン電極を駆動トラ
ンジスタ６Ａのゲート電極及び保持容量５Ａの一端に接
続されている。In the drive circuit of the current control element of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4A, the storage capacitor 5A, the drive transistor 6A, the current control element 7A and the parasitic capacitance 8A. Is the same as the case of the fifth embodiment shown in FIG. 12, but is different from the case of the fifth embodiment in that it has a switching transistor 10A shown in FIG. 14 in addition to these. The switching transistor 10A is composed of a P-channel field effect transistor, the gate electrode is connected to the selection line, the source electrode is connected to the power supply line 1, and the drain electrode is connected to the gate electrode of the drive transistor 6A and one end of the storage capacitor 5A. ing.
【００６１】この例の電流制御素子の駆動回路は、図１
０に示された第４実施例の場合のＮチャネル電界効果ト
ランジスタからなる選択ゲートトランジスタ４，駆動ト
ランジスタ６及びスイッチングトランジスタ１０を、Ｐ
チャネル電界効果トランジスタからなる選択ゲートトラ
ンジスタ４Ａ，駆動トランジスタ６Ａ及びスイッチング
トランジスタ１０Ａによって置き替えたものであって、
従って、図１０に示された第４実施例の場合と比べて、
電圧の関係が逆になるので、電流の向きが逆になるが、
その動作は、第４実施例の場合と同様であって、図１１
に示されたタイミングチャートを適用することができる
ので、以下においては、詳細な説明を省略する。The drive circuit for the current control element of this example is shown in FIG.
The selection gate transistor 4, the driving transistor 6 and the switching transistor 10 which are N-channel field effect transistors in the case of the fourth embodiment shown in FIG.
A selection gate transistor 4A which is a channel field effect transistor, a driving transistor 6A and a switching transistor 10A are replaced.
Therefore, as compared with the case of the fourth embodiment shown in FIG.
Since the relationship of voltage is reversed, the direction of current is reversed,
The operation is the same as in the case of the fourth embodiment.
Since the timing chart shown in FIG. 7 can be applied, detailed description will be omitted below.
【００６２】このように、この例の電流制御素子の駆動
回路によれば、第５実施例の場合と同様に駆動トランジ
スタ６Ａのしきい値を補正して、その変化の影響を受け
ないようにすることができる。この際、第５実施例の場
合と比較して、スイッチングトランジスタ１０Ａが余分
に必要となるが、スイッチングトランジスタ１０Ａによ
る保持容量５Ａ及び電流制御素子７の寄生容量８のリセ
ットを、選択ゲートトランジスタ４Ａによる保持容量５
Ａの書き込みと独立に行うことができるので、リセット
の時期を選択することによって、保持容量５Ａ及び寄生
容量８Ａのリセットをより確実に行うことができるよう
になる。As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6A is corrected in the same manner as in the fifth embodiment so that it is not affected by the change. can do. At this time, an extra switching transistor 10A is required as compared with the case of the fifth embodiment, but the resetting of the storage capacitor 5A and the parasitic capacitance 8 of the current control element 7 by the switching transistor 10A is performed by the selection gate transistor 4A. Storage capacity 5
Since the data can be written independently of A, the storage capacitor 5A and the parasitic capacitance 8A can be reset more reliably by selecting the reset time.
【００６３】以上、この発明の実施例を図面により詳述
してきたが、具体的な構成はこの実施例に限られたもの
ではなく、この発明の要旨を逸脱しない範囲の設計の変
更等があってもこの発明に含まれる。例えば、第３実施
例，第４実施例及び第７実施例，第８実施例において、
スイッチングトランジスタによる保持容量５と寄生容量
８の放電は、非選択期間でもよく、又は選択期間の初期
でもよい。非選択期間の場合は、その終期に限らず、任
意のタイミングで行うことができる。選択期間の初期の
場合は、選択ゲートトランジスタをオフにしておくこと
が必要である。また、各実施例において、駆動トランジ
スタがＮチャネル電界効果トランジスタ又はＰチャネル
電界効果トランジスタの場合に、その他の選択ゲートト
ランジスタ及びスイッチングトランジスタは、Ｎチャネ
ル電界効果トランジスタ又はＰチャネル電界効果トラン
ジスタに限らず、Ｎチャネル電界効果トランジスタとＰ
チャネル電界効果トランジスタとを任意に混用すること
が可能である。さらに、この発明の電流制御素子の駆動
回路は、多数の電流制御素子を平面状に、行方向と列方
向とにマトリクス状に配列した画像表示装置における、
電流制御素子の駆動回路にも適用可能であって、この場
合に前述の各実施例の効果を得られることは明らかであ
る。また、第３、第４の実施例では、スイッチングトラ
ンジスタ９のソース電極が、接地線２に接続されている
が、接地線２とは異なる電圧の他の電源線に接続し、リ
セット時の駆動トランジスタ６のソース電圧ＶＳを０Ｖ
ではない電圧に設定することで、回路設計の許容度を広
げることもできる。第７、第８の実施例についても同様
な変更が可能である。Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific structure is not limited to this embodiment, and there are design changes and the like within a range not departing from the gist of the present invention. However, it is included in this invention. For example, in the third, fourth, seventh and eighth embodiments,
The discharge of the storage capacitor 5 and the parasitic capacitance 8 by the switching transistor may be performed in the non-selection period or in the initial stage of the selection period. In the case of the non-selected period, it can be performed at any timing, not limited to the end thereof. At the beginning of the selection period, it is necessary to turn off the selection gate transistor. In each embodiment, when the drive transistor is the N-channel field effect transistor or the P-channel field effect transistor, the other selection gate transistors and the switching transistors are not limited to the N-channel field effect transistor or the P-channel field effect transistor, N-channel field effect transistor and P
It is possible to arbitrarily mix the channel field effect transistor. Furthermore, the drive circuit of the current control element of the present invention is an image display device in which a large number of current control elements are arranged in a plane, in a matrix in the row direction and the column direction,
It is also applicable to the drive circuit of the current control element, and in this case, it is obvious that the effects of the above-described embodiments can be obtained. Further, in the third and fourth embodiments, the source electrode of the switching transistor 9 is connected to the ground line 2, but it is connected to another power supply line having a voltage different from that of the ground line 2 to drive at the time of reset. The source voltage VS of the transistor 6 is 0V
By setting the voltage to other than, it is possible to widen the tolerance of the circuit design. Similar changes can be made to the seventh and eighth embodiments.
【００６４】[0064]
【発明の効果】以上説明したように、本発明の電流制御
素子の駆動回路及び画像表示装置によれば、電流制御素
子を駆動する駆動トランジスタのしきい値特性にばらつ
きがあっても影響を受けないようにすることができると
ともに、従来の同様な電流制御素子の駆動回路と比較し
て、画素回路を構成する素子数を少なくすることができ
るので、画素の開口率を大きくできるとともに、製造プ
ロセスが容易になる。また、小さな書き込み電圧で、駆
動回路の書き込みを行うことができるので、消費電力の
点からも有利である。As described above, according to the drive circuit of the current control element and the image display device of the present invention, even if the threshold characteristic of the drive transistor for driving the current control element varies, it is not affected. In addition, the number of elements forming the pixel circuit can be reduced as compared with the conventional similar current control element drive circuit, so that the aperture ratio of the pixel can be increased and the manufacturing process can be improved. Will be easier. Further, since the driving circuit can be written with a small writing voltage, it is advantageous in terms of power consumption.
【図１】本発明の第１実施例である電流制御素子の駆動
回路の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a first embodiment of the present invention.
【図２】同実施例の電流制御素子の駆動回路の動作を説
明するタイミングチャートである。FIG. 2 is a timing chart explaining the operation of the drive circuit of the current control element of the same embodiment.
【図３】同実施例における駆動トランジスタのＩＤＳ−
ＶＧＳ特性を示す図である。FIG. 3 is an IDS- of a drive transistor in the same embodiment.
It is a figure which shows a VGS characteristic.
【図４】同実施例における電流制御素子のＩＬ−ＶＬ特
性を示す図である。FIG. 4 is a diagram showing an IL-VL characteristic of the current control element in the example.
【図５】駆動トランジスタの特性がばらついているとき
のＩＤＳ−ＶＧＳ特性を示す図である。FIG. 5 is a diagram showing IDS-VGS characteristics when the characteristics of drive transistors vary.
【図６】駆動トランジスタの特性がばらついているとき
のＶＧＳの過渡特性を示す図である。FIG. 6 is a diagram showing transient characteristics of VGS when the characteristics of drive transistors vary.
【図７】本発明の第２実施例である電流制御素子の駆動
回路の動作を説明するタイミングチャートである。FIG. 7 is a timing chart for explaining the operation of the drive circuit for the current control element according to the second embodiment of the present invention.
【図８】本発明の第３実施例である電流制御素子の駆動
回路の構成を示す回路図である。FIG. 8 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a third embodiment of the present invention.
【図９】同実施例の電流制御素子の駆動回路の動作を説
明するタイミングチャートである。FIG. 9 is a timing chart for explaining the operation of the drive circuit for the current control element of the same example.
【図１０】本発明の第４実施例である電流制御素子の駆
動回路の構成を示す回路図である。FIG. 10 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a fourth embodiment of the present invention.
【図１１】同実施例の電流制御素子の駆動回路の動作を
説明するタイミングチャートである。FIG. 11 is a timing chart for explaining the operation of the drive circuit for the current control element of the same example.
【図１２】本発明の第５実施例である電流制御素子の駆
動回路の構成を示す回路図である。FIG. 12 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a fifth embodiment of the present invention.
【図１３】本発明の第７実施例である電流制御素子の駆
動回路の構成を示す回路図である。FIG. 13 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a seventh embodiment of the present invention.
【図１４】本発明の第８実施例である電流制御素子の駆
動回路の構成を示す回路図である。FIG. 14 is a circuit diagram showing a configuration of a drive circuit for a current control element that is an eighth embodiment of the present invention.
【図１５】第１の従来例の電流制御素子の駆動回路の構
成を示す図である。FIG. 15 is a diagram showing a configuration of a drive circuit of a current control element of a first conventional example.
【図１６】駆動トランジスタの特性がばらついていると
きのＩＤＳ−ＶＧＳ特性を示す図である。FIG. 16 is a diagram showing the IDS-VGS characteristics when the characteristics of the drive transistor vary.
【図１７】第２の従来例の電流制御素子の駆動回路の構
成を示す図である。FIG. 17 is a diagram showing a configuration of a drive circuit of a current control element of a second conventional example.
【図１８】第２の従来例の電流制御素子の駆動回路の動
作を説明するタイミングチャートである。FIG. 18 is a timing chart explaining the operation of the drive circuit of the current control element of the second conventional example.
１ 電源線（第１の電源線） ２ 接地線（第２の電源線） ３ 信号線 ４，４Ａ 選択ゲートトランジスタ ５，５Ａ 保持容量 ６，６Ａ 駆動トランジスタ ７，７Ａ 電流制御素子 ８，８Ａ 寄生容量 ９，９Ａ スイッチングトランジスタ １０，１０Ａ スイッチングトランジスタ 1 power line (first power line) 2 Ground wire (second power line) 3 signal lines 4, 4A select gate transistor 5,5A holding capacity 6,6A drive transistor 7,7A current control element 8.8A parasitic capacitance 9,9A switching transistor 10,10A switching transistor
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０３Ｋ 17/687 Ｈ０５Ｂ 33/14 Ａ Ｈ０５Ｂ 33/14 Ｈ０３Ｋ 17/687 Ｈ Ｆターム(参考） 3K007 AB02 AB06 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 DD22 DD26 DD28 EE28 FF11 JJ03 JJ04 JJ05 5J055 AX04 AX49 BX16 CX29 DX13 DX14 DX53 DX55 EX01 EX07 EX21 EY00 EY10 EY21 EY29 FX12 FX17 FX24 FX35 GX00 GX01 GX06 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H03K 17/687 H05B 33/14 A H05B 33/14 H03K 17/687 HF term (reference) 3K007 AB02 AB06 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 DD22 DD26 DD28 EE28 FF11 JJ03 JJ04 JJ05 5J055 AX04 AX49 BX16 CX29 DX13 DX14 DX53 DX55 EX01 EX07 EX21 EY00 EY10 EY21 EY29 FX12 FX17 FX24 FX35 GX06 GX06 GX00 GX00
Claims (10)
列に接続された駆動トランジスタと電流制御素子と、前
記駆動トランジスタと電流制御素子の接続点と前記駆動
トランジスタのゲート電極との間に接続された保持容量
と、信号線と前記駆動トランジスタのゲート電極との間
に接続された選択ゲートトランジスタとを備え、 前記駆動回路の選択期間に、選択ゲートトランジスタを
オンにして前記信号線から第１の信号電圧を入力し、前
記保持容量に書き込まれた信号電荷を前記駆動トランジ
スタを経て放電したのち、前記信号線から第２の信号電
圧を入力して前記保持容量に保持し、前記駆動回路の非
選択期間に、前記選択ゲートトランジスタをオフにして
前記駆動トランジスタを経て前記電流制御素子に電流を
流すことを特徴とする電流制御素子の駆動回路。1. A drive transistor and a current control element connected in series between a first power supply line and a second power supply line, a connection point between the drive transistor and the current control element, and a gate electrode of the drive transistor. And a select gate transistor connected between a signal line and a gate electrode of the drive transistor, the select gate transistor being turned on during a select period of the drive circuit. A first signal voltage is input from a signal line, the signal charge written in the storage capacitor is discharged through the drive transistor, and then a second signal voltage is input from the signal line and stored in the storage capacitor. During the non-selection period of the drive circuit, the selection gate transistor is turned off, and a current is caused to flow through the drive transistor to the current control element. Drive circuit of the control element.
信号線にリセット信号電圧を入力することによって、前
記保持容量及び前記電流制御素子の寄生容量に蓄積され
ている電荷をリセットすることを特徴とする請求項１記
載の電流制御素子の駆動回路。2. A reset signal voltage is input to the signal line at the beginning of the selection period of the drive circuit to reset the charges accumulated in the storage capacitor and the parasitic capacitance of the current control element. The drive circuit for the current control element according to claim 1, wherein the drive circuit is for a current control element.
駆動トランジスタをオンにし、前記第１の電源線をリセ
ット信号電圧とすることによって、前記保持容量及び前
記電流制御素子の寄生容量に蓄積されている電荷をリセ
ットすることを特徴とする請求項１記載の電流制御素子
の駆動回路。3. The storage capacitor and the parasitic capacitance of the current control element are accumulated by turning on the drive transistor and setting the first power supply line to a reset signal voltage in the initial stage of the selection period of the drive circuit. 2. The drive circuit for a current control element according to claim 1, wherein the electric charge that has been stored is reset.
ンジスタとが、Ｎチャネル電界効果トランジスタからな
ることを特徴とする請求項１乃至３のいずれか一に記載
の電流制御素子の駆動回路。4. The drive circuit for a current control element according to claim 1, wherein the select gate transistor and the drive transistor are N-channel field effect transistors.
ンジスタとが、Ｐチャネル電界効果トランジスタからな
ることを特徴とする請求項１乃至３のいずれか一に記載
の電流制御素子の駆動回路。5. The drive circuit for a current control element according to claim 1, wherein the select gate transistor and the drive transistor are P-channel field effect transistors.
ース電極との間にスイッチングトランジスタを備え、前
記駆動回路の非選択期間又は選択期間の初期に、前記ス
イッチングトランジスタをオンにすることによって、前
記保持容量及び前記電流制御素子の寄生容量に蓄積され
ている電荷をリセットすることを特徴とする請求項１記
載の電流制御素子の駆動回路。6. A storage transistor is provided between a gate electrode and a source electrode of the drive transistor, and the storage capacitor is turned on by turning on the switching transistor at the beginning of a non-selection period or a selection period of the drive circuit. 2. The drive circuit for the current control element according to claim 1, wherein the electric charge accumulated in the parasitic capacitance of the current control element is reset.
記他方の電源線との間にスイッチングトランジスタを備
え、前記駆動回路の非選択期間又は選択期間の初期に、
前記スイッチングトランジスタをオンにすることによっ
て、前記保持容量及び前記電流制御素子の寄生容量に蓄
積されている電荷をリセットすることを特徴とする請求
項１記載の電流制御素子の駆動回路。7. A switching transistor is provided between the gate electrode of the drive transistor and the other power supply line, and at the beginning of a non-selection period or a selection period of the drive circuit,
The drive circuit for the current control element according to claim 1, wherein the charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor.
ンジスタとスイッチングトランジスタとが、Ｎチャネル
電界効果トランジスタからなることを特徴とする請求項
６又は７に記載の電流制御素子の駆動回路。8. The drive circuit for a current control element according to claim 6, wherein the select gate transistor, the drive transistor, and the switching transistor are N-channel field effect transistors.
ンジスタとスイッチングトランジスタとが、Ｐチャネル
電界効果トランジスタからなることを特徴とする請求項
６又は７に記載の電流制御素子の駆動回路。9. The drive circuit for the current control element according to claim 6, wherein the select gate transistor, the drive transistor, and the switching transistor are P-channel field effect transistors.
流制御素子の駆動回路を複数個平面状に配列して、行方
向と列方向とに駆動可能なように構成してなることを特
徴とする画像表示装置。10. A plurality of drive circuits for the current control element according to claim 1 are arranged in a plane so as to be driven in a row direction and a column direction. Characteristic image display device.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002070730A JP3613253B2 (en) | 2002-03-14 | 2002-03-14 | Current control element drive circuit and image display device |
| PCT/JP2003/002578 WO2003075256A1 (en) | 2002-03-05 | 2003-03-05 | Image display and its control method |
| US10/506,371 US7876294B2 (en) | 2002-03-05 | 2003-03-05 | Image display and its control method |
| US12/877,068 US20100328294A1 (en) | 2002-03-05 | 2010-09-07 | Image display apparatus and control method therefor |
| US12/976,757 US8519918B2 (en) | 2002-03-05 | 2010-12-22 | Image display apparatus and control method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002070730A JP3613253B2 (en) | 2002-03-14 | 2002-03-14 | Current control element drive circuit and image display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003271095A true JP2003271095A (en) | 2003-09-25 |
| JP3613253B2 JP3613253B2 (en) | 2005-01-26 |
Family
ID=29201224
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002070730A Expired - Lifetime JP3613253B2 (en) | 2002-03-05 | 2002-03-14 | Current control element drive circuit and image display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3613253B2 (en) |
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