JP2008026468A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of reducing electric power consumption by compensating in circuits the loss of a signal voltage produced by a correction function. <P>SOLUTION: A switching transistor Tr 4 conducts in a sampling period to connect a drive transistor Trd to a power source potential Vcc, fetches an output current from the drive transistor Trd, for the time in which the signal potential V<SB>sig</SB>is sampled, negatively feeds back the same to a pixel capacity Cs, and eliminates the influence of carrier mobility μ of the drive transistor Trd from the input voltage Vgs. In order to compensate the loss of the input voltage Vgs generated by the negative feedback, a coupling capacity Cc to previously add the topping up to the input voltage Vgs by gate coupling of a switching transistor Tr 2 to a pixel capacity Cs is provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image display device that performs display by driving a light-emitting element arranged for each pixel. More specifically, the present invention relates to a so-called active matrix type image display device that controls an amount of current supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel circuit. More specifically, the present invention relates to a technique for reducing power consumption of such an active matrix image display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional pixel circuit is arranged at a portion where a row scanning line for supplying a control signal and a column signal line for supplying a video signal intersect, and includes at least a sampling transistor, a pixel capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control signal supplied from the scanning line and samples the video signal supplied from the signal line. The pixel capacitor holds an input voltage corresponding to the signal potential of the sampled video signal. The drive transistor supplies an output current as a drive current during a predetermined light emission period in accordance with the input voltage held in the pixel capacitor. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives an input voltage held in the pixel capacitor at the gate, causes an output current to flow between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input voltage written in the pixel capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  However, the variation factor of the output current with respect to the light emitting element is not only the threshold voltage Vth of the drive transistor. As is apparent from the transistor characteristic equation 1 described above, the output current Ids varies even when the mobility μ of the drive transistor varies. As a result, the uniformity of the screen is impaired. Correcting the variation in mobility is also a problem to be solved.

  In view of the above-described problems of the conventional technique, it is a general object of the present invention to provide an image display device in which a mobility correction function is incorporated for each pixel in addition to a threshold voltage correction function of a drive transistor. In particular, it is a direct object to provide an image display device capable of reducing power consumption by compensating for a loss of signal voltage caused by a correction function in a circuit manner. In order to achieve this purpose, the following measures were taken. That is, an image display device according to the present invention includes a pixel array unit, a scanner unit, and a signal unit, and the pixel array unit includes a first scanning line, a second scanning line, a third scanning line, and a first scanning line arranged in rows. 4 scanning lines, signal lines arranged in columns, matrix pixel circuits connected to these scanning lines and signal lines, and first, second, and third potentials necessary for the operation of each pixel circuit The signal unit supplies a video signal to the signal line, and the scanner unit includes a first scan line, a second scan line, a third scan line, and a fourth scan. A control signal is supplied to the line to sequentially scan the pixel circuit for each row. Each pixel circuit includes a sampling transistor, a drive transistor, a first switching transistor, a second switching transistor, a third switching transistor, and a pixel. Capacity and luminous element And the sampling transistor conducts in response to a control signal supplied from the first scanning line during a predetermined sampling period and samples the signal potential of the video signal supplied from the signal line into the pixel capacitor, and The capacitor applies an input voltage to the gate of the drive transistor according to the signal potential of the sampled video signal, the drive transistor supplies an output current according to the input voltage to the light emitting element, and the light emission The element emits light with a luminance corresponding to the signal potential of the video signal by an output current supplied from the drive transistor during a predetermined light emission period. The first switching transistor is turned on according to a control signal supplied from the second scanning line prior to the sampling period to set the gate of the drive transistor to the first potential, and the second switching transistor is set to the sampling period. The drive transistor is turned on in response to a control signal supplied from the third scanning line prior to setting the source of the drive transistor to the second potential, and the third switching transistor is supplied from the fourth scanning line prior to the sampling period. The drive transistor is turned on in response to the control signal to connect the drive transistor to the third potential, so that a voltage corresponding to the threshold voltage of the drive transistor is held in the pixel capacitor to correct the influence of the threshold voltage. The third switching transistor is turned on again during the sampling period to connect the drive transistor to the third potential, and takes out an output current from the drive transistor while the signal potential is sampled, and this is output to the pixel capacitor. To negatively influence the carrier mobility of the drive transistor from the input voltage. The third switching transistor maintains a conducting state during a light emission period subsequent to the sampling period and allows the output current to flow through the light emitting element. When removing the influence of the carrier mobility of the drive transistor from the input voltage, in order to compensate for the loss of the input voltage caused by the negative feedback of the output current extracted from the drive transistor, any one of the additions to the input voltage is switched in advance. A coupling capacitor added to the pixel capacitor is provided by gate coupling of the transistor.

  Preferably, the coupling capacitor is connected between a source of the drive transistor and a gate of the first switching transistor, and is caused by gate coupling that occurs when a control signal supplied from the second scan line is released. An addition to the input voltage is added to the pixel capacitance.

  According to the present invention, the mobility of the drive transistor is corrected using a part of the period during which the signal potential is sampled into the pixel capacitance (sampling period). Specifically, in the latter half of the sampling period, the switching transistor is turned on to make the current path conductive, and a drive current is passed through the drive transistor. This drive current has a magnitude corresponding to the sampled signal potential. At this stage, the light emitting element is in a reverse bias state, and the drive current does not flow through the light emitting element but is charged to its parasitic capacitance and pixel capacitance. Thereafter, the sampling pulse falls, and the gate of the drive transistor is disconnected from the signal line. During the correction period from when the switching transistor is turned on to when the sampling transistor is turned off, the drive current is negatively fed back from the drive transistor to the pixel capacitor, and that amount is subtracted from the signal potential sampled in the pixel capacitor. Since this negative feedback amount acts in a direction to suppress variation in mobility of the drive transistor, mobility correction can be performed for each pixel. That is, when the mobility of the drive transistor is large, the amount of negative feedback with respect to the pixel capacitance is increased, the signal potential held in the pixel capacitance is greatly reduced, and as a result, the output current of the drive transistor is suppressed. On the other hand, when the mobility of the drive transistor is small, the negative feedback amount is also small, and the signal potential held in the pixel capacitor is not significantly affected. Therefore, the output current of the drive transistor does not drop so much. The amount of negative feedback is at a level corresponding to the signal potential applied directly from the signal line to the gate of the drive transistor. That is, the negative feedback amount increases as the signal potential increases and the luminance increases. As described above, the mobility correction is performed according to the luminance level.

  As described above, the mobility correction function of the drive transistor extracts the output current from the drive transistor while the signal potential is sampled, negatively feeds back this to the pixel capacitance, and the carrier mobility of the drive transistor from the input voltage. Is excluded. In order to apply negative feedback, the input voltage written in the pixel capacitor is consumed. For this reason, in order to ensure the desired light emission luminance, the signal potential of the video signal needs to be added to the voltage consumed for mobility correction in addition to the input voltage required for light emission, and the signal amplitude is Increase, leading to an increase in power consumption. Therefore, in the present invention, before entering the mobility correction period, the voltage for the negative feedback consumed at the time of mobility correction is added in advance to the pixel capacitance by the gate coupling of the switching transistor. With this configuration, it is possible to reduce the amplitude of the video signal and contribute to low power consumption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing the overall configuration of an image display apparatus according to the present invention. As shown in the figure, this image display apparatus basically includes a pixel array unit 1 and a drive unit including a scanner unit and a signal unit. The pixel array unit 1 includes a scanning line WS, a scanning line AZ1, a scanning line AZ2, and a scanning line DS arranged in a row, a signal line SL arranged in a column, and the scanning lines WS, AZ1, AZ2, DS. And a matrix pixel circuit 2 connected to the signal line SL, and a plurality of power supply lines for supplying the first potential Vss1, the second potential Vss2, and the third potential Vcc necessary for the operation of each pixel circuit 2. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72, and supplies control signals to the scanning line WS, the scanning line DS, the scanning line AZ1, and the scanning line AZ2, respectively. The pixel circuit is sequentially scanned for each row.

  FIG. 2 is a circuit diagram showing a configuration example of a pixel circuit incorporated in the image display device shown in FIG. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a pixel capacitor Cs, a coupling capacitor Cc, A light emitting element EL. The sampling transistor Tr1 conducts in response to a control signal supplied from the scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the pixel capacitor Cs. The pixel capacitor Cs applies an input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 is turned on according to the control signal supplied from the scanning line AZ1 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vss1. The second switching transistor Tr3 is turned on in response to a control signal supplied from the scanning line AZ2 prior to the sampling period, and sets the source S of the drive transistor Trd to the second potential Vss2. The third switching transistor Tr4 is turned on in response to a control signal supplied from the scanning line DS prior to the sampling period to connect the drive transistor Trd to the third potential Vcc, and thus corresponds to the threshold voltage Vth of the drive transistor Trd. The voltage is held in the pixel capacitor Cs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 is turned on again in response to the control signal supplied from the scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vcc, and causes the output current Ids to flow through the light emitting element EL.

  As a characteristic matter, the pixel circuit 2 includes a coupling capacitor Cc. The coupling capacitor Cc is connected between the source S of the drive transistor Trd and the gate of the switching transistor Tr2, and the input voltage Vgs is generated by gate coupling generated when the control signal AZ1 supplied from the scanning line AZ1 is released. Is added to the pixel capacitance Cs.

  As is apparent from the above description, the pixel circuit 2 includes five transistors Tr1 to Tr4 and Trd, two capacitors Cs and Cc, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 3 is a schematic diagram in which only the pixel circuit 2 is extracted from the image display device shown in FIG. In order to facilitate understanding, the signal potential Vsig of the video signal sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. . The operation of the pixel circuit 2 according to the present invention will be described below with reference to FIG.

  FIG. 4 is a timing chart of the pixel circuit shown in FIG. With reference to FIG. 4, the operation of the pixel circuit according to the present invention shown in FIG. 3 will be described in detail. FIG. 4 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2 and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level, and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 4, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  After timing T1, the control signal AZ2 rises at timing T21, and the switching transistor Tr3 is turned on. As a result, the source S of the drive transistor Trd is initialized to the predetermined potential Vss2. Subsequently, at timing T22, the control signal AZ1 rises and the switching transistor Tr2 is turned on. As a result, the potential of the gate G of the drive transistor Trd is initialized to a predetermined potential Vss1. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T21-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to low level, and then the control signal DS is set to low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the pixel capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, at timing T4a, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the pixel capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  By the way, at timing T4a, the control signal AZ1 falls. This causes a negative fluctuation in the gate voltage of the switching transistor Tr2. Due to the change in the gate voltage of the switching transistor Tr2, a negative coupling Vb enters the source S of the drive transistor Trd via the coupling capacitor Cc. As a result, the gate voltage Vgs of the drive transistor Trd held in the pixel capacitor Cs becomes Vth + Vb.

  After performing the Vth correction and the negative coupling Vb in this way, the control signal WS is switched to the high level at the timing T5, the sampling transistor Tr1 is turned on, and the signal potential Vsig of the video signal is written in the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, almost most of the signal potential Vsig of the video signal is written into the pixel capacitor Cs. To be precise, for Vss1. The difference Vsig−Vss1 of Vsig is written to the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth + Vb) obtained by adding Vth + Vb previously detected and held and Vsig−Vss1 sampled this time. Hereinafter, for simplicity of explanation, assuming that Vss1 = 0V, the gate / source voltage Vgs becomes Vsig + Vth + Vb as shown in the timing chart of FIG. The sampling of the signal potential Vsig of the video signal is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in the present invention, the mobility correction is performed in the period T6-T7 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed to the level of the signal potential Vsig of the video signal. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 4, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

  In this mobility correction period T6-T7, the correction amount ΔV is subtracted from the gate voltage Vgs. In other words, the gate voltage Vgs held in the pixel capacitor Cs is slightly consumed by this mobility correction operation. As a result, Vgs = Vsig + Vth + Vb−ΔV. Here, assuming that the added value Vb due to the negative coupling is substantially equal to the mobility correction amount ΔV, the gate voltage Vgs after the mobility correction is approximately Vth + Vsig. Therefore, since a net input voltage substantially equal to the signal potential Vsig of the video signal is applied to the drive transistor Trd, it is not necessary to set the signal potential Vsig of the video signal larger in advance.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the signal potential Vsig of the video signal is released, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth + Vb). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth + Vb into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV + Vb) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal potential Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the signal potential Vsig of the video signal. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the signal potential Vsig of the video signal. In addition, gate coupling Vb is added to compensate for the decrease in ΔV.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the gate coupling operation, the signal potential sampling operation, the mobility correction operation, and the light emission operation are repeated again.

  FIG. 5 is a circuit diagram showing a state of the pixel circuit 2 in the mobility correction period T6-T7. As shown in the figure, in the mobility correction period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are on, while the remaining switching transistors Tr2 and Tr3 are off. In this state, the source potential (S) of the drive transistor Tr4 is Vss1-Vth. This source potential (S) is also the anode potential of the light emitting element EL. By setting Vss1−Vth <VthEL as described above, the light emitting element EL is placed in a reverse bias state, and exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd flows into the combined capacitance C = Cs + Coled of the pixel capacitance Cs and the equivalent capacitance Coled of the light emitting element EL. In other words, a part of the drain current Ids is negatively fed back to the pixel capacitor Cs, and the mobility is corrected.

  FIG. 6 is a graph of the above-described transistor characteristic formula 2, in which Ids is plotted on the vertical axis and Vsig is plotted on the horizontal axis. In the graph of FIG. 6, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example, when the signal potential Vsig of the video signal of the same level is written in both the pixels 1 and 2, the output current Ids 1 ′ flowing through the pixel 1 having the high mobility μ is equal to the mobility μ unless the mobility is corrected. A large difference is generated as compared with the output current Ids2 'flowing through the small pixel 2. In this way, a large difference occurs between the output currents Ids due to the variation in the mobility μ, so that unevenness occurs and the uniformity of the screen is impaired.

  Therefore, in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As apparent from the previous transistor characteristic equation 1, the drain current Ids increases when the mobility is large. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 6, the negative feedback amount ΔV1 of the pixel 1 having a high mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 having a low mobility. Therefore, the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown in the figure, when ΔV1 is corrected in the pixel 1 having a high mobility μ, the output current greatly decreases from Ids1 ′ to Ids1. On the other hand, since the correction amount ΔV2 of the pixel 2 having the low mobility μ is small, the output current Ids2 ′ does not decrease so much to Ids2. As a result, Ids1 and Ids2 are substantially equal, and the variation in mobility is cancelled. Since the cancellation of the variation in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen becomes extremely high. In summary, when there are pixels 1 and 2 having different mobility, the correction amount ΔV1 of the pixel 1 having high mobility is smaller than the correction amount ΔV2 of the pixel 2 having low mobility. That is, as the mobility increases, ΔV increases and the decrease value of Ids increases. As a result, pixel current values having different mobilities are made uniform, and variations in mobility can be corrected.

For reference, numerical analysis of the mobility correction described above is performed. As shown in FIG. 5, the analysis is performed by taking the source potential of the drive transistor Trd as a variable V in a state where the transistors Tr1 and Tr4 are turned on. Assuming that the source potential (S) of the drive transistor Trd is V, the drain current Ids flowing through the drive transistor Trd is as shown in Equation 3 below.

Further, Ids = dQ / dt = CdV / dt is established as shown in the following Expression 4 by the relationship between the drain current Ids and the capacitance C (= Cs + Coled).

Both sides are integrated by substituting Equation 3 into Equation 4. Here, the initial state of the source voltage V is -Vth, and the mobility variation correction time (T6-T7) is t. When this differential equation is solved, the pixel current with respect to the mobility correction time t is given as shown in Equation 5 below.

  As is apparent from the graph of FIG. 6, in the mobility correction, the source voltage (S) of the drive transistor Trd increases by ΔV, so that the gate voltage Vgs of the drive transistor Trd decreases by ΔV. For this reason, the input video signal needs to have an amplitude obtained by adding in advance the signal potential Vsig necessary for light emission with a desired luminance and the amount prepared for the phenomenon of ΔV. Therefore, if no measures are taken, the mobility correction will result in a significant increase in the video signal amplitude, leading to an increase in power consumption.

  In order to compensate for the loss of the gate voltage Vgs due to the mobility correction described above, the present invention adds a coupling capacitor Cc to each pixel circuit. FIG. 7 is a schematic diagram for explaining the operation of the coupling capacitor Cc. This coupling capacitance Cc is a loss ΔV of the input voltage caused by negative feedback of the output current Ids extracted from the drive transistor Trd when the influence of the carrier mobility μ is removed from the input voltage (gate voltage Vgs) applied to the drive transistor Trd. In order to compensate for this, an additional amount Vb with respect to the input voltage Vgs is previously added to the pixel capacitance Cs by gate coupling of one of the switching transistors. In the illustrated example, the coupling capacitor Cc is connected between the source S of the drive transistor Trd and the gate of the switching transistor Tr2, and gate coupling that occurs when the control signal AZ1 supplied from the scanning line AZ1 is released. Thus, an addition Vb with respect to the input voltage Vgs is added to the pixel capacitor Cs.

Assuming that the gate voltage variation due to switching off of the switching transistor Tr2 is Va, the above-described coupling amount Vb is given by the following equation.
Vb = Va * Cc / (Cc + Coled)
Assuming that Va = −20V, Cc = 500fF, and Coled = 2500fF, the coupling component Vb = −20 × 500/3000 = −3.3V. Therefore, it is possible to compensate by the gate coupling of the switching transistor Tr2 by the amplitude of the signal voltage Vsig of 3.3V. As described above, according to the present invention, the mobility correction amount ΔV can be compensated only by adding the coupling capacitor Cc to the pixel circuit 2, and it is not necessary to increase the signal amplitude accordingly, which contributes to the reduction in power consumption of the panel. I can do it.

  Further, as a by-product, it is possible to increase the storage capacity when the signal voltage Vsig is written, and an improvement in the write gain GW can be expected. The write gain GW when there is no coupling capacitance Cc is given by GW = 1− (Cs / (Cs + Coled)). On the other hand, when the coupling capacitance Cc is added, the write gain is expressed by GW = 1 − ((Cs / (Cs + Cc + Coled)), so that the increase of the write gain GW is expected by adding the coupling capacitance Cc. Also in this case, it is possible to further reduce the amplitude of the signal potential Vsig of the video signal, and further promote the reduction in power consumption.

  As described above, the image display apparatus according to the present invention basically includes the pixel array unit 1, the scanner unit, and the signal unit. The pixel array unit 1 includes a first scanning line WS, a second scanning line DS, a third scanning line AZ1 and a fourth scanning line AZ2 arranged in a row, a signal line SL arranged in a column, and these scans. The pixel circuit 2 has a matrix shape connected to the line and the signal line, and a plurality of power supply lines for supplying the first potential Vss1, the second potential Vss2, and the third potential Vcc necessary for the operation of each pixel circuit 2. The signal unit 3 supplies a video signal to the signal line SL. The scanner unit supplies the control signals WS, DS, AZ1, and AZ2 to the first scanning line WS, the second scanning line DS, the third scanning line AZ1, and the fourth scanning line AZ2, and sequentially scans the pixel circuit 2 for each row. To do. Each pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a pixel capacitor Cs, a coupling capacitor Cc, and a light emitting element EL. Including. The sampling transistor Tr1 conducts in response to the control signal WS supplied from the first scanning line WS during a predetermined sampling period T5-T7, and samples the signal potential Vsig of the video signal supplied from the signal line SL into the pixel capacitor Cs. . The pixel capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the sampled video signal potential Vsig. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential Vsig of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period T7-T8.

  The first switching transistor Tr2 conducts according to the control signal AZ1 supplied from the second scanning line AZ1 at the timing T22 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vss1. Prior to sampling feedback, the second switching transistor Tr3 conducts in response to the control signal AZ2 supplied from the third scanning line AZ2 at timing T21, and sets the source S of the drive transistor Trd to the second potential Vss2. The third switching transistor Tr4 conducts according to the control signal DS supplied from the fourth scanning line DS at the timing T3 prior to the sampling period, and connects the drive transistor Trd to the third potential Vcc. A voltage corresponding to the threshold voltage Vth is held in the pixel capacitor Cs to correct the influence of the threshold voltage Vth. The third switching transistor Tr4 is turned on again at timing T6 within the sampling period, connects the drive transistor Trd to the third potential Vcc, and extracts the output current Ids from the drive transistor Trd while the signal potential Vsig is being sampled. This is negatively fed back to the pixel capacitor Cs to eliminate the influence of the carrier mobility μ of the drive transistor Trd from the input voltage Vgs. Further, the third switching transistor Tr4 maintains a conduction state during the light emission period following the sampling period, and allows the output current Ids to flow through the light emitting element EL.

  The coupling capacitor Cc compensates for the input voltage loss ΔV caused by the negative feedback of the output current Ids extracted from the drive transistor Trd when removing the influence of the carrier mobility μ of the drive transistor Trd from the input voltage Vgs. The added amount Vb with respect to Vgs is added to the pixel capacitor Cs at timing T4a by gate coupling of the switching transistor Tr2. That is, the added amount Vb with respect to the input voltage Vgs is added to the pixel capacitance Cs by gate coupling that occurs when the control signal AZ1 supplied from the second scanning line AZ1 is canceled.

1 is a block diagram showing an overall configuration of an image display device according to the present invention. It is a circuit diagram which shows the pixel structure of the image display apparatus concerning this invention. It is a schematic diagram with which operation | movement description of the image display apparatus concerning this invention is used. 6 is a timing chart for explaining the operation. It is a circuit diagram similarly used for operation | movement description. It is a graph similarly provided for operation | movement description. FIG. 6 is a schematic circuit diagram for explaining the operation in the same manner.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel circuit, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 71 ... 1st correction scanner, 72 ... Second correction scanner, Tr1... Sampling transistor, Tr2... First switching transistor, Tr3... Second switching transistor, Tr4... Third switching transistor, Trd. Pixel capacitance, Cc: coupling capacitance, EL: light emitting element, Vss1 ... first power supply potential, Vss2 ... second power supply potential, Vcc ... third power supply potential, WS ... first 1 scanning line, AZ1... Second scanning line, AZ2... Third scanning line, DS.

Claims (2)

A pixel array unit, a scanner unit, and a signal unit;
The pixel array unit includes a first scanning line, a second scanning line, a third scanning line, and a fourth scanning line arranged in a row, a signal line arranged in a column, and the scanning line and the signal line. The connected matrix pixel circuit and a plurality of power supply lines for supplying the first potential, the second potential and the third potential necessary for the operation of each pixel circuit,
The signal unit supplies a video signal to the signal line,
The scanner unit supplies a control signal to the first scanning line, the second scanning line, the third scanning line, and the fourth scanning line to sequentially scan the pixel circuit for each row,
Each pixel circuit includes a sampling transistor, a drive transistor, a first switching transistor, a second switching transistor, a third switching transistor, a pixel capacitor, and a light emitting element.
The sampling transistor conducts according to a control signal supplied from the first scanning line during a predetermined sampling period and samples the signal potential of the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the signal potential of the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element,
The light emitting element emits light with a luminance corresponding to the signal potential of the video signal by an output current supplied from the drive transistor during a predetermined light emitting period,
The first switching transistor is turned on in response to a control signal supplied from the second scanning line prior to the sampling period to set the gate of the drive transistor to the first potential,
The second switching transistor conducts according to a control signal supplied from the third scanning line prior to the sampling period, and sets the source of the drive transistor to the second potential,
The third switching transistor is turned on in response to a control signal supplied from the fourth scanning line prior to the sampling period to connect the drive transistor to the third potential, and thus corresponds to the threshold voltage of the drive transistor. Correct the influence of the threshold voltage by holding the voltage in the pixel capacitance,
The third switching transistor is turned on again during the sampling period to connect the drive transistor to a third potential, and takes out an output current from the drive transistor while the signal potential is being sampled. To negatively influence the carrier mobility of the drive transistor from the input voltage,
The third switching transistor maintains a conductive state during a light emission period subsequent to the sampling period and allows the output current to flow through the light emitting element.
When removing the influence of the carrier mobility of the drive transistor from the input voltage, in order to compensate for the loss of the input voltage caused by the negative feedback of the output current extracted from the drive transistor, any one of the additions to the input voltage is switched in advance An image display device comprising a coupling capacitor added to the pixel capacitor by gate coupling of a transistor. The coupling capacitor is connected between the source of the drive transistor and the gate of the first switching transistor, and the input voltage is generated by gate coupling generated when the control signal supplied from the second scan line is released. The image display apparatus according to claim 1, wherein an additional amount for the is added to the pixel capacity.

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