JP2003244697A - Information processing device and method, recording medium and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a reproduced image from being disturbed even when synchronous systems are changed. <P>SOLUTION: When a transmission system is reproduced, a coefficient k of an amplifier 22 is defined as a prescribed value of zero or more. In this case, a PLL is performed at the speed of response corresponding to the magnitude of the coefficient k, and a reference clock synchronizing with a clock at encoding is outputted. When a storage system is reproduced, the coefficient is defined as a value zero. In this case, a reference clock of a default frequency of a VCXO 25 is outputted from a PLL circuit 13. Since the reference clocks in the transmission system reproduction and the storage system reproduction in the present invention are generated from a clock of one VCXO 25 in either case, the continuity of a reference clock and a synchronizing signal is maintained even when a reproduction mode is changed and synchronous systems are switched. Thus, the image without any disturbance can be displayed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, a recording medium, and a program, and in particular, an information processing apparatus capable of outputting a proper reproduced image even when the reproduction mode is changed. And a method, a recording medium, and a program.

[0002]

2. Description of the Related Art When a transmitted MPEG transport stream is reproduced in real time, on the decoding side, synchronization is established based on a reference clock synchronized with the clock on the encoding side, and various reproduction processes are executed. That is, in this case, the decoding side needs a synchronization system (hereinafter referred to as a transmission system synchronization system) for adjusting its own clock to the encoding side clock.

In the following, reproduction using the transmission system synchronization system will be appropriately referred to as transmission system reproduction.

On the other hand, when reproducing, for example, an MPEG transport stream or an MPEG program stream recorded on a recording medium, the decoding side usually synchronizes based on a fixed frequency reference clock generated by a crystal oscillator. Establish and execute various playback processes. That is, in this case, the decoding side needs a self-contained synchronization system (hereinafter referred to as a storage synchronization system).

In the following, reproduction using the storage system synchronization system will be appropriately referred to as storage system reproduction.

[0006]

By the way, a reproducing apparatus which can perform both transmission system reproduction and storage system reproduction is
Normally, a transmission system synchronization system and a storage system synchronization system are prepared independently.

However, in such a case, when the reproduction mode is switched from the transmission system reproduction to the storage system reproduction or from the storage system reproduction to the transmission system reproduction, the synchronization system is also switched. was there.

It has been proposed to mute the video and audio output to blacken the screen at a timing when the synchronization is disturbed so that a disturbed image is not displayed, but the proper reproduced image is not displayed in the end. Absent.

The present invention has been made in view of such a situation, and it is possible to prevent the reproduced image from being disturbed when the reproduction mode is switched.

[0010]

The information processing apparatus of the present invention, when decoding the encoded first video data,
Fixing means for fixing the frequency of the clock output from the oscillator to a predetermined frequency, and decoding the first video data based on the clock of the predetermined frequency fixed by the fixing means, output from the oscillator 1 decryption means,
When decoding the encoded second video data, the second video
Based on the time information added to the video data of
It is provided with a changing means for changing the frequency of the clock of the oscillator and a second decoding means for decoding the second video data based on the clock of the frequency outputted from the oscillator and changed by the changing means. And

Storage means for storing the first video data and reception means for receiving the second video data are further provided, and the first decoding means stores the first video data stored in the storage means. Is decrypted, and the second decryption means
The second video data received by the receiving means can be decoded in real time.

The oscillator is a voltage controlled crystal oscillator, and
Video data is MPEG transport stream, MP
The EG program stream or ATRAC data, the second video data is an MPEG transport stream, the time information is PCR, and the changing means is an oscillator so that the clock based on the time information and the clock of the oscillator are synchronized. The frequency can be changed.

The changing means uses the second video data as the second video data.
When the input of the MPEG transport stream is switched and the PCR as time information becomes discontinuous, and the clock based on the time information and the clock of the oscillator are out of synchronization,
The frequency of the oscillator clock can be changed within the range in which the chroma subcarrier of the NTSC / PAL encoder shakes and the hue does not rotate.

The first decoding means generates a first signal processing clock based on the clock of a predetermined frequency fixed by the fixing means, which is output from the oscillator, and at the same time, performs the first signal processing clock. A first synchronizing signal can be generated based on the clock, the first video data can be decoded based on the first signal processing clock and the first synchronizing signal, and the second decoding means can: The clock for the second signal processing is generated based on the clock of the frequency changed by the changing means, which is output from the oscillator, and
The second synchronization signal can be generated based on the second signal processing clock, and the second video data can be decoded based on the second signal processing clock and the second synchronization signal.

A generating means for generating a third synchronizing signal on the basis of a clock of a predetermined frequency fixed by the fixing means, which is output from the oscillator, is further provided, and the first decoding means has the first signal processing. For decoding the first video data on the basis of the clock for clock, and the first synchronization signal synchronized with the third synchronization signal, and the first synchronization signal synchronized with the third synchronization signal, and the third synchronization signal. The format of the decoded first video data is converted based on the fourth synchronization signal which is synchronized with the synchronization signal, and the second decoding means
A second synchronization signal that decodes the second video data based on the second signal processing clock and the second synchronization signal that synchronizes with the third synchronization signal, and that synchronizes with the third synchronization signal. , And a fifth sync signal that is synchronized with the third sync signal, the format of the decoded second video data can be converted.

The fixing means fixes the frequency of the clock output from the oscillator to a predetermined frequency when the third video data to which the sixth synchronizing signal is added is input, and fixes the sixth synchronizing signal. , And the third signal processing clock generated based on the sixth synchronization signal, instead of the first
It is possible to change the synchronization of the third video data and output the third video data in accordance with the synchronization signal and the clock for the first signal processing.

According to the information processing method of the present invention, when decoding the encoded first video data, a fixed step of fixing the frequency of the clock output from the oscillator to a predetermined frequency, and the output from the oscillator. , The first based on the clock of the predetermined frequency fixed in the fixed step processing,
The first decoding step of decoding the video data of the above, and when decoding the encoded second video data, change the frequency of the clock of the oscillator based on the time information added to the second video data. And a second decoding step of decoding the second video data based on the clock having the frequency changed by the processing of the changing step, which is output from the oscillator.

The program of the recording medium of the present invention has a fixed control step of controlling the frequency of the clock output from the oscillator to be fixed to a predetermined frequency when decoding the encoded first video data. And a first decoding control step for controlling decoding of the first video data based on a clock of a predetermined frequency fixed by the processing of the fixed control step, which is output from the oscillator, and a second encoded control step. When decoding the video data, it is changed by the processing of the change control step for controlling the change of the frequency of the clock of the oscillator based on the time information added to the second video data and the processing of the change control step output from the oscillator. A second decoding control step of controlling decoding of the second video data based on the clock of the generated frequency.

The program of the present invention is the first encoded
When decoding the video data of, a fixed control step for controlling the frequency of the clock output from the oscillator to be fixed to a predetermined frequency, and the output from the oscillator.
A first decoding control step for controlling decoding of the first video data based on a clock of a predetermined frequency fixed by the processing of the fixed control step, and a first decoding control step for decoding the encoded second video data, A change control step for controlling a change in the frequency of the clock of the oscillator based on the time information added to the video data of 2, and a clock output from the oscillator and having a frequency changed in the process of the change control step, And a second decoding control step for controlling decoding of the second video data.

In the information processing apparatus, method and program of the present invention, when decoding the encoded first video data, the frequency of the clock output from the oscillator is fixed to a predetermined frequency and output from the oscillator. Will be
When the first video data is decoded based on the fixed clock having the predetermined frequency and the encoded second video data is decoded, based on the time information added to the second video data The frequency of the oscillator clock is changed, and the second video data is decoded based on the changed frequency clock output from the oscillator.

[0021]

1 shows an example of the structure of a recording / reproducing apparatus to which the present invention is applied.

The BS / CS digital tuner 1 is a broadcasting satellite or a communication satellite.
MPEG Digital Transport Stream encoded by the Moving Picture Experts Group (MPEG) 2 standard of the selected channel after receiving and demodulating digital television broadcasting transmitted via Is supplied to the selector 5.

The terrestrial digital tuner 2 demodulates the received terrestrial wave and supplies the MPEG transport stream of the selected channel to the selector 5.

The Ethernet (registered trademark) / wireless LAN interface 3 is an Ethernet (registered trademark) or wireless LAN.
The MPEG transport stream received from the LAN is supplied to the selector 5. IEEE1394 interface 4 is IE
The MPEG transport stream received via the EE1394 network is supplied to the selector 5.

The selector 5 is a BS / CS digital tuner 1
If the MPEG transport stream input from the IEEE 1394 interface 4 is recorded on a recording medium (not shown), the MPEG transport stream to be recorded is selected and supplied to the buffer controller 6.

The selector 5 is a BS / CS digital tuner 1
To When the MPEG transport stream input from the IEEE1394 interface 4 is reproduced in real time (when the transmission system is reproduced), the MPEG transport stream to be reproduced is selected and supplied to the demultiplexer 8.

The selector 5 sends the MPEG transport stream supplied from the buffer controller 6 to the demultiplexer 8 when reproducing the data (for example, the MPEG transport stream) recorded on the recording medium (when reproducing the storage system). Supply.

At the time of recording, the buffer controller 6 uses a built-in FIFO memory to store a low-speed continuous MPEG transport stream input from the selector 5 into a recording medium (for example, HDD, optical disk, magnetic disk). , Or a solid-state memory) at a transfer rate and timing (for example, a non-linear recording medium is intermittently output at high speed if the recording medium is a non-linear recording medium) and is recorded on the recording medium.

At the time of reproduction, the buffer controller 6 stores, in the FIFO memory, the MPEG transport stream read and supplied from the recording medium by the storage device 7 intermittently at high speed, and smoothes it. The obtained low-speed continuous MPEG transport stream is supplied to the selector 5.

The demultiplexer 8 receives the PES (Pack) from the MPEG transport stream supplied from the selector 5.
etized Elementary Stream) packet extraction and MPEG AV
It is supplied to the decoder 9.

The demultiplexer 8 also receives a PCR (Program Clock Reference) from the MPEG transport stream.
Is extracted and supplied to a PLL (Phase Lock Loop) circuit 13.

The MPEG AV decoder 9 establishes frame synchronization by using the synchronization signal supplied from the synchronization signal generation circuit 17, and from the PES packet input from the demultiplexer 8, the video elementary stream and the audio elementary stream. To generate.

The MPEG AV decoder 9 decodes the video elementary stream in accordance with a video signal processing clock supplied from the PLL circuit 15, and post-video signal processing the resulting video data (baseband digital signal). Supply to the circuit 10.

The MPEG AV decoder 9 also decodes the audio elementary stream in accordance with the audio signal processing clock supplied from the PLL circuit 16, and outputs the audio data (baseband digital signal) obtained as a result of the D / D conversion.
It is supplied to the A conversion circuit 12.

The post video signal processing circuit 10 establishes frame synchronization by using the sync signal supplied from the sync signal generation circuit 17, and performs digital effect processing and noise on the video data input from the MPEG AV decoder 9. Filtering processing, or OSD (On Screen Display) or 2D or 3D graphic creation and synthesis processing is performed according to the video signal processing clock supplied from the PLL circuit 15.

The post video signal processing circuit 10 also sends an SD (Standard Definition) signal to an HD (High Definition) if necessary.
(inition) signal is up-converted and HD signal is down-converted to SD signal.
The post video signal processing circuit 10 further performs not only conversion between SD and HD but also format conversion between different video formats (for example, 1080I and 720P of HD) among signals called HD and SD. For example, enlargement, reduction, IP
(Interlace / progressive) conversion and the like.

The post video signal processing circuit 10 supplies the signal obtained by performing various processes to the D / A conversion circuit 11.

The D / A conversion circuit 11 is the synchronization signal generation circuit 1
Establish synchronization by using the synchronization signal supplied from 7.
According to the video signal processing clock supplied from the L circuit 15, the input digital video signal (digital component signal) is D / A converted, and the resulting analog component video signal is output to an external device. .

The D / A conversion circuit 11 also functions as an NTSC encoder to encode a digital component signal to generate a YC digital signal and D / A convert it to obtain an analog composite video signal obtained as a result. The S video signal can also be output to an external device.

The D / A conversion circuit 12 receives the MPEG signal in accordance with the audio signal processing clock supplied from the PLL circuit 16.
The digital audio signal input from the AV decoder 9 is converted into an analog stereo audio signal and output to an external device.

The PLL circuit 13 is a BS / CS digital tuner 1
To the built-in V based on the PCR supplied from the demultiplexer 8 when the MPEG transport stream input from the IEEE1394 interface 4 is reproduced in the transmission system.
PLL is applied to the clock of the CXO (voltage control crystal) 25 (Fig. 2) to generate a clock synchronized with the clock (27MHz) at the time of encoding the MPEG transport stream,
It is supplied to each of the MPEG AV decoder 9, the PLL circuit 15, and the PLL circuit 16 by using it as a reference clock.

The PLL circuit 13 also uses the default frequency clock of the VCXO 25 as the reference clock when the MPEG transport stream recorded on the recording medium is reproduced, that is, when the accumulation system reproduction is performed. It is supplied to each of the decoder 9, the PLL circuit 15, and the PLL circuit 16.

The process of switching the reference clock of the PLL circuit 13 is controlled by the system controller 14,
The details will be described later.

The system controller 14 is a ROM (Read Only Memor) connected via a host bus (not shown).
y) or RAM (Random Access Memory),
Besides the PLL circuit 13, it controls the entire recording / reproducing apparatus.

The PLL circuit 15 synchronizes with the reference clock supplied from the PLL circuit 13 by the PLL and, for example, 1125i of HD.
Generates a 74.18MHz clock required for 29.97Hz playback processing, and uses it as a clock for video signal processing.
The V decoder 9, the post video signal processing circuit 10, the D / A conversion circuit 11, and the synchronization signal generation circuit 17 are supplied at predetermined timings.

The PLL circuit 16 synchronizes the reference clock supplied from the PLL circuit 13 with the PLL to generate a clock of 12.288 MHz (256xFs) of 48 KHz sampling,
MPEG A as a clock for audio signal processing
It is supplied to each of the V decoder 9 and the D / A conversion circuit 12 at a predetermined timing.

The sync signal generator 17 uses the clock supplied from the PLL circuit 15 to generate a sync signal in a free-running cycle, and the MPEG AV decoder 9 and the post video signal processing circuit 1 are generated.
0 and the D / A conversion circuit 11 are supplied at a predetermined timing.

FIG. 2 shows a configuration example of the PLL circuit 13.

PCR supplied from the demultiplexer 8
Are supplied to the subtractor 21. The subtractor 21 uses the PCR
From, the count value of the STC (System Time Clock) 26 counted at the timing when the packet in which the PCR is incorporated is detected is subtracted, and the subtraction result is supplied to the amplifier 22.

The amplifier 22 multiplies the data from the subtractor 21 by the coefficient k and supplies the resulting data to the D / A conversion circuit 23. The value of the coefficient k is changed by the system controller 14 in accordance with the reproduction mode (in accordance with the transmission system reproduction or the storage system reproduction) (described later).

The D / A conversion circuit 23 converts the data from the amplifier 22 into an analog signal (voltage) and outputs it to the LPF 24. LPF 24 is a signal (voltage) from the D / A conversion circuit 23
The high-frequency component of is removed, and the resulting signal is VCXO2
Supply to 5.

The VCXO 25 changes the default frequency of the clock (27 MHz) according to the voltage from the LPF 24, and supplies the clock of that frequency to the STC 26, the MPEG AV decoder 9, the PLL circuit 15 and the PLL circuit 16. .

The STC 26 is a counter (self-running time) for counting the output clock of the VCXO 25, and supplies the count value to the subtractor 21 as appropriate.

For example, when the count value of the STC 26 is smaller than PCR (when the clock of the VCXO 25 is later than the clock on the encoding side (PCR clock)), the output of the subtracter 21 becomes positive and the VCXO 25 has a coefficient k. Is added, the VCXO 25 outputs a clock having a frequency higher than the default frequency by the applied positive voltage.

On the other hand, when the count value of the STC 26 is larger than PCR (when the clock of the VCXO 25 is faster than the PCR clock), the output of the subtractor 21 becomes negative and the VCXO 25
, A negative voltage corresponding to the coefficient k is applied, and thus the VCXO 25 outputs a clock having a frequency lower than the default frequency by the applied negative voltage.

When the count value of STC 26 is equal to PCR,
The output of the subtracter 21 becomes 0, and no voltage is applied to the VCXO 25, so the VCXO 25 outputs a clock having a default frequency.

In this way, a clock synchronized with the PCR clock is generated.

The count value of the STC 26 is initialized by the PCR first input from the demultiplexer 8 after the system controller 14 starts the reproduction process or after changing the reproduction mode.

The system controller 14 changes the value of the coefficient k of the amplifier 22 according to the reproduction mode as described above. Specifically, for example, when reproducing the transmission system, the coefficient k is set to a predetermined value larger than 0. Value of. That is, in this case, the PLL circuit 13 performs PLL at a response speed according to the magnitude of the coefficient k, and a clock synchronized with the encoding clock (PCR clock) is output as the reference clock.

Since the loopback gain of the PLL is based on the coefficient k, the larger the coefficient k, the faster the response,
If the coefficient k is small, the response becomes slow. Therefore, the coefficient k at this time is set to the NTSC / PAL encoder as the final output even when the PCR becomes discontinuous due to the switching or loss of the MPEG transport stream stream input and the PLL is unlocked. It is possible to make the size such that the chroma sub-carrier of (3) does not shake and the hue does not rotate.

On the other hand, at the time of reproducing the storage system, the system controller 14 sets the coefficient k to the value 0. That is, in this case, the PLL is not actually performed, and the VCXO 25
The clock having the default frequency of is output as the reference clock.

Therefore, in the present invention, a synchronizing signal, a video signal processing clock, and an audio signal processing clock are generated from the clock (reference clock) from the PLL circuit 13 and the reproduction processing is performed based on them. Therefore, only by changing the value of the coefficient k and changing the reference clock, the transmission system reproduction or the storage system reproduction can be appropriately executed.

In either case of the reproduction of the transmission system and the reproduction of the storage system, the reference clock is one VCXO 25.
Since it is generated from the clock, the continuity of the reference clock can be maintained even if the reference clock is changed according to the change of the reproduction mode. As a result, the continuity of the synchronization signal, the clock for video signal processing, and the clock for audio signal processing is maintained, and the synchronization in the processing of the MPEG AV decoder 9 to the D / A conversion circuit 12 is not disturbed. Even when changing, it is possible to display an image without distortion.

Next, the operation of the system controller 14 when changing the reference clock according to the reproduction mode will be described with reference to the flowchart of FIG.

In step S1, the system controller 14 determines whether the transmission system reproduction is requested or the storage system reproduction is requested. When it is determined that the transmission system reproduction is requested, the system controller 14 proceeds to step S2. That is, when the reproduction start is requested but the reproduction is the transmission system reproduction, or when the accumulation system reproduction is performed but the reproduction mode is switched to the transmission system reproduction, the process proceeds to step S2.

In step S2, the system controller 14 determines whether or not the PCR supplied from the demultiplexer 8 to the PLL circuit 13 is the first PCR after the reproduction is started or the reproduction mode is changed. If it is determined that there is, the process proceeds to step S3.

In step S3, the system controller 14 initializes the count value of the STC 26 of the PLL circuit 13 to the first PCR and sets the coefficient k of the amplifier 22 to the value 0. That is, at this time, PLL is not substantially performed in the PLL circuit 13, and the VCXO 25
The clock of the default frequency of is output as the reference clock.

Then, the process returns to step S1 and the subsequent processes are executed.

When it is determined in step S2 that the PCR is not the first PCR, the system controller 14 proceeds to step S4. When the PCR after the first PCR is input, the process proceeds to step S4.

In step S4, the system controller 14 sets the coefficient k of the amplifier 22 of the PLL circuit 13 to a value of a predetermined magnitude. As a result, the PLL control is performed at the response speed according to the magnitude of the coefficient k, and the PLL circuit 13 outputs the clock synchronized with the encoding clock as the reference clock.

That is, at this time, the MPEG AV decoder 9 to the D / A conversion circuit 12 are arranged so that the MPEG AV decoder 9 to the D / A conversion circuit 12 generate a synchronizing signal generated on the basis of a reference clock synchronized with the encoding clock, a video signal processing clock, and an audio signal processing. Since the processing is executed in accordance with the clock for transmission, the reproduction of the transmission system is properly performed.

Then, the process returns to step S1 and the subsequent processes are executed.

If it is determined in step S1 that the reproduction of the storage system is requested, the process proceeds to step S5. That is, when the reproduction start is requested but the reproduction is the storage system reproduction, or when the reproduction mode is switched from the transmission system reproduction to the storage system reproduction, the process proceeds to step S5.

In step S5, the system controller 14 sets the coefficient k of the amplifier 22 of the PLL circuit 13 to 0.
To As a result, the PLL circuit 13 outputs the clock of the default frequency of the VCXO 25 as the reference clock.

That is, at this time, the MPEG AV decoders 9 to D / A 12 process according to the sync signal generated based on the reference clock of the default frequency of the VCXO 25, the video signal processing clock, and the audio signal processing clock. Therefore, the storage system is properly regenerated. In other words, the standard signal is reproduced and output with no clock fluctuation.

Then, the process returns to step S1 and the subsequent processes are executed.

FIG. 4 shows a structural example of another recording / reproducing apparatus to which the present invention is applied. This recording / reproducing apparatus can convert different image formats such as enlargement / reduction and IP conversion (interlace / progressive conversion) into a predetermined format and output it.

A PLL circuit 31 is further provided in this recording / reproducing apparatus, and instead of the synchronization signal generating circuit 17 of FIG.
A synchronization signal generation circuit 32 including a master synchronization signal generation circuit 41, a decoding synchronization signal generation circuit 42, and an output synchronization signal generation circuit 43 is provided. The other parts are the same as in the case of FIG. The BS / CS digital tuner 1 to the IEEE1394 interface 4 in FIG. 1 are not shown.

The PLL circuit 13 is a BS / CS digital tuner 1
To the built-in V based on the PCR supplied from the demultiplexer 8 when the MPEG transport stream input from the IEEE1394 interface 4 is reproduced in the transmission system.
PLL is applied to the clock of CXO25 (Fig. 2) to generate a clock that synchronizes with the encoding clock (27MHz) of the MPEG transport stream, and this is used as the reference clock.
It is supplied to the MPEG AV decoder 9, the PLL circuit 15, the PLL circuit 16, the PLL circuit 31, and the synchronization signal generation circuit 32 (master synchronization signal generation circuit 41).

The PLL circuit 13 also uses the default frequency clock of the VCXO 25 as a reference clock when the MPEG transport stream recorded on the recording medium is reproduced, that is, when the accumulation system reproduction is performed, and the MPEG AV Decoder 9, PLL circuit 15, PLL circuit 1
6, the PLL circuit 31, and the synchronization signal generation circuit 32 (master synchronization signal generation circuit 41).

The PLL circuit 15 synchronizes with the reference clock supplied from the PLL circuit 13 by the PLL, generates a clock suitable for the video format of the decoded video data, and uses it as a clock for video signal processing. The signals are supplied to the decoder 9, the input side of the post video signal processing circuit 10, and the synchronization signal generation circuit 32 (decoding synchronization signal generation circuit 42) at predetermined timings.

The PLL circuit 31 synchronizes the reference clock supplied from the PLL circuit 13 with the PLL to generate a clock suitable for the video format of the output video data, and uses the clock as a clock for video signal processing for post video. The signals are supplied to the output side of the signal processing circuit 10, the D / A conversion circuit 11, and the synchronization signal generation circuit 32 (output synchronization signal generation circuit 43) at predetermined timings.

The master synchronization signal generation circuit 41 of the synchronization signal generator 32 uses the reference clock supplied from the PLL circuit 13 to generate a master frame synchronization signal (for example, 29.97 Hz) in a free-running cycle for decoding. Sync signal generation circuit 4
2 and the output synchronizing signal generating circuit 43.

The decoding synchronization signal generating circuit 42 uses the clock supplied from the PLL circuit 15 to generate a decoding synchronization signal in a free-running cycle, and also uses the master frame synchronization signal from the master synchronization signal generating circuit 41. By resetting, a decoding synchronizing signal that is synchronized with the master frame synchronizing signal is generated, and this is supplied to the MPEG AV decoder 9 and the post video signal processing circuit 10.

The output synchronization signal generation circuit 43 uses the clock supplied from the PLL circuit 31 to generate an output synchronization signal in a free-running cycle, and uses the master frame synchronization signal from the master synchronization signal generation circuit 41. By resetting, an output synchronizing signal which is synchronized with the master frame synchronizing signal is generated and is supplied to the post video signal processing circuit 10 and the D / A conversion circuit 11.

The post video signal processing circuit 10 is an MPEG AV
The decoded video data from the decoder 9 is written in the built-in frame memory by using the decoding sync signal, and is read by using the output sync signal.
When this writing or reading is performed, the video data from the MPEG AV decoder 9 is converted into a predetermined format (enlargement, reduction, or IP conversion (interlace / progressive conversion) processing is performed). Note that the write (input side) and read (output side) sync signals of the memory must be synchronized in the same phase because this format conversion image processing of the moving image facilitates memory bank control.
This is to prevent overtaking of reading.

As described above, the decoding sync signal and the output sync signal are synchronized with the master frame sync signal created by the PLL from the reference clock, and the final output video format is unified. Therefore, even if the format of the video data to be played back is switched to another video format, the continuity of the synchronization signal and the clock can be maintained, and the video can be played back properly.

FIG. 5 shows a configuration example of another recording / reproducing apparatus to which the present invention is applied.

This recording / reproducing apparatus includes a PLL circuit 1 shown in FIG.
5, the PLL circuit 16 and the synchronization signal generating circuit 17 are removed, and an MPEG AV decoder 51 and a post video signal processing circuit (Post / OSD) 52 are provided in place of the MPEG AV decoder 9 and the post video signal processing circuit 10. ing.

The MPEG AV decoder 51 is the PLL circuit 1 of FIG.
5, a PLL is used to synchronize with the reference clock supplied from the PLL circuit 13 to generate a clock for video signal processing, and the clock is processed through the post video signal processing circuit 52 and the post video signal processing circuit 52. It is supplied to the D / A conversion circuit 11. The MPEG AV decoder 51 also includes the PLL circuit 1 shown in FIG.
6, the PLL is used to synchronize with the reference clock from the PLL circuit 13 to generate a clock for audio signal processing,
It is supplied to the D / A conversion circuit 12.

Further, the MPEG AV decoder 51, like the sync signal generation circuit 17 of FIG. 1, uses a clock for video signal processing to generate a sync signal by free running, and outputs it to the post video signal processing circuit 52. And to the D / A conversion circuit 11 via the post video signal processing circuit 52.

The MPEG AV decoder 51, like the MPEG AV decoder 9 in FIG. 1, decodes the video elementary stream supplied from the demultiplexer 8 according to the clock for video signal processing, and the video data obtained as a result. The (baseband digital signal) is supplied to the post video signal processing circuit 52.

Like the MPEG AV decoder 9, the MPEG AV decoder 51 also decodes the audio elementary stream supplied from the demultiplexer 8 according to the clock for audio signal processing, and outputs the resulting audio data (base The digital signal of the band) is supplied to the D / A conversion circuit 12.

In order to construct a system that executes processing in accordance with a single synchronization signal, the operating device needs to be a slave, but there are devices in the AV decoder that can only be masters. So MPEG AV
Like the decoder 51, the present invention can be used by making it a master of a synchronization signal.

The post video signal processing circuit 52 has basically the same function as that of the post video signal processing circuit 10 of FIG. 1, but for processing the synchronizing signal and the video signal supplied from the MPEG AV decoder 51. The clock can be relayed to the D / A conversion circuit 11. In addition, gl for the sync signal
By not providing the ue circuit, a simpler connection is possible, and by using an interface such as CCIR656 in which a sync signal is embedded in digital data, the connection can be made easier. Can be

As in the case of FIG. 1, the system controller 14 changes the value of the coefficient k of the amplifier 22 of the PLL circuit 13 according to the reproduction mode, and the PLL circuit 13 uses the reference clock based on the coefficient k. It is designed to output.

FIG. 6 shows another configuration example of the recording / reproducing apparatus to which the present invention is applied.

In this recording / reproducing apparatus, a DVD AV decoder 61 and a selector 62 are further provided in the recording / reproducing apparatus of FIG. That is, this recording / reproducing apparatus is a DVD
The video (MPEG program stream) recorded in can be further reproduced. Note that the reproduction of the MPEG program stream is a storage system reproduction.

To the DVD AV decoder 61, an MPEG program stream of the DVD video format recorded on the DVD (not shown) is appropriately supplied from the selector 5 when the DVD is reproduced.

The DVD AV decoder 61 is also supplied with the sync signal generated by the MPEG AV decoder 51 through the selector 62, and the clock for audio signal processing and the clock for video signal processing generated by the MPEG AV decoder 51. The clock is directly supplied.

That is, the DVD AV decoder 61 establishes frame synchronization in accordance with the synchronization signal from the MPEG AV decoder 51 during DVD reproduction and is supplied from the selector 5.
Demultiplexer processing for MPEG program stream, sub-picture decoding processing, Dolby Digital 5.
1CH decoding processing and the like are performed in accordance with the video signal processing clock and the audio signal processing clock from the MPEG AV decoder 51.

It should be noted that the synchronizing signal, the video signal processing clock, and the audio signal processing clock supplied to the DVD AV decoder 61 during DVD reproduction are VCXO2.
Reference clock with default frequency of 5 (PLL circuit 13
Clock when the coefficient k of the amplifier 22 of is set to 0)
It is generated based on.

The selector 62 selects the video elementary stream and the audio elementary stream supplied from the MPEG AV decoder 51 during the reproduction of the MPEG transport stream (in both the transmission system reproduction and the storage system reproduction). Together with supplying the video elementary stream to the post video signal processing circuit 52,
The audio elementary stream is supplied to the D / A conversion circuit 12.

At this time, the selector 62 selects the synchronizing signal and video signal processing clock supplied from the MPEG AV decoder 51 and the audio signal processing clock, and at the same time, selects the synchronizing signal and video signal processing clock. The signal is supplied to the D / A conversion circuit 11 via the post video signal processing circuit 52 and the post video signal processing circuit 52, and the clock for audio signal processing is supplied to the D / A conversion circuit 12.

The selector 62 is an MPE recorded on the DVD.
When the G program stream is reproduced, the video elementary stream and the audio elementary stream supplied from the DVD AV decoder 61 are selected and
The video elementary stream is supplied to the post video signal processing circuit 52, and the audio elementary stream is supplied to the D / A conversion circuit 12.

At this time, the selector 62 selects the synchronizing signal and video signal processing clock supplied from the MPEG AV decoder 51, and the audio signal processing clock, and also supplies the synchronizing signal to the DVD AV decoder 61. Clock for synchronizing signal and video signal processing,
The post-video signal processing circuit 52 and the D / A conversion circuit 11 are supplied via the post-video signal processing circuit 52, and the audio signal processing clock is supplied to the D / A conversion circuit 12.

The synchronizing signal is transmitted through the selector 62,
The reason why the DVD AV decoder 61 is supplied is that the selector 62 has a built-in Glue circuit for matching the interface of the synchronization signal.

As in the case of FIG. 5, the MPEG AV decoder 51 generates a video signal processing clock and an audio signal processing clock based on the reference clock from the PLL circuit 13, and selects the selector 62 and the DVD AV. Decoder 6
Supply to 1.

The MPEG AV decoder 51 uses the clock for video signal processing to generate a synchronization signal and supplies it to the selector 62.

The MPEG AV decoder 51 decodes the video elementary stream supplied from the demultiplexer 8 in accordance with the clock for video signal processing, and the resulting video data (baseband digital signal) is sent to the selector 62. The audio elementary stream supplied and decoded from the audio elementary stream supplied from the demultiplexer 8 is decoded in accordance with the audio signal processing clock, and the resulting audio data (baseband digital signal) is supplied to the selector 62.

In the case of this example, the MPEG AV decoder 51
Even when it is not operating as a decoder, it outputs a clock for video signal processing, a clock for audio signal processing, and a synchronization signal.

Also in this case, the synchronization signal, the video signal processing clock, and the audio signal clock necessary for DVD reproduction (accumulation system reproduction) are simply changed by changing the value of the coefficient k to change the reference clock. Is generated, DVD playback can be performed appropriately.

The reference clock for DVD reproduction is also the same as the reference clock for digital sanitary broadcast reproduction.
Since it is generated from the VCXO25 clock, the continuity of the reference clock is maintained even if the reference clock is changed according to the change of the playback mode from digital satellite broadcast playback to DVD playback or DVD playback to digital satellite broadcast playback. Can be kept. As a result, the continuity of the synchronization signal, the video signal processing clock, and the audio signal processing clock is maintained, and the MPEG AV decoder 9 to the D / A conversion circuit 12,
In addition, since the synchronization in the processing of the DVD AV decoder 61 and the selector 62 is not disturbed, it is possible to display an undisturbed image even when the reproduction mode is changed.

In the above, the recording / reproducing apparatus is
I explained the case where it has a function to play a DVD, but D
It can also have the function of playing back V (Digital Video Tape) and ATRAC format data.

FIG. 7 shows a structural example of another recording / reproducing apparatus to which the present invention is applied.

This recording / reproducing apparatus is the same as the recording / reproducing apparatus of FIG. 5 except that the terrestrial / BS analog tuner 71 to the selector 7 are used.
7 is provided.

The terrestrial / BS analog tuner 71 receives and demodulates the analog broadcast transmitted via the terrestrial or BS, and outputs the analog composite video signal of the selected channel to the A / D conversion circuit 72. Supply.

The A / D conversion circuit 72 is an analog composite video signal from the terrestrial / BS analog tuner 71.
Or select one of the separately input analog composite video signals from the external LINE, perform Y / C separation processing and A / D conversion on the selected analog composite video signals, and output digital component video signals. To generate.

The A / D conversion circuit 72 also separates the sync signal combined with the analog composite video signal, generates a clock (clock for video signal processing) based on the sync signal, and outputs the sync signal. And a clock for video signal processing to the frame synchronizer 7
Supply to 3.

That is, the A / D conversion circuit 72 has an NTSC
(National Television System Committee) Contains a demodulation circuit, a sync signal separation circuit, and a clock generation circuit.

The frame synchronizer 73 uses a built-in frame memory to synchronize the synchronization signal from the A / D conversion circuit 72 and the video signal processing clock from the MPEG AV decoder 51 supplied via the selector 77. Performs TBC (Time Base Corrector) processing by switching to the clock for signal and video signal processing. The clock for processing the synchronizing signal and the video signal supplied to the frame synchronizer 73 is the VCXO 25 of the PLL circuit 13.
Clock of the default frequency of (amplifier 22 coefficient k
Is generated according to the clock when the value is set to 0).

The sync signal combined with the analog composite video signal received by the terrestrial / BS analog tuner 71 and the video signal processing clock generated on the basis of the sync signal are used in the (MPEG
Since the synchronization signal and the clock for video signal processing (generated by the AV decoder 51) are asynchronous, it is necessary to perform the synchronous transfer processing in the frame synchronizer 73. In addition, the signal input from the external LINE may not be a so-called standard video signal, such as a video signal when the channel is switched, a video signal specially played for VHS video, or a video signal from a home video game console. In some cases, the synchronization is different from that of the standard video signal, and a lot of jitter is included. Therefore, it is effective to perform synchronous transfer processing with the TBC effect on the signal input from the external LINE.

The frame synchronizer 73 converts the TBC-processed digital component video signal into an MPEG AV signal.
It is supplied to the encoder 75 and the selector 77.

The A / D conversion circuit 74 selects one of the analog stereo signal from the terrestrial / BS analog tuner 71 or the analog stereo signal from the external LINE which is separately input, and selects the selected analog stereo signal. Is supplied from the selector 77 to the MPEG AV decoder 5
A / according to the clock for audio signal processing from 1
The D-converted digital serial audio signal obtained as a result is supplied to the MPEG AV encoder 75 and the selector 77.

Since the analog voice signal is a continuous signal without the concept of a sync signal, when the analog signal is A / D converted and digitized in this way, the audio generated by the PLL from the reference clock is used. By using the clock for signal processing, it is possible to easily achieve synchronization with the video signal.

The MPEG AV encoder 75 compresses and encodes the digital video signal and the digital audio signal into a video elementary stream and an audio elementary stream of the MPEG format, and supplies them to the multiplexer 76.

The multiplexer 76 multiplexes the video elementary stream and the audio elementary stream from the MPEG AV encoder 75 to generate an MPEG transport stream, and supplies it to the selector 5.

The MPEG transport stream from the multiplexer 76 supplied to the selector 5 is appropriately supplied to the buffer controller 6, and the storage device 7
Is recorded on the recording medium via.

The selector 77 selects the video elementary stream and the audio elementary stream supplied from the MPEG AV decoder 51 during the reproduction of the MPEG transport stream (in both the transmission system reproduction and the storage system reproduction). Together with supplying the video elementary stream to the post video signal processing circuit 52,
The audio elementary stream is supplied to the D / A conversion circuit 12.

At this time, the selector 77 selects the synchronizing signal and video signal processing clock supplied from the MPEG AV decoder 51 and the audio signal processing clock, and at the same time, selects the synchronizing signal and video signal processing clock. The signal is supplied to the D / A conversion circuit 11 via the post video signal processing circuit 52 and the post video signal processing circuit 52, and the clock for audio signal processing is supplied to the D / A conversion circuit 12.

The selector 77 selects the digital component video signal from the frame synchronizer 73 when the analog broadcast selected by the terrestrial / BS analog tuner 71 is reproduced by the transmission system, and the post video signal processing circuit 52 and the post video signal processing circuit 52. D / via the video signal processing circuit 52
The signal is supplied to the A conversion circuit 11, and the digital serial audio signal from the A / D conversion circuit 74 is supplied to the D / A conversion circuit 12.

At this time, the selector 77 selects the synchronizing signal and the clock for the video signal processing (the signal and the clock generated according to the clock of the default frequency of the VCXO 25) supplied from the MPEG AV decoder 51, and the post video signal processing. The clock for audio signal processing supplied from the MPEG AV decoder 51 is supplied to the D / A conversion circuit 11 via the circuit 52 and the post video signal processing circuit 52, and also supplied to the frame synchronizer 73 for D / A conversion. It is supplied to the circuit 12 and the A / D conversion circuit 74.

Since the D / A conversion circuit 12 and the A / D conversion circuit 74 are connected, the audio signal processing clock output from the selector 77 is supplied to both.

If the analog broadcast selected by the terrestrial / BS analog tuner 71 is recorded, the selector 77
Selects a sync signal and a clock for video signal processing (a signal and a clock generated according to a clock having a default frequency of the VCXO 25) supplied from the MPEG AV decoder 51, and supplies the selected clock to the frame synchronizer 73. The clock for audio signal processing supplied from the A / D conversion circuit 74 is supplied.

Note that the synchronizing signal, the clock for processing the video signal, and the clock for processing the audio signal are supplied to each section via the selector 77.
This is because the Glue circuit that incorporates the interfaces of the synchronization signal, the clock for video signal processing, and the clock for audio signal processing is built in.

As described above, in this case, the synchronization signal from the MPEG AV decoder 51 and the clock for processing the video signal are used to perform the TBC and the synchronous transfer processing for the input analog composite signal. Even if the playback mode is switched from playback of MPEG transport stream recorded in (playback of storage system) to playback of analog broadcast transmission system, the synchronization is not disturbed and the disturbed image does not appear (OSD screen also Stable display).

The series of processes described above can be realized by hardware, but can also be realized by software. When a series of processes is realized by software, a program that constitutes the software is installed in a computer, and the program is executed by the computer, so that the recording / reproducing apparatus described above is functionally realized.

FIG. 8 is a block diagram showing the configuration of an embodiment of the computer 101 which functions as the recording / reproducing apparatus as described above. CPU (Central Processing Unit)
I / O interface 111 to bus 111 via bus 115
16 is connected, and when the CPU 111 receives a command from the user through the input / output interface 116 and the input unit 118 including a keyboard and a mouse,
For example, a program stored in a recording medium such as the ROM 112, the hard disk 114, or the magnetic disk 131, the optical disk 132, the magneto-optical disk 133 mounted in the drive 120, or the semiconductor memory 134 is loaded into the RAM 113 and executed. As a result, the various processes described above are performed. Furthermore, the CPU 111
The processing result is, for example, input / output interface 116.
If necessary, the data is output to an output unit 117 including an LCD (Liquid Crystal Display) or the like. The program is stored in the hard disk 114 or the ROM 112 in advance and provided to the user integrally with the computer 101, or provided as a package medium such as the magnetic disk 131, the optical disk 132, the magneto-optical disk 133, and the semiconductor memory 134. Alternatively, it can be provided to the hard disk 114 via a communication unit 119 from a satellite, a network, or the like.

In the present specification, the steps for describing the program provided by the recording medium are not limited to the processing performed in time series according to the order described, but may not necessarily be performed in time series. It also includes processing executed in parallel or individually.

[0140]

According to the information processing apparatus, method and program of the present invention, when decoding the encoded first video data, the frequency of the clock output from the oscillator is fixed to a predetermined frequency, The first video data is decoded and encoded based on the clock of the fixed predetermined frequency output from the oscillator and its synchronizing signal, and the encoded second video data is decoded.
When decoding the video data of, the frequency of the clock of the oscillator is changed based on the time information added to the second video data, and the clock of the changed frequency and its synchronizing signal output from the oscillator are changed. Since the second video data is decoded based on the above, the reproduction of the first video data is changed to the reproduction of the second video data, or the reproduction of the second video data is changed to the reproduction of the first video data. Even when the reproduction mode is changed, a proper reproduced image can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a recording / reproducing apparatus to which the present invention is applied.

FIG. 2 is a diagram showing a configuration example of a PLL circuit 13 in FIG.

FIG. 3 is a flowchart showing a control procedure of a PLL circuit 13 of a system controller 14.

FIG. 4 is a block diagram showing another configuration example of a recording / reproducing apparatus to which the present invention has been applied.

FIG. 5 is a block diagram showing another configuration example of a recording / reproducing apparatus to which the present invention has been applied.

FIG. 6 is a block diagram showing another configuration example of a recording / reproducing apparatus to which the present invention has been applied.

FIG. 7 is a block diagram showing another configuration example of a recording / reproducing apparatus to which the present invention has been applied.

FIG. 8 is a block diagram showing a configuration example of a personal computer 101.

[Explanation of symbols]

1 BS / CS digital tuner, 2 terrestrial digital tuner, 3 Ethernet (registered trademark) / wireless LAN interface, 4 IEEE1394 interface, 5
Selector, 6 buffer controller, 7 storage device, 8 demultiplexer, 9 MPEG AV
Decoder, 10 Post video signal processing circuit, 11
D / A conversion circuit, 12 D / A conversion circuit, 13 PLL circuit, 14 system controller, 15 PLL circuit, 16 PLL circuit, 17 synchronization signal processing circuit,
21 subtractor, 22 amplifier, 23 D / A conversion circuit, 24 LPF, 25 VCXO, 26 STC, 51
MPEG AV decoder, 52 Post video signal processing circuit, 61 DVD AV decoder, 42 selector, 7
1 terrestrial / BS analog tuner, 72 A / D conversion circuit, 73 frame synchronizer, 74 A / D conversion circuit, 75 MPEG AV encoder, 76 multiplexer, 77 selector

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinya Tatsumi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 5C052 AB02 CC03 CC04 CC11 DD04                 5C059 KK00 MA00 PP04 RB10 RC03                       SS02 SS06 SS12 SS20 TA00                       TC47 UA05 UA09 UA32 UA39

Claims (10)

[Claims] 1. When decoding encoded first video data, the frequency of a clock output from an oscillator is
Based on a fixing means for fixing the frequency to a predetermined frequency and a clock output from the oscillator and having the predetermined frequency fixed by the fixing means, the first
And a frequency of a clock of the oscillator based on time information added to the second video data when decoding the encoded second video data. And a second decoding means for decoding the second video data based on the clock of the frequency changed by the changing means, which is output from the oscillator. Information processing device. 2. A storage unit for storing the first video data, and a reception unit for receiving the second video data, wherein the first decoding unit is stored in the storage unit. The information processing apparatus according to claim 1, wherein the first video data is decoded, and the second decoding means decodes the second video data received by the receiving means in real time. . 3. The oscillator is a voltage controlled crystal oscillator, the first video data is an MPEG transport stream, an MPEG program stream, or ATRAC data, and the second video data is an MPEG transport stream. A stream, the time information is PCR, and the changing unit changes the frequency of the oscillator so that a clock based on the time information and a clock of the oscillator are synchronized. The information processing device according to 1. 4. The changing means switches the input of the MPEG transport stream as the second video data to discontinue the PCR as the time information, and a clock and the oscillator based on the time information. The clock frequency of the oscillator is changed within a range in which the chroma subcarrier of the NTSC / PAL encoder shakes and the hue does not rotate when the clock is out of synchronization with the clock of the oscillator. apparatus. 5. The first decoding means generates a first signal processing clock based on the clock of the predetermined frequency fixed by the fixing means, which is output from the oscillator, and The first synchronization signal is generated based on a first signal processing clock, and the first video data is decoded based on the first signal processing clock and the first synchronization signal. The second decoding means generates a clock for second signal processing based on the clock of the frequency changed by the changing means, which is output from the oscillator, and also generates the second signal processing clock. A second synchronization signal is generated based on the clock, and the second video data is decoded based on the second signal processing clock and the second synchronization signal. The information processing apparatus according to claim 1. 6. The apparatus further comprises: generating means for generating a third synchronizing signal based on the clock of the predetermined frequency fixed by the fixing means, which is output from the oscillator, and the first decoding means The first video data is decoded based on the first signal processing clock and the first synchronization signal that is synchronized with the third synchronization signal, and is synchronized with the third synchronization signal. Converting the format of the decoded first video data based on the first sync signal and a fourth sync signal that is in synchronization with the third sync signal; The second video data is decoded on the basis of the second signal processing clock and the second synchronization signal synchronized with the third synchronization signal, and the second video data is synchronized with the third synchronization signal. 6. The information according to claim 5, wherein the format of the decoded second video data is converted based on a second synchronization signal and a fifth synchronization signal that is synchronized with the third synchronization signal. Processing equipment. 7. The fixing means fixes the frequency of the clock output from the oscillator to the predetermined frequency when inputting the third video data to which the sixth synchronization signal is added, The sixth synchronization signal, and the sixth
In place of the third signal processing clock generated based on the first synchronizing signal and the first signal processing clock, the synchronization of the third video data is changed and output. Claim 1 characterized by the above.
The information processing device according to 1. 8. The frequency of the clock output from the oscillator when decoding the encoded first video data is
A fixing step of fixing the predetermined frequency, and a first decoding step of decoding the first video data based on the clock of the predetermined frequency fixed by the processing of the fixing step, which is output from the oscillator. And a changing step of changing the frequency of the clock of the oscillator based on time information added to the second video data when decoding the encoded second video data, and outputting from the oscillator. The second clock based on the clock of the frequency changed in the process of the changing step.
And a second decoding step of decoding the video data of 1. 9. The frequency of the clock output from the oscillator when decoding the encoded first video data is
A fixed control step of controlling so as to be fixed to a predetermined frequency, and an output from the oscillator based on the clock of the predetermined frequency fixed in the processing of the fixed control step,
A first decoding control step of controlling decoding of the first video data; and a step of decoding the encoded second video data based on time information added to the second video data. A change control step of controlling a change in the frequency of the clock of the oscillator; and controlling decoding of the second video data based on the clock of the frequency output from the oscillator and changed in the processing of the change control step. A recording medium having a computer-readable program recorded thereon, comprising a second decoding control step. 10. A fixed control step of controlling the frequency of the clock output from the oscillator so as to be fixed to a predetermined frequency when decoding the encoded first video data, and the fixed control step output from the oscillator. Based on the clock of the predetermined frequency fixed in the process of the fixed control step,
A first decoding control step of controlling decoding of the first video data; and a step of decoding the encoded second video data based on time information added to the second video data. A change control step of controlling a change in the frequency of the clock of the oscillator; and controlling decoding of the second video data based on the clock of the frequency output from the oscillator and changed in the processing of the change control step. A program for causing a computer to execute a process including a second decoding control step.