JP2003163313A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be further miniaturized by minimizing a fillet around a semiconductor chip, and reduces restrictions in design, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: A semiconductor package is composed by fixing a semiconductor chip 100 to an insulating board 102 via die paste 104. The semiconductor chip 100 has a main front 112 where an electronic circuit is formed, and a back 114 bonded to the insulating board 102, and is composed so that the back 114 becomes smaller than the main front 112. By reducing the back 114 as compared with the main front 112, the squeezed out amount of the die paste around the semiconductor chip 100 can be reduced. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a semiconductor package and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high performance of electronic information devices, technological developments for further miniaturizing semiconductor devices such as semiconductor packages mounted therein have been actively conducted. C
SP (Chip Size Package) is a semiconductor package with a high density, which is equal to or slightly larger than the chip size. Like the conventional semiconductor package, this CSP has a structure in which the semiconductor chip is covered with a sealing material such as a resin, and thus has high reliability and is easy to handle.

FIG. 14 is a sectional view showing the basic structure of a general CSP type semiconductor package. In this semiconductor package, a semiconductor chip 1400 having an integrated circuit formed on its main surface (upper surface in the drawing) is fixed to an insulating substrate 1402 via a die paste 1404. Insulating substrate 14
A conductor lead 1406 is formed on the main surface of 02, and is connected to the solder bump 1408 through a through hole formed in the insulating substrate 1402. Semiconductor chip 1400
An electrode pad 1420 is formed on the main surface of the electrode pad 1420, and the electrode pad 1420 and the conductor lead 1406 are connected via a conductor wire 1410 by wire bonding. The semiconductor chip 1400 has a resin sealing material 14
It is sealed by 18.

[0004]

Here, in the step of adhering the semiconductor chip 1400 to the insulating substrate 1402, a liquid die paste is supplied to the surface of the insulating substrate 1402, and the semiconductor chip 1400 is pressed onto the die paste. The method of applying and adhering this is performed. At this time, the die paste 140 is formed around the semiconductor chip 1400.
It is known that 4 protrudes and a die paste pool called fillet F is formed. Generally, the protrusion of such die paste extends from the periphery of the semiconductor chip 1400 to a range of about 200 to 300 μm. Also, when a film adhesive is used instead of the die paste (liquid), the film adhesive is fluidized when pressure is applied, and a similar fillet is formed. Semiconductor chip 1
If such a fillet F exists around 400,
The bonding position B of the conductor wire 1410 on the conductor lead 1406 should be provided at a position relatively away from the semiconductor chip 1400 while avoiding the fillet F. This is an obstacle to further miniaturization of the semiconductor package.

Further, the presence of such fillets poses a problem even in a semiconductor package having a stack structure in which a plurality of semiconductor chips are laminated. That is, in a semiconductor package having a stack structure, the size of each stacked semiconductor chip is made smaller toward the upper layer, thereby ensuring a region for electrode pad formation near the outer periphery of the main surface of each semiconductor chip. There is. However, even in the semiconductor package having such a stack structure, when the upper-layer semiconductor chip is bonded to the main surface of the lower-layer semiconductor chip, the adhesive layer extends beyond the chip region to form a fillet. Therefore, it is necessary to determine the relative plane size of the semiconductor chips to be stacked, in consideration of this protrusion amount. As a result, there is a problem in that the plane size of the upper layer semiconductor chip cannot be made much larger than that of the lower layer semiconductor chip, and the constraint in the package design becomes large.

Therefore, firstly, an object of the present invention is to further miniaturize a semiconductor package by minimizing the amount of fillet protruding from the periphery of the semiconductor chip.

A second object of the present invention is to minimize the amount of fillets protruding from the periphery of the semiconductor chip in a semiconductor package having a stacked structure, thereby making it possible to form an upper layer with respect to a lower semiconductor chip to be stacked. To maximize the planar size of the semiconductor chip.

[0008]

The semiconductor device of the present invention comprises:
On an insulating substrate having conductor leads formed on the main surface, an electronic circuit and an electrode pad are formed on the main surface, and on the back surface side having a smaller area than the main surface, on the main surface side of the insulating substrate. A first semiconductor chip fixed via an adhesive, the conductor lead of the insulating substrate, and the first semiconductor chip.
A conductor wire electrically connecting to the electrode pad of the semiconductor chip, and a sealing material provided on the insulating substrate and sealing the first semiconductor chip and the conductor wire,
And an electrode for external connection formed on the back surface of the insulating substrate with respect to the main surface.

In the above structure, the area of the back surface of the first semiconductor chip is smaller than that of the main surface of the first semiconductor chip, so that the fillet is formed when the semiconductor chip is mounted on the insulating substrate. With respect to the outer shape of the semiconductor chip (which is determined by the planar size of the main surface), there is no or a minimum amount of protrusion. Therefore, the bonding position of the conductor wire can be easily secured, and the size of the semiconductor device can be further reduced.

In the semiconductor device of the present invention, an electronic circuit and an electrode pad are formed on the main surface, and the back surface side is directly fixed to the main surface side of the insulating substrate via an adhesive. The semiconductor chip may be further provided, and the first semiconductor chip may be directly fixed onto the main surface of the second semiconductor chip via an adhesive.

In a semiconductor device having such a structure, that is, a so-called stack structure, the back surface side of the upper semiconductor chip is
By making the area smaller than the main surface side, the planar size of the upper semiconductor chip can be maximized with respect to the lower semiconductor chip to be stacked.

In this case, it is preferable that the second semiconductor chip has a back surface having an area smaller than that of the main surface.

Further, in each of the semiconductor devices, each side of the back surface of the first semiconductor chip and / or the second semiconductor chip is retracted inward from each side of the main surface of the semiconductor chip. An outer peripheral end surface inclined at a predetermined angle is formed at a position, and the retreat amount is 100 μm or more and 300 μm
The following is preferable.

Further, it is preferable that an inclination angle of the outer peripheral end surface of the first semiconductor chip and / or the second semiconductor chip with respect to the main surface is 30 ° or more and 60 ° or less.

The semiconductor device of the present invention adopts a structure in which the outer peripheral end surface of the first semiconductor chip and / or the second semiconductor chip has a stepped shape instead of the predetermined angle inclination. You can also

The present invention also relates to a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to the present invention includes a step of forming an electronic circuit and an electrode pad on a main surface of a wafer which is a semiconductor substrate; A step of cutting so as to be larger than the area, a step of supplying an adhesive to the main surface of an insulating substrate having conductor leads formed on the main surface, and a first semiconductor chip formed by cutting the wafer Fixing the insulating substrate to the main surface side of the insulating substrate via the adhesive, and connecting the conductor lead of the insulating substrate and the electrode pad of the first semiconductor chip with a conductor wire. , A step of supplying a resin onto the insulating substrate to seal the first semiconductor chip, and a step of forming an electrode for external connection on a back surface of the insulating substrate with respect to the main surface. It

In the above manufacturing method, the present invention further comprises a step of preparing a second semiconductor chip having an electronic circuit and an electrode pad formed on a main surface thereof, wherein the first semiconductor chip is formed on the insulating substrate. The step of fixing the second semiconductor chip to the main surface side with the adhesive agent, the step of directly fixing the second semiconductor chip to the main surface side of the insulating substrate with the adhesive agent, and the first semiconductor chip. Can be directly fixed to the main surface of the second semiconductor chip via an adhesive.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail based on the illustrated embodiment. FIG. 1A is a sectional view showing the basic structure of a semiconductor package as a semiconductor device according to the first embodiment. The semiconductor package of the present embodiment has a semiconductor chip 100 fixed to an insulating substrate 102 via a die paste 104 as an adhesive. The semiconductor chip 100 is formed by forming an integrated circuit (not shown) on the main surface of the silicon substrate (referred to as the circuit surface 112), and is bonded to the insulating substrate 102 on the back surface (referred to as the adhesion surface 114). The circuit surface 112 and the adhesive surface 114 are formed parallel to each other. The die paste 104 is made of thermoplastic polyimide or the like. The insulating substrate 102 is a substrate made of polyimide or ceramics, and has a main surface (semiconductor chip 10).
The conductor lead 10 made of copper is provided on the surface on which 0 is mounted.
6 is formed. The conductor lead 106 is the insulating substrate 1.
It is connected to the solder bump 108 as an external connection terminal through the through hole formed in 02. In the preferred embodiment, the semiconductor chip 100 has a thickness of about 250-3.
The insulating substrate 102 has a thickness of about 50 μm. The thickness of the die paste 104 is about 20 to 50 μm.
m.

The circuit surface 112 of the semiconductor chip 100 has a large number of electrode pads 120 (only two are shown in FIG. 1) extending from the integrated circuit along the outer periphery thereof.
The electrode pad 120 on the circuit surface 112 and the conductor lead 106 on the insulating substrate 102 are made of a conductor wire 110 made of gold.
Connected by. These semiconductor chips 100,
The insulating substrate 102 and the conductor wire 110 are sealed with a sealing material 118 made of resin.

FIG. 1B is a perspective view showing the external shape of the semiconductor chip 100 as seen from the adhesive surface 114 side. Both the circuit surface 112 and the bonding surface 114 of the semiconductor chip 100 have a substantially rectangular shape, but the area of the bonding surface 114 is smaller than the area of the circuit surface 112, and the bonding surface 114 has four areas.
The four sides are at positions retracted inward from the four sides of the circuit surface 112. Further, the outer peripheral end surface 116 of the semiconductor chip 100 is a tapered surface that is inclined with respect to the circuit surface 112 (and the bonding surface 114). This is formed by reducing the amount of the die paste, which sticks out around the bonding surface 114 in the step of bonding the semiconductor chip 100 to the insulating substrate 102, to the outside of the circuit surface 112 or reduces it to zero. This is because In a preferred embodiment, it is preferable that each side of the adhesive surface 114 is at a position retracted inward by 100 μm to 300 μm from each side of the circuit surface 112. In this way, the adhesive surface 11
This is because the die paste protruding around 4 is substantially contained in the space inside the circuit surface 112. The inclination angle of the outer peripheral end surface 116 with respect to the circuit surface 112 is 30 °.
It is preferably -60 °.

Next, a method of manufacturing the semiconductor package according to this embodiment will be described with reference to FIGS. First, a main surface 20 of a wafer 200 made of silicon, which is a semiconductor substrate, is formed by a normal wafer process.
1, an integrated circuit forming a predetermined circuit pattern and an electrode pad (for connection with the conductor lead 106) extracted from this integrated circuit are formed. Next, as shown in FIG. 2A, the resin-made first sheet 202 having adhesiveness
Then, the wafer 200 is attached from the main surface 201 side.

Then, as shown in FIG. 2B, the first
The wafer 200 supported by the sheet 202 is cut using the blade 204 for dicing. In the preferred embodiment,
Using the blade 204 having a blade width of 400 μm and a blade edge angle a of 60 ° to 120 °, the first sheet 20 of the wafer 200 is used.
Dicing from the side opposite to 2. This dicing is
Continue until the blade 204 reaches the first sheet 202. As a result, a plurality of semiconductor chips 100 having an outer peripheral end surface having an inclination of 30 ° to 60 ° from the wafer 200.
Is cut out. It should be noted that the main surface 201 of the wafer 200 is preliminarily formed with a grid-like scrub line indicating the dicing position, and the dicing of the wafer 200 is performed while observing the scrub line using an infrared camera.

When the cutting of the wafer 200 is completed, the cut wafer 200 is washed, and then the first sheet 202 is irradiated with ultraviolet rays (UV) to wash the first sheet 202.
Is cured to lose the adhesive strength. Next, as shown in FIG. 2C, a second resin sheet 206 having adhesiveness is attached to the side of the wafer 200 opposite to the first sheet 202 side. After that, as shown in FIG. 2D, the first sheet 202 is peeled from the wafer 200 while the wafer 200 is supported by the second sheet 206. Next, after the second sheet 206 is irradiated with ultraviolet rays to eliminate the adhesive force, the individual semiconductor chips 100 are peeled from the second sheet 206 as shown in FIG.

The individual semiconductor chips 100 thus taken out are adhered to the insulating substrate 102 using a die paste 104, as shown in FIG. That is, on the main surface of the insulating substrate 102 (the surface on the conductor lead 106 side),
After the die paste 104 is supplied by a method called potting, the semiconductor chip 100 is pressed onto the die paste 104. Thereby, the semiconductor chip 100
Are fixed to the insulating substrate 102 via the die paste 104. At this time, since the adhesive surface 114 of the semiconductor chip 100 is smaller than the circuit surface 112, even if the die paste protrudes around the adhesive surface 114, the amount of protrusion to the outside of the circuit surface 112 is small. Subsequently, the electrode pad 120 of the semiconductor chip 100 and the conductor lead 106 on the insulating substrate 102 are connected to the conductor wire 1 by wire bonding.
Connect via 10. After that, the resin is supplied onto the insulating substrate 102 to form the sealing material 118, and the semiconductor chip 1 is formed.
00 is sealed. In this way, the semiconductor package shown in FIG. 1 is obtained.

As described above, in the present embodiment,
Since the adhesive surface 114 of the semiconductor chip 100 is made smaller than the circuit surface 112, even if the die paste protrudes around the adhesive surface 114, the amount of protrusion to the outside of the circuit surface 112 can be reduced. As a result, the bonding position on the conductor lead 106 can be brought close to the outer circumference of the semiconductor chip 100. Therefore, the semiconductor package can be further downsized, which can contribute to high integration of electronic information devices and the like.

In particular, each side of the adhesive surface 114 has a circuit surface 11
Since the structure is configured to be retracted inward by 100 μm to 300 μm from each side of 2, the protruding portion of the adhesive can be accommodated in this retracted space, and the semiconductor package can be reliably downsized. In addition, since the outer periphery of the semiconductor chip 100 is provided with a taper, a structure in which the adhesion surface 114 is smaller than the circuit surface 112 can be obtained by relatively simple processing.

Next, a second embodiment of the present invention will be described. FIG. 3 shows a semiconductor device according to the second embodiment. Similar to the first embodiment, the semiconductor chip 300
An integrated circuit (not shown) and an electrode pad 320 are formed on the circuit surface 312 of the die paste 30.
It is adhered to the insulating substrate 302 via 4. Further, the semiconductor chip 300 is sealed with a sealing material 318, and the back surface side of the insulating substrate 302 (the side opposite to the semiconductor chip 300).
Solder bumps 308 are provided on. In addition, as in the first embodiment, the semiconductor chip 300 has the adhesive surface 314.
Is smaller than the circuit surface 312.
However, in the outer peripheral end surface 316 of the semiconductor chip 300, the end surface 316 on the circuit surface 312 side becomes a vertical end surface, and the bonding surface 314
The side end surface 317 is configured to be a tapered surface. The material of each component is the same as that of the first embodiment.

FIG. 4 shows a method of manufacturing a semiconductor package according to this embodiment. First, an integrated circuit and electrode pads are formed on the surface of the wafer 400 by a normal wafer process, and the integrated circuit is formed on the first sheet 402 made of resin as shown in FIG. 4A. And attach it with the facing surface (bottom surface in the figure) facing. After that, as shown in FIG. 4B, the wafer 400 is cut. In a preferred embodiment, the cutting edge angle a is 60 ° to 120 °.
The wafer 400 is diced from the side opposite to the first sheet 402 side by the first blade 404 having a blade width of 400 μm at an angle of 400 °. However, the dicing by the first blade 404 is performed halfway in the thickness direction of the wafer 400. Next, as shown in FIG. 4C, the first blade 404
The wafer 400 is completely cut (until the respective semiconductor chips 300 are separated) by using the second blade 405 having a narrower blade width and a vertical edge face than the second blade 405. after that,
Similar to the first embodiment, after the cut wafer 400 is washed, the first sheet 402 is irradiated with ultraviolet rays to lose the adhesive force, and as shown in FIG.
On the side opposite to the first sheet 402 side of another resin second
After the sheet 406 is attached, the first sheet 402 is peeled off as illustrated in FIG. Next, after irradiating the second sheet 406 with ultraviolet rays to eliminate the adhesive force,
As shown in FIG. 4F, the individual semiconductor chips 300 are
Is peeled from the second sheet 406. The semiconductor chip 300 thus taken out is adhered to the insulating substrate 302 using the die paste 304 as shown in FIG. 3, and further, the electrode pad 320 of the semiconductor chip 300 and the conductor lead 306 on the insulating substrate 302 are bonded. And are connected by wire bonding (conductor wire 310). As a result, the semiconductor package shown in FIG. 3 is obtained.

Also in this embodiment, the semiconductor chip 3 is used.
Since the bonding surface 314 of 00 is smaller than the circuit surface 312,
Even if the die paste protrudes around the bonding surface 314, the amount of protrusion to the outside of the semiconductor chip 300 can be reduced. As a result, the wire bonding position on the conductor lead 306 is changed to the semiconductor chip 30.
It is possible to approach 0, and the semiconductor package can be further miniaturized.

Next, a third embodiment of the present invention will be described. FIG. 5 shows a semiconductor device according to the third embodiment. Similar to the first embodiment, the semiconductor chip 500
The integrated circuit (not shown) and the electrode pad 520 are formed on the circuit surface 512 of the die paste 50.
It is adhered to the insulating substrate 502 via 4. Further, the semiconductor chip 500 is sealed with a sealing material 518, and the back surface side of the insulating substrate 502 (the side opposite to the semiconductor chip 500).
Are provided with solder bumps 508. Further, similarly to the first and second embodiments, the semiconductor chip 500 is configured so that the adhesive surface 514 is smaller than the circuit surface 512. However, the outer peripheral end surface of the semiconductor chip 500 is a vertical end surface having a two-step structure, and the end surface 5 on the circuit surface 512 side is
16 is configured to project outward from the end surface 517 on the adhesive surface 514 side. The material of each component is the same as that of the first embodiment.

FIG. 6 shows a method of manufacturing a semiconductor package according to this embodiment. First, an integrated circuit is formed on the surface of the wafer 600 by a normal wafer process, and then, as shown in FIG.
The wafer 600 is attached to the sheet 602 with the surface on which the integrated circuit is formed facing. After that, as shown in FIG. 6B, the wafer 600 is cut. In the preferred embodiment, the first blade 604 having a blade width of 400 μm and a vertical edge is a vertical end face is used to remove the wafer 600 from the first blade 604.
Dicing is performed from the side opposite to the sheet 602 side. However,
The dicing by the first blade 604 is performed on the wafer 600.
Halfway in the thickness direction. Next, as shown in FIG. 6C, the wafer 600 is completely cut (so that the semiconductor chips 500 are separated) by using the second blade 605 having a narrower blade width than the first blade 604. After that, as in the first embodiment, after the cut wafer 600 is washed, the first sheet 602 is irradiated with ultraviolet rays to eliminate the adhesive force. Then, as shown in FIG. 6D, on the side opposite to the first sheet 602 side of the wafer 600,
Another resin second sheet 606 is attached. After that, as shown in FIG. 6E, the first sheet 602 is peeled from the wafer 600 while the wafer 600 is supported by the second sheet 606. Next, after the second sheet 606 is irradiated with ultraviolet rays to eliminate the adhesive force, the individual semiconductor chips 500 are attached to the second sheet 60 as shown in FIG. 6 (F).
Peel from 6. As shown in FIG. 5, the semiconductor chip 500 thus taken out is adhered onto the insulating substrate 502 by using the die paste 504, and further, the electrode pad 620 of the semiconductor chip 600 and the conductor lead on the insulating substrate 502. 506 and wire bonding (conductor wire 51
0) to connect. As a result, the semiconductor package shown in FIG. 5 is obtained.

Also in this embodiment, the semiconductor chip 5 is used.
Since the bonding surface 514 of 00 is smaller than the circuit surface 512,
Even if the die paste protrudes around the bonding surface 514, the amount of protrusion to the outside of the circuit surface 512 can be reduced. As a result, the wire bonding position on the conductor lead 506 can be brought closer to the semiconductor chip 500, and the size of the semiconductor package can be further reduced.

Next, fourth to sixth embodiments in which the present invention is applied to a semiconductor package having a stack structure, that is, a structure in which semiconductor chips are stacked in the package will be described.

FIG. 7 is a sectional view showing a semiconductor package having a stack structure according to the fourth embodiment. In this semiconductor package, the semiconductor chip 700 is fixed on the insulating substrate 102 using the die paste 104, and the die paste 702 is used thereon to form the tapered outer peripheral surface described in the first embodiment. The semiconductor chip 100 having is fixed. The insulating substrate 102 and the semiconductor chip 100 have the same configuration as that of the first embodiment (FIG. 1). Of the components shown in FIG. 7, the components described in FIG. 1 will be described using the same reference numerals, and description thereof will be omitted.

In the present embodiment, the semiconductor chip 700
Unlike the semiconductor chip 100, is a semiconductor chip having a general shape in which a main surface, that is, a circuit surface and a back surface, that is, an adhesive surface are configured to have the same size. On the circuit surface of the semiconductor chip 700, electrode pads 720 are formed around the surface area on which the semiconductor chip 100 is mounted. The electrode pad 720 and the conductor lead 106 on the insulating substrate 102 are connected by a conductor wire 710. Further, the electrode pad 120 of the semiconductor chip 100 and the conductor lead 106 on the insulating substrate 102 are connected by a conductor wire 110. The taper of the side end surface of the semiconductor chip 100 is 30 to 6 as in the first embodiment.
It is preferably 0 °, particularly preferably about 45 °.
Is. Both the semiconductor chips 100 and 700 are covered with a sealing material 704.

FIG. 8 shows a method of manufacturing a semiconductor package according to this embodiment. First, as shown in FIG. 8A, a semiconductor chip 700 manufactured in another process
Is fixed to the main surface of the insulating substrate 102 using the die paste 104. Subsequently, as shown in FIG. 8B, the electrode pad 720 of the semiconductor chip 700 and the conductor lead of the insulating substrate 102 are connected by the conductor wire 710 using a wire bonding method. Further, as shown in FIG. 8C, the die paste 702 is supplied to the circuit surface of the semiconductor chip 700. Next, as shown in FIG. 8D, the semiconductor chip 100 formed in the process shown in FIG. 2 is formed on the die paste 702 on the semiconductor chip 700.
Are fixed so that the bonding surface side faces the semiconductor chip 700 side (that is, the insulating substrate 102 side). after that,
As shown in FIG. 8E, the electrode pad 120 of the semiconductor chip 100 and the conductor lead of the insulating substrate 102 are connected by the conductor wire 110 using the wire bonding method. After that, as shown in FIG. 7, the semiconductor chips 100 and 700 are sealed with a sealing material 704, and the insulating substrate 10
A solder ball 708 is attached to the No. 2.

In the present embodiment, the semiconductor chip 1
Since the adhesive surface of 00 is smaller than the circuit surface, even if the die paste 702 protrudes from the adhesive surface of the semiconductor chip 100 to form a fillet, the amount of protrusion to the outside of the semiconductor chip 100 can be reduced. Therefore, the electrode pad 7 on the circuit surface of the semiconductor chip 700 is
It becomes easy to secure a region for forming 20.

In the preferred embodiment, the fillet is preferably housed below the side edge of the semiconductor chip 100.
In this case, for example, assuming that the length of the fillet is about 0.2 mm, conventionally, the outer peripheral edge of the semiconductor chip 700 is located outside the outer peripheral edge of the semiconductor chip 100 by about 0.5 mm (that is, the semiconductor chip 700 is reduced by that much). big)
However, in this embodiment, the outer side may be about 0.3 mm. With this configuration, the size of the upper semiconductor chip 100 can be increased by 0.2 mm on one side (0.4 mm on both sides), and restrictions in design can be reduced. On the contrary, the size of the lower semiconductor chip 700 is 0.2 mm on one side (0.4 m on both sides).
m) It can be made smaller. This makes it possible to reduce the size of the semiconductor package.

The conductor wire 710 is the semiconductor chip 10.
The side end surface of the semiconductor chip 100 may cover above the wire bonding position on the insulating substrate 102 as long as it does not contact the side end surface of 0. Even with such a configuration, wire bonding is possible if the steps shown in FIG. 8 are performed.

In this embodiment, an example is shown in which only the upper semiconductor chip 100 to be stacked has a tapered outer peripheral surface, but the lower semiconductor chip 700 is shown.
Can have a similar configuration. in this case,
As in the case of the first embodiment, the insulating substrate 102
Since the protrusion amount of the upper fillet can be reduced, it is further effective in reducing the size of the package.

FIG. 9 is a sectional view showing a semiconductor package according to the fifth embodiment. In this semiconductor package, a semiconductor chip 700 is fixed on an insulating substrate 302, and the semiconductor chip 300 described in the second embodiment is fixed thereon. Insulating substrate 302
The semiconductor chip 300 is the second embodiment (FIG. 3).
It has the same configuration as. Of the components shown in FIG. 9, the components described in FIGS. 3 and 7 will be described using the same reference numerals, and description thereof will be omitted.

In this embodiment, the semiconductor chip 700 is fixed on the insulating substrate 302 via the die paste 304, and the semiconductor chip 300 is fixed on the circuit surface thereof via the die paste 702. Insulating substrate 302
The upper conductor lead 306 and the electrode pad 720 of the semiconductor chip 700 are connected by a conductor wire 710, and the conductor lead 306 on the insulating substrate 302 and the semiconductor chip 30.
The zero electrode pad 320 is connected by the conductor wire 310.

FIG. 10 shows a method of manufacturing a semiconductor package according to this embodiment. First, FIG.
As shown in (A), the semiconductor chip 700 is fixed to the main surface of the insulating substrate 302 using the die paste 304. Subsequently, as shown in FIG. 10B, the electrode pad 720 of the semiconductor chip 700 and the conductor lead of the insulating substrate 302 are connected by the conductor wire 710 using a wire bonding method. Next, as shown in FIG. 10C, the die paste 70 is applied to the circuit surface of the semiconductor chip 700.
Supply 2. Then, as shown in FIG.
On the die paste 702 on the semiconductor chip 700, as shown in FIG.
In the semiconductor chip 300 manufactured in the step shown in FIG. 3, the bonding surface side is the semiconductor chip 700 side (that is, the insulating substrate 302
Side) and fix it. After that, FIG.
As shown in (E), the electrode pad 320 of the semiconductor chip 300 and the conductor lead of the insulating substrate 302 are connected by the conductor wire 310 using the wire bonding method. After that, as shown in FIG.
00 and 700 are sealed with a sealing material 704, and the insulating substrate 302
A solder ball 708 is attached to the.

Similar to the fourth embodiment, in the present embodiment, since the bonding surface of the semiconductor chip 300 is smaller than the circuit surface, the die paste 7 is applied from the bonding surface of the semiconductor chip 300.
Even if 02 extends to form a fillet, the amount of protrusion to the outside of the semiconductor chip 300 can be reduced. Therefore, it becomes easy to secure a region for forming the electrode pad 720 on the circuit surface of the semiconductor chip 700. As a result, it is possible to reduce the size of the semiconductor package having a stack structure, and it is possible to reduce restrictions in designing.

FIG. 11 is a sectional view showing a semiconductor package according to the sixth embodiment. In this semiconductor package, the semiconductor chip 700 is fixed on the insulating substrate 502, and the semiconductor chip 500 described in the third embodiment is fixed thereon. Insulating substrate 50
2 and the semiconductor chip 500 have the same configuration as that of the third embodiment (FIG. 5). Of the constituent elements shown in FIG. 9, the constituent elements described in FIGS. 5 and 7 are described using the same reference numerals, and description thereof will be omitted.

In this embodiment, the semiconductor chip 700 is fixed on the insulating substrate 502 via the die paste 504, and the semiconductor chip 500 is fixed on the circuit surface thereof via the die paste 702. Insulating substrate 502
The upper conductor lead 506 and the electrode pad 720 of the semiconductor chip 700 are connected by a conductor wire 710, and the conductor lead 506 on the insulating substrate 502 and the semiconductor chip 50.
The zero electrode pad 520 is connected by a conductor wire 510.

FIG. 12 shows a method of manufacturing a semiconductor package according to this embodiment. First, FIG.
As shown in (A), the semiconductor chip 700 is fixed to the main surface of the insulating substrate 502 using a die paste 504. Subsequently, as shown in FIG. 12B, the electrode pad 720 of the semiconductor chip 700 and the conductor lead of the insulating substrate 502 are connected by the conductor wire 710 using the wire bonding method. Next, as shown in FIG. 12C, the die paste 70 is applied to the circuit surface of the semiconductor chip 700.
Supply 2. Then, as shown in FIG.
On the die paste 702 on the semiconductor chip 700, as shown in FIG.
The semiconductor chip 500 manufactured in the step shown in FIG.
Side) and fix it. After that, FIG.
As shown in (E), the electrode pad 520 of the semiconductor chip 500 and the conductor lead of the insulating substrate 502 are connected by the conductor wire 510 using the wire bonding method. After that, as shown in FIG. 11, the semiconductor chips 500 and 700 are sealed with a sealing material 704, and the insulating substrate 50
A solder ball 708 is attached to the No. 2.

Similar to the fourth and fifth embodiments, in the present embodiment, since the bonding surface of the semiconductor chip 500 is smaller than the circuit surface, the die paste 702 protrudes from the bonding surface of the semiconductor chip 500 to form a fillet. Even if formed, the amount of protrusion to the outside of the semiconductor chip 500 can be reduced. Therefore, it becomes easy to secure a region for forming the electrode pad 720 on the circuit surface of the semiconductor chip 700. As a result, it is possible to reduce the size of the semiconductor package having a stack structure, and it is possible to reduce restrictions in designing.

The embodiments of the present invention have been described above with reference to the drawings. However, it is obvious that the present invention is not limited to the matters shown in the respective embodiments, and changes and improvements thereof can be made based on the description of the claims.

For example, in the third embodiment, FIG.
In the dicing process of the wafer 600 shown in (B) and (C), two types of blades 604 and 605 having different widths are used to make the end surface of the semiconductor chip into two steps, but the method shown in FIG. 13 is also possible. is there. That is, in FIG.
As shown in (B), while dicing the wafer 600 with a blade 1304 having a small width, the blade 1304 is moved in a direction orthogonal to the dicing direction to form a groove having a large width, and a central portion of the groove is formed. Blade 13
By cutting with 06, the end surface of the semiconductor chip can be formed into a two-step shape. The subsequent steps are shown in FIG.
The same as (D) to (F).

[0051]

As described above, according to the present invention, the amount of the fillet protruding from the periphery of the semiconductor chip can be minimized or completely eliminated, thereby further miniaturizing the semiconductor package. Is something that can be done.

Further, in a so-called stack structure semiconductor package, by adopting the present invention, it is possible to maximize the planar size of the upper layer semiconductor chip with respect to the lower layer semiconductor chip to be stacked. The restrictions of can be reduced.

[Brief description of drawings]

FIG. 1 is a side sectional view (A) of a semiconductor package according to a first embodiment of the present invention and a perspective view (B) of a semiconductor chip.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 3 is a side sectional view of a semiconductor package according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 5 is a side sectional view of a semiconductor package according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 7 is a side sectional view of a semiconductor package according to a fourth embodiment of the present invention.

8 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 9 is a side sectional view of a semiconductor package according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 11 is a side sectional view of a semiconductor package according to a sixth embodiment of the present invention.

12 is a diagram showing a manufacturing process of the semiconductor package shown in FIG.

FIG. 13 is a cross-sectional view showing another example of the wafer dicing process.

FIG. 14 is a cross-sectional view showing a structure of a conventional semiconductor package.

[Explanation of symbols]

100, 300, 500, 700 Semiconductor chip 102, 302, 502 Insulating substrate 104, 304, 504, 702 Die paste 106, 306, 506 Conductor lead 110, 310, 510, 710 Conductor wire 112, 312, 512 Main surface 114, 314, 514 Back surface 120, 320, 520, 720 Electrode pad 116 Outer peripheral end surface 316, 317, 516, 517 End surface 200, 400, 600 Wafer 204, 404, 405, 604, 605, 1034
1305 blade

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 25/18 (72) Inventor Mutsumi Masumoto 4260 Takao, Hiji-cho, Hayami-gun, Oita Prefecture Takao 4260 Japan Texas Instruments Stocks In-house F-term (reference) 5F047 AA17 BA21 BB11 CB01

Claims (8)

[Claims] 1. An insulating substrate having conductor leads formed on a main surface thereof, and an electronic circuit and an electrode pad formed on the main surface of the insulating substrate on the back surface side having a smaller area than the main surface. A first semiconductor chip fixed to the main surface side with an adhesive; a conductor wire electrically connecting the conductor lead of the insulating substrate and the electrode pad of the first semiconductor chip; A sealing material provided on an insulating substrate for sealing the first semiconductor chip and the conductor wire; and an electrode for external connection formed on a back surface of the insulating substrate with respect to the main surface. A semiconductor device characterized by: 2. A second semiconductor chip having an electronic circuit and an electrode pad formed on a main surface thereof, and a back surface side thereof being directly fixed to the main surface side of the insulating substrate via an adhesive, The semiconductor device according to claim 1, wherein the first semiconductor chip is directly fixed to the main surface of the second semiconductor chip via an adhesive. 3. The semiconductor device according to claim 2, wherein the second semiconductor chip has a back surface having an area smaller than that of the main surface. 4. A predetermined angle inclination at a position where each side of the back surface of the first semiconductor chip and / or the second semiconductor chip is retracted inward from each side of the main surface of the semiconductor chip. The outer peripheral end face is formed, and the retracted amount is 10
It is 0 micrometer or more and 300 micrometers or less, The semiconductor device as described in any one of Claims 1-3. 5. The tilt angle of the outer peripheral end surface of the first semiconductor chip and / or the second semiconductor chip with respect to the main surface is 30 ° or more and 60 ° or less. Semiconductor device. 6. The outer peripheral end face of the first semiconductor chip and / or the second semiconductor chip has a stepped shape, according to any one of claims 1 to 3. Semiconductor device. 7. A step of forming an electronic circuit and an electrode pad on a main surface of a wafer which is a semiconductor substrate, so that the area of the main surface of each wafer of the wafer is larger than the area of the back surface thereof. And a step of supplying an adhesive to the main surface of an insulating substrate having conductor leads formed on the main surface, and a first semiconductor chip formed by cutting the wafer,
Fixing the insulating substrate to the main surface side via the adhesive; connecting the conductor lead of the insulating substrate and the electrode pad of the first semiconductor chip with a conductor wire; A step of supplying a resin onto an insulating substrate to seal the first semiconductor chip; and a step of forming an electrode for external connection on a back surface of the insulating substrate with respect to the main surface, Of manufacturing a semiconductor device. 8. The method further comprises the step of preparing a second semiconductor chip having an electronic circuit and an electrode pad formed on a main surface thereof, wherein the first semiconductor chip is bonded to the main surface side of the insulating substrate. Fixing the second semiconductor chip to the main surface side of the insulating substrate directly with an adhesive, and fixing the first semiconductor chip to the second semiconductor. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of directly fixing the chip on the main surface of the chip via an adhesive.