JP2003108260A - Information processer and controlling method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow changing an operating frequency and a voltage enabling to operate at the minimum consumption power possible to achieve a processing capacity enough to perform an application. SOLUTION: An apparatus for information processing comprises MPUs 101 and 102, a memory control unit 103, dividers 111, 113, 115 and 120 whose frequency-division ratios are individually controlled to a functional block 106 and vary those operating frequencies. An application on the apparatus prepares information on operating frequencies optimum to each MPU 101 and 102 and the functional block 106. A control means for controlling the information for a plurality of applications is prepared to acquire the present operating status from the control means when initiating the applications and allocates the processing capacity needed by the applications to be initiated to each MPU 101 and 102 and the functional block 106 to vary those operating frequencies, and the same operation is performed when exiting the applications.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a control method for the information processing apparatus, and more particularly to an information processing apparatus and a control method for the information processing apparatus whose operating frequency is changeable.

[0002]

2. Description of the Related Art In recent years, in the fields of signal processing, media processing, etc., processing using a processor or dedicated hardware has come to be performed. These processes require a very large amount of calculation and require real-time processing that requires the processing to be completed within a fixed time. For this reason,
An information processing apparatus that implements these processes requires extremely high processing performance, and a high operating frequency is required to achieve this.

Generally, the power consumption of a semiconductor circuit such as a processor formed of CMOS transistors increases in proportion to its operating frequency. Since these power consumptions become obstacles when configuring the information processing apparatus, various methods for reducing the power consumption have been proposed.

For example, a technique described in Japanese Patent Laid-Open No. 8-202468 is known as a conventional technique that can reduce power consumption in a multiprocessor system or the like. This conventional technology detects the processing state of each processor in a multiprocessor system and shifts the unused or lightly loaded processor to a low power consumption mode to reduce the power consumption of the entire system. is there.

As a conventional technique of a terminal, for example, a technique described in Japanese Patent Laid-Open No. 2000-66776 is known. This prior art relates to a method of controlling the power consumption of a sub-circuit of a system, in which an operating frequency commensurate with a load assigned to a processor is determined, and a power supply voltage at which the processor can operate is detected. By applying the power supply voltage to the processor, it is possible to operate the processor with the minimum power that can handle the load.

As described above, in order to construct a large-scale information processing device such as a multiprocessor system, it has been attempted to reduce the overall power consumption.

On the other hand, the degree of integration of semiconductor circuits has been increasing year by year, and as a result, it has become possible to integrate an information processing apparatus, which was previously composed of a plurality of parts, into one semiconductor circuit. It was This makes it possible to develop a smaller information processing device, which is applied to various small devices. In particular, it is possible to create a portable information processing device by using a power supply source such as a battery. Conventionally, when a semiconductor circuit is used for such an application, one having a maximum power consumption commensurate with the capacity of a power supply source has been developed or selected, but this method requires a high load such as the above-mentioned media processing. It is difficult to realize an information processing device that performs processing.

[0008]

As described above, while the information processing apparatus is required to have an increased processing capacity, it is required to save power such that it can be operated by a battery.
Therefore, in order to satisfy these two requirements, the information processing apparatus has sufficient processing capacity for an application that is an object to be processed by a certain information processing apparatus, and can realize the processing capacity. It is required to operate with minimum power consumption.

However, the above-mentioned conventional information processing apparatus has a problem that it cannot satisfy the above-mentioned two requirements simultaneously and sufficiently.

An object of the present invention is to have a high processing capacity capable of changing an operating frequency and an operating voltage so as to operate with a minimum power consumption capable of realizing a sufficient processing power for an application, and a low power consumption. An object of the present invention is to provide an information processing apparatus and a method for controlling the information processing apparatus, which are realized.

[0011]

According to the present invention, the object is to provide an information processing apparatus comprising one or more processors, one or more functional blocks having dedicated logic, or both. , Means for independently changing the operating frequency of each of the functional blocks,
The operating frequency of the processor or the functional block is determined based on the optimal operating frequency information of the processor or the functional block of each of the one or more applications operating on the information processing apparatus, and the operating frequency is changed. And control means for controlling the means.

[0012] Further, the above-mentioned object is a method of controlling an information processing apparatus comprising one or a plurality of processors and / or one or a plurality of functional blocks having a dedicated logic. Or, based on the optimum operating frequency information for each of the processors and functional blocks of each of the multiple applications,
Determine the operating frequency of the processor, functional block,
This is achieved by independently changing the operating frequencies of the processor and the functional blocks.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an information processing apparatus according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the hardware configuration of an information processing apparatus according to the first embodiment of the present invention, and FIG. 2 is a flow chart for explaining the processing operation of a program used when an application program is added and activated. 3, FIG. 3 is a flow chart for explaining the processing operation of the program used at the end of the application program, FIG. 4 is a diagram for explaining the clock table used in the processing of FIG. 2, and FIG. 5 is an additional application started in the processing of FIG. Diagram explaining the state of the clock table after,
FIG. 6 is a diagram for explaining the state of the clock table after the application is terminated in the process of FIG.
A first embodiment of the present invention will be described with reference to these drawings.

In FIG. 1, 101 and 102 are first and second microprocessor units (hereinafter referred to as MPU), 103 is an external memory control unit, 104 is an external memory, 105 is a system bus, 106 is a functional block, 107. Is a digital-to-analog converter (hereinafter, D
AC), 108 and 118 are first and second phase locked loops (hereinafter, PLL), 109 and 11
9 is the first and second PLL reference clocks, 11
0 is the oscillation clock of the first PLL, 111, 113, 1
Reference numerals 15 and 120 are first to fourth frequency dividers, 112 and 114 are first and second MPU local clocks, 116 is a memory control unit local clock, and 117 and 122 are first and second control registers. , 121 are local clocks for functional blocks and DACs.

In the first embodiment of the present invention shown in FIG. 1, the first PLL 108 multiplies the reference clock 109 based on the value of the first control register 117 to create the oscillation clock 110. The oscillation clock 110 is used for the first to third frequency dividers 111, 113, 11
5 through the first MPU101, the second MPU102
And used to generate local clocks 112, 114, 116 for driving the memory control unit 103. Each of the frequency dividers 111, 113, 115
It is independently controlled based on the value from the first control register 117, and divides the oscillation clock 110 to reduce the frequency to 1 / n. Since the frequency dividers 111, 113, 115 are provided for each of the first and second MPUs 101, 102 and the memory control unit 103, each unit has its operating frequency 1 /
It is possible to receive as a frequency set to n times (the value of n may be different for each frequency divider), and it is possible to operate at a required frequency.

The first and second MPUs 101 and 102 read programs and data from the external memory 104,
It also performs arithmetic operations, and through the system bus 105, the functional block 106, the first and second control registers 11
It is possible to control 7,122. The memory control unit 103 includes the first and second MPUs 101 and 102,
The request from the function block 106 is sent to the system bus 105.
When it is received, the external memory 104 is controlled to read / write data, and the result is returned to the request source if necessary. The system bus 105 transmits a request from the request source to the request destination for all units connected thereto, and returns the result from the request destination to the request source.

The embodiment of the present invention described is, for convenience, the system bus 105 and each unit (101, 102, 103, 106, 117, 1) connected thereto.
In 22), it is assumed that all of the portions controlling the system bus 105 are operating with the local clock 116 for the memory control unit 103. However, in the present invention, the system bus 105 may be operated by the local clock of another unit, or a local clock dedicated to the system bus may be newly created and operated.

The second PLL 118 is the first PLL 10
The same operation as 8 is performed. That is, the second PLL 118
Uses the value of the second control register 122,
The reference clock 119 is multiplied and output to the fourth frequency divider 120. The fourth frequency divider 120 uses the value of the second control register 122 to generate the fourth frequency divider 1
The frequency-multiplied clock from 20 is divided to generate the local clock 121, and the functional block 106 and the DAC 1
Supply to 07. The function block 106 is configured by a dedicated logic specialized for processing that cannot be processed by the first and second MPUs 101 and 102. And
The function block 106 includes the first MPU 101 or the second MPU 101.
It is controlled by the MPU 102 of FIG. 1 to perform filtering processing of digital video images and digital audio, and encryption processing which cannot be implemented by software for tampering prevention.

In the above-described first embodiment of the present invention, the first and second MPUs 101 and 102 are caused to operate a program to be described later to control the control registers 117 and 122, and the first and second MPUs 101 and 102 are controlled. By changing the operating frequencies of the memory control unit 103 and the function block 106, the power consumption of the entire system is suppressed.

Although the example of the information processing apparatus shown in FIG. 1 described above includes two MPUs and one functional block, one or a plurality of MPUs and functional blocks are provided. Of course, only one of the MPU and the functional block may be provided.

Next, referring to FIGS. 2 and 3, first and second
The operations of the programs used by the MPUs 101 and 102 will be described. These programs are stored in the external memory 104 shown in FIG. 1, and are read and processed by the MPU as necessary. Further, these programs use a clock table shown in FIGS. 4 to 6 which will be described later, but this table is also stored in the external memory 104 and is read and processed by the MPU as necessary.

The clock table shown in FIG. 4 includes an application number item 401, a first MPU clock item 402, a second MPU clock item 403, a memory control block clock item 404, a functional block, and D.
It has AC and display clock items 405 as parameters, and these are the system parameter fields 40.
6, a first application parameter column 407, a second application parameter column 408, a sum value parameter column 409, and a maximum allowable amount parameter column 410.
It is stored and configured in. Further, this table is provided with a determination column 411 for each parameter.

The numerical values of the clock items 402 to 405 in the parameter columns 406 to 408 are the reference clock 109 or 119 and the local clock 11 shown in FIG.
2, 114, 116, 121, that is, a value corresponding to the product of the multiplication value by the first PLL and the frequency division values of the first to third frequency dividers, and the second value. It is a value corresponding to the product of the multiplication value by the PLL and the division value of the fourth frequency divider, and the value obtained by multiplying the frequency of the reference clock 109 or 119 by these values is the system and the first and second frequencies.
First and second MPU required by the application
The clock frequency in the memory control unit and DAC is shown. Here, when the value indicating the clock frequency is 0,
The corresponding application is the MP for that clock item.
It means that U etc. are not used.

The value of each clock item in the sum total value parameter column 409 is set to the reference clock 10
It is shown that the value multiplied by the frequency of 9 or 119 becomes the required clock frequency in the first and second MPUs, the memory control unit, and the DAC when the system and the first and second applications operate simultaneously. ing. further,
For each value in the parameter column 410 of the maximum allowable amount, a value obtained by multiplying this value by the frequency of the reference clock 109 or 119 is used as the first and second MPUs, the memory control unit, D
The AC indicates the maximum clock frequency at which the AC can operate, and the determination column 411 indicates whether or not the first and second MPUs, the memory control unit, and the DAC are operable in the state of the table.

When the processing described later with reference to FIG. 2 is executed and a third application is newly added and activated, a parameter column 501 for the third application is added to the table of FIG. 4 as shown in FIG. While being provided, the parameter column 409 of the total value is changed by the addition of an application and is changed to the parameter column 502. Further, when the processing described later with reference to FIG. 3 is executed and the second application is terminated, as shown in FIG.
The parameter column 408 for the second application is deleted from the table shown in (1) and the parameter column of the total value is changed to the parameter column 601.

The first and second MPUs, memory control unit, and D required by the first and second applications
Each application has a value that determines the clock frequency in AC inside thereof.

First, with reference to the flow shown in FIG. 2, a processing operation of a program used when newly adding and starting an application program in the embodiment of the present invention will be described.

(1) This processing program starts when a program activation request is issued by a user or the like, and first acquires an application number for a newly activated application (step 201).

(2) Next, at 202, a new column is created in the clock table shown in FIG. 4 stored in the external memory 104, and the new application number and the unique parameters 402, 403, 404, 4 of the application are held.
05 is stored and the clock table is updated. The parameter column 501 shown in FIG. 5 is a column for a newly created new application (step 202).

(3) With respect to the clock table updated in step 202, the sum of each parameter of parameters 402 to 405 is obtained, and the parameter column 409 of the sum value is updated to be the parameter column 502 (step 20).
3).

(4) It is judged whether or not all of the parameters in the parameter column 502 updated in the processing of step 203 exceed the values in the maximum allowable amount column 410, and if any one is exceeded, the step The new column 501 of the clock table created in 202 is deleted, the column 409 of the sum of parameter values is returned to the original value, and the processing here is finished.
In this case, the application for which the activation request is issued is determined to be inoperable in the current system state and is not activated (steps 204 and 205).

(5) If it is determined in step 204 that all the parameters in the updated parameter column 502 do not exceed the values in the maximum allowable amount column 410, the new sum total value of each parameter is stored in the table. , And sum value parameter 502 is updated (step 206).

(6) Next, the value of the control register for each PLL and frequency divider is changed based on the total sum value of each parameter updated in step 206, and each local clock 112, 114, 116, 121 is changed. Set the frequency. After that, a new application main body is activated (steps 207 and 208).

The example of the above-mentioned processing has been explained by assuming that when two applications are operating and the clock table is in a state as shown in FIG. 4, another application is added and activated. As can be seen from the above description, the clock table at the time of system start-up includes a system parameter column 406, a total value parameter column 409, a maximum allowable amount parameter column 410,
The configuration is such that only the determination column 411 for each parameter is provided, and each time an application is launched, the parameter column corresponding to those applications is added.

Next, with reference to the flow shown in FIG. 3, the processing operation of the program used to terminate the application program in the embodiment of the present invention will be described. The processing here is an example in the case where the second application is terminated after the processing described with reference to FIG.

(1) This processing program is started when an application to be terminated is designated by the user or the like. First, the application to be terminated is used to find the corresponding parameter column from the clock table of FIG.
Next, the parameter column is deleted from the clock table (steps 301 and 302).

(2) After that, parameters 402 to 405
The total sum value of each parameter is calculated again, and the parameter column 502 of the total value is updated to be the parameter column 601 (step 303).

(3) Next, the designated application program is terminated, and the sum value column 601 for each parameter is entered.
To update the value of the control register for each PLL and frequency divider, and to update each local clock 112, 114, 11
The frequencies of Nos. 6 and 121 are set to the predetermined frequencies, and the process ends (steps 304, 305).

According to the first embodiment of the present invention described above, each MPU and hardware function block can be set to operate at an appropriate operating frequency, and the power consumption of the entire system can be increased. It is possible to hold down.

FIG. 7 is a block diagram showing the hardware configuration of an information processing apparatus according to the second embodiment of the present invention, FIG. 8 is a flow chart for explaining the processing operation of a program used when starting the processing of stream data, FIG. 9 is a view for explaining the state of the clock table after the processing of the stream data is started in the processing of FIG. 8, and the second embodiment of the present invention will be described below with reference to these figures. In FIG. 7, reference numeral 701 is a stream data input block, and other symbols are the same as those in FIG.

A second embodiment of the present invention shown in FIG. 7 is configured by adding a stream data input block 701 to the system bus 105 in addition to the information processing apparatus according to the first embodiment shown in FIG. The data processing is made possible, and other configurations are the same as those in FIG. The stream data input block 701 added in the second embodiment performs a process of receiving data input such as digital video and audio from the outside at any time, and sending this to the external memory 104 via the system bus 105. is there.

The data such as digital video and audio from the outside may be, for example, a digital TV tuner, a radio tuner or the like outside the system. These data will be referred to as stream data below, but when processing such stream data, it is necessary to perform processing in accordance with the format used when the stream data was created on the transmission side. These formats are selected mainly due to the amount of data, the convenience of the transmitting side, and the like. When the receiving side is configured to support a plurality of formats, it needs to be configured to be able to determine which format this stream corresponds to. Generally, the plurality of formats have different processing capabilities required for each format.

The second embodiment of the present invention makes it possible to set an appropriate operating frequency each time the format of a stream is changed by using a program for executing the processing described with reference to FIG. Then, the processing when the processing of the external stream is started will be described with reference to the flow shown in FIG. Also in this process, FIG.
The clock table described in 1. is used, and the parameter column for the first application in this clock table corresponds to the stream data processing program in this processing.

(1) This processing program is started at the same time as the stream data processing program, and first determines whether or not the input stream format has been changed. If the input stream format has not been changed, the determination is repeated after a certain period of time. Perform (step 801).

(2) If it is determined in step 801 that the input stream format has been changed, a new input stream format parameter is stored in the field of the corresponding application. By this processing, the parameter column of the first application shown at 407 in FIG. 4 is changed to the parameter column of the application 1a shown as 901 in FIG. 9 to update the table (step 802).

(3) Next, regarding the clock table updated in step 802, parameters 402 to 405 are set.
The total sum of each parameter of
09 is updated to the parameter column 902 (step 8).
03).

(4) It is determined whether or not all of the parameters in the parameter column 902 updated in the process of step 803 exceed the values in the maximum allowable amount column 410. The updated column 901 of the clock table updated in 802 is deleted, the total sum value of each parameter in the total sum 902 of parameter values is recalculated, and the total sum value 902 of the clock table is updated. The process ends (steps 804 and 805).

(5) If it is determined in step 804 that all parameters do not exceed the maximum permissible amount, the control register values for each PLL and frequency divider are set based on the sum total value updated in step 803. The frequency of each local clock 112, 114, 116, 121 is changed to a predetermined value. After that, the processing operation in the new stream format is started, and the processing returns from step 801 (steps 806 and 807).

According to the second embodiment of the present invention described above, in addition to the effect of the first embodiment, it becomes possible to change the operating frequency in response to the format change of the input data from the outside. The power consumption of the entire system can be suppressed.

FIG. 10 is a block diagram showing the hardware configuration of an information processing apparatus according to the third embodiment of the present invention, FIG.
1 is a flowchart for explaining the processing operation of the program used to change the operating frequency when the power supply voltage changes, and FIG. 12 shows the state of the clock table after the operating frequency is changed in the processing of FIG. It is a figure, and below, a 3rd embodiment of the present invention is described with reference to these figures. In FIG. 10, 1001 is a battery,
1002 is a voltmeter, 1003 is a power supply monitor register, 1
Reference numeral 004 is a voltage storage register, and other reference numerals are the same as those in FIG.

The third embodiment of the present invention shown in FIG.
This is a voltmeter 1002 that measures the voltage of the battery 1001 by lowering the operating frequency of the entire processing device when the power supply voltage drops, thereby reducing power consumption.
And a voltage that stores the voltage value of the battery at the time of updating the clock table last time, which monitors the voltage measured by the voltmeter 1002 and supplies the signal to the system via the system bus 105. The storage register 1004 is configured in addition to the first embodiment of the present invention described with reference to FIG. 1, and other configurations are the same as those in FIG.

Normally, the voltage of the battery 1001 decreases as power is consumed. The voltmeter 1002 detects this voltage drop and reflects it in the power supply monitor register 1003 as needed. The register 1003 can be referenced by the first and second MPUs 101 and 102 via the system bus 105.

Next, the processing for changing the operating frequency when the power supply voltage fluctuates will be described with reference to the flow shown in FIG. The clock table described with reference to FIG. 4 is also referred to in this processing. The voltage storage register 1004 stores the voltage value of the battery when the clock table was last updated, that is, when the clock table was brought into the state shown in FIG.

(1) This processing program is started when the system is started, and when it is started, the value of the voltage monitor register 1003 is first read to determine whether or not the value of the voltage monitor register has been updated. The voltage monitor register 1003 constantly reflects the voltage change of the battery 1001, and when there is no change, the determination of whether or not it has been updated at regular intervals is continued (steps 1101 and 1102).

(2) If the value in the voltage monitor register is updated in the determination in step 1102, the value in the voltage save register 1004 that saves the voltage value of the battery at the time of the previous update of the clock table, The updated value of the voltage monitor register is compared to determine whether the value of the voltage monitor register is greater than the value of the voltage storage register by a certain amount or more (step 1103).

(3) If it is determined in step 1103 that the value of the voltage monitor register is not larger than the value of the voltage save register by a certain amount or more, whether the value of the voltage monitor register is less than the value of the voltage save register by more than a certain amount. Is judged,
If it is not smaller than a certain value, that is, if the difference is less than a certain value, it is determined that the change in voltage is not large enough to change the set value of the clock table, and the process from step 1101 is performed without changing anything. The process is returned to continue the processing (step 1107).

(4) If the value of the voltage monitor register is smaller than the value of the voltage storage register by a certain amount or more in the judgment in step 1107, the quotient of 2 of the values of the parameters that can be changed in the clock table is calculated, and the present Replace with the value.
As a result, the clock table shown in FIG. 4 is in the state shown in FIG. In this case, the value of the system parameter column 406 and the clock item 40 of the display
The value of 5 is an unchangeable value, the values of the parameter columns of the first and second applications are changed as shown by 1201 and 1202, and the parameter column 1204 of the maximum allowable amount is changed.
Is changed to a quotient of 2 and the total value column 1203 is recalculated (step 1108).

(5) After that, it is determined whether or not even one of the parameter values recalculated in step 1108 is 0, and if there is, the sum of the clock item values of the MPU required by the application. Is 0 or the value of the clock item 404 of the memory control block is 0, it is determined that the application cannot operate, the application is terminated, and the processing here is terminated (step 1109). 1110).

(6) If there is no parameter whose value is 0 in the determination in step 1109, the values of the control registers for the PLL and the frequency divider are updated and set, and the current value of the voltage monitor register is saved as a voltage. Register 100
4 and then returns to the processing from step 1101 to continue the processing (step 1111).

(7) If it is determined in step 1103 that the value of the voltage monitor register is larger than the value of the voltage save register by a certain amount or more, it is determined whether the value of the voltage monitor register is the maximum value (step). 1104).

In general, when the information processing apparatus is driven by a battery, the voltage of the battery decreases with time, so that the processing according to the flow described above is performed. Therefore, when the result of the determination in step 1103 is that the value of the voltage monitor register is larger than the value of the voltage storage register by a certain amount or more, when the battery is replaced or when the battery is in an alternating current state. It was when it came to be floated from the power supply.

(8) If it is determined in step 1104 that the value of the voltage monitor register does not reach the maximum value, it means that the voltage that has dropped has been recovered, so that the clock table can be changed. The parameter value is doubled and replaced with the current value, and the processing from step 1111 is continued. In this case, since the parameter value is set to at least ½ in the process of step 1108 described above, there is no problem even if the parameter value is doubled in the process here (step 1106).

(9) When the value of the voltage monitor register is the maximum value in the judgment of step 1104, each parameter of the clock table is returned to the initial value, and step 11
The processing from 11 is continued (step 1105).

According to the third embodiment of the present invention described above, in addition to the effect of the first embodiment, it becomes possible to change the operating frequency in response to the change in the voltage of the external power supply, and the consumption of the entire system is reduced. Power consumption can be suppressed and the operation time can be extended.

FIG. 13 is a block diagram showing the hardware arrangement of an information processing apparatus according to the fourth embodiment of the present invention, FIG.
4 is a flow chart for explaining the processing operation of the program for changing the power supply voltage according to the required clock frequency,
FIG. 15 is a diagram for explaining the configuration of the clock-voltage table used in the process of FIG. 14, and the fourth embodiment of the present invention will be described below with reference to these diagrams. FIG.
1301 is a DC-DC converter, 1302
Is a voltage setting register, and other symbols are the same as those in FIG.

The fourth embodiment of the present invention shown in FIG. 13 is
It is possible to reduce the power consumption of the processing device by changing the voltage supplied to each block constituting the processing device based on the value in the parameter column of the total value in the clock table described above. In the first embodiment of the present invention described with reference to FIG. 1, a DC-DC converter 1301 and a voltage setting register 1302 are provided. The DC-DC converter 1301 determines the power supply voltage using the set value of the voltage setting register 1302, and supplies the power supply having this voltage to all the blocks shown in FIG. The voltage setting register 1302 is
First and second MPU 10 via the system bus 105
1 and 102 are accessible, and these MPUs
It is possible to control from.

Next, the processing operation of the program for changing the power supply voltage according to the required clock frequency will be described with reference to the flow shown in FIG. In this process, as shown in FIG.
The clock-voltage table shown in is used. In FIG. 15, 1501 is the maximum value in the parameter column of the total value in the clock table, and 1502 is the corresponding voltage setting register value.

(1) This processing program is started when the system is started, and when it is started, it is first determined whether the clock table described with reference to FIG. 4 has been updated,
The determination as to whether the clock table has been updated is repeated until the update is performed (step 1401).

(2) After that, the maximum value is selected from the parameter column 409 of the total value in the clock table. The maximum value in the parameter column 409 is 16, and then the voltage value for the maximum value is obtained from the clock-voltage table shown in FIG. In this case, the minimum value of the total sum maximum value 1501 exceeding the maximum value 16 in FIG. 15 is 20, so the corresponding voltage setting register value 15
The voltage register setting value obtained from 02 is 19 (steps 1402 and 1403).

(3) Next, it is determined whether or not the value obtained in step 1403 is the same as the current voltage register setting value. If the values are the same, the process returns to step 1401 and the above-described processing is repeated. If different, a new value is set in the voltage setting register (step 1405).

According to the fourth embodiment of the present invention described above, in addition to the effect of the first embodiment, it becomes possible to change the power supply voltage in accordance with the operating frequency, and the power consumption of the entire system is further improved. Can be held down.

Although the first to fourth embodiments of the present invention have been described above, the present invention can also be configured by combining a plurality of these first to fourth embodiments.

[0074]

As described above, according to the present invention, a functional block such as an MPU is provided with an appropriate frequency so that sufficient processing capacity can be realized for an operating application and operation can be performed with minimum power consumption. It can be operated by an operating voltage, and the power consumption of the information processing device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of an information processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation of a program used when an application program is added and started.

FIG. 3 is a flowchart illustrating a processing operation of a program used when an application program ends.

FIG. 4 is a diagram illustrating a clock table used in the process of FIG.

5 is a diagram illustrating a state of a clock table after an application is additionally activated in the process of FIG.

FIG. 6 is a diagram illustrating a state of the clock table after the application is terminated in the process of FIG.

FIG. 7 is a block diagram showing a hardware configuration of an information processing device according to a second embodiment of the present invention.

FIG. 8 is a flowchart illustrating a processing operation of a program used when starting processing of stream data.

9 is a diagram illustrating a state of the clock table after the processing of stream data is started in the processing of FIG.

FIG. 10 is a block diagram showing a hardware configuration of an information processing device according to a third embodiment of the present invention.

FIG. 11 is a flowchart illustrating a processing operation of a program used to change the operating frequency when the power supply voltage changes.

12 is a diagram illustrating a state of the clock table after the operating frequency is changed by the process of FIG.

FIG. 13 is a block diagram showing a hardware configuration of an information processing device according to a fourth embodiment of the present invention.

FIG. 14 is a flowchart illustrating a processing operation of a program for changing a power supply voltage according to a required clock frequency.

15 is a diagram illustrating a configuration of a clock-voltage table used in the process of FIG.

[Explanation of symbols]

101, 102 First and second microprocessor units (MPU) 103 External memory control unit 104 External memory 105 System bus 106 Functional block 107 Digital-analog converter (DAC) 108, 118 First and second phase-locked loop ( PLL) 111, 113, 115, 120 First to fourth frequency dividers 117, 122 First and second control registers 701 Stream data input block 1001 Battery 1002 Voltmeter 1003 Power supply monitor register 1004 Voltage save register 1301 DC- DC converter 1302 voltage setting register

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroaki Nakata             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory (72) Inventor Koji Hosoki             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory F term (reference) 5B011 DA06 FF02 GG02 LL02 LL13                 5B079 BA01 BC01

Claims (7)

[Claims] 1. An information processing apparatus comprising one or a plurality of processors and / or one or a plurality of functional blocks having dedicated logic, wherein the operating frequencies of the processors and the functional blocks are independently changed. Based on the optimum operating frequency information for each of the processor and the functional block of each of the means and one or more applications running on the information processing device,
Determine the operating frequency of the processor, functional block,
An information processing apparatus comprising: a control unit that controls the unit that changes the operating frequency. 2. The control means, when an application is started, acquires the operation status from the management means that manages the current operation status of the information processing apparatus, and has a processing capacity required for the application to be started by a processor, The information processing apparatus according to claim 1, wherein the information processing apparatus is assigned to a functional block, and the operating frequencies of the processor and the functional block are changed. 3. The control means, when the application is terminated, acquires the operation status from the management means that manages the current operation status of the information processing apparatus, and determines the processing capacity assigned to the application to be terminated. The information processing apparatus according to claim 1, wherein the operating frequencies of the processor and the functional block are changed by deleting the operating frequency of the processor and the functional block. 4. A main power supply such as a battery, and a measuring means for measuring the voltage thereof, wherein the control means operates the operating frequency of the processor and the functional block at the power supply voltage measured by the measuring means. The information processing apparatus according to claim 1, wherein the frequency is set to a possible frequency. 5. The apparatus further comprises means for receiving a formatted data input from the outside, wherein the control means is adapted to set the operating frequency of the processor and the functional block according to the data format of the data input. The information processing apparatus according to claim 1, wherein the information processing apparatus is set to an operating frequency. 6. Further comprising means for changing the power supply voltage,
The control means applies, to the processor and the functional block, a voltage that allows the processor and the functional block to operate at a sum of operating frequencies required by one or more applications that are currently operating. The information processing apparatus according to any one of claims 1 to 5, characterized in that the means for changing the power supply voltage is controlled so as to do so. 7. A method of controlling an information processing device, comprising one or more processors, and / or one or more functional blocks having dedicated logic, and one or more applications operating on the information processing device. Of each of the processor, based on the optimum operating frequency information for each of the functional block, the processor,
Determining the operating frequency of the functional block, the processor,
A method for controlling an information processing device, characterized in that the operating frequencies of the respective functional blocks are changed independently.