JP2005085164A - Control method for multiprocessor system, and multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system determining the best operating point in consideration of both electric power consumption and processing performance. <P>SOLUTION: A control circuit 10 calculates necessary throughput in response to a job throughput estimated by a job throughput estimating part 11. The control circuit 10 selects a precedently calculated optimum operating point from an operating point LUT 12. In consideration of that electric power consumption of a processor is proportional to a square of an operating voltage and a frequency, and throughput is proportional to the frequency, operating points wherein electric power consumption is optimum with respect to necessary throughput are calculated and stored in the operating point LUT 12. The control circuit 10 operates only a necessary number of processor cores 17a-17d. The control circuit 10 controls a PLL 13 in response to an operating frequency of the operating point to supply a clock of a desired frequency, or an optimum operating voltage in response to an operating voltage of the operating point to the processor cores 17a-17d. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a control method for a multiprocessor system having a plurality of processors and a multiprocessor system.

  With the recent rapid development of semiconductor technology, the number of gates built in one large-scale integration (LSI) has increased dramatically. With the progress of such semiconductor technology, it becomes possible to mount a plurality of processor cores on one chip, and these LSIs are called CMP (Chip Multi Processor).

  As a technique for reducing power consumption in a multiprocessor system having a plurality of processors such as CMP, a degeneration operation is known. The degeneration operation is an operation that gradually reduces the processing capacity of the CPU as necessary in order to reduce power consumption. The following two methods are known as methods for realizing a method for controlling a degeneration operation in a multiprocessor system.

  In the first method, the operations of some of the plurality of processor cores are stopped as necessary. In order to stop the operation of the processor core, the supply of the clock is stopped or the supply of the operating voltage is stopped. A configuration example of such a multiprocessor system is shown in FIGS.

  As shown in FIG. 8, the conventional multiprocessor system 21 is configured to turn on and off the power supply from the power supply 23 to the processor cores 24 a to 24 d by the control circuit 22.

  Further, as shown in FIG. 9, the conventional multiprocessor system 25 is configured to turn on and off the clock supply from the oscillation circuit 27 to the processor cores 29a to 29d by the control circuit 26 and the Gating (gating) circuits 28a to 28d. It is.

  Here, it is assumed that each processor core has an equivalent processing capability and is symmetric. One processor core has three types of operating frequencies and operating voltages, that is, operating points. Hereinafter, the power consumption and processing performance per processor core will be described by appropriately normalizing them based on the case of the maximum operating voltage and the maximum operating frequency.

  In the multiprocessor systems 21 and 25 shown in FIGS. 8 and 9, the operating voltage and the operating frequency are not changed, and only the number of processor cores to be used is changed. For this reason, the relationship between the power consumption and the processing performance during the degenerate operation in this configuration is such that the processing capacity and the power consumption change in proportion to the number of operating processor cores, as shown in FIG. .

  As described above, for example, Patent Documents 1 and 2 disclose a method of changing the number of operating processor cores as required by stopping the operation of the processor cores by stopping the supply of clocks or the supply of power supply voltage. Has been described.

  Further, as a second method for realizing the degenerate operation, there is a method in which the operating voltage and operating frequency of the multiprocessor system are made variable as necessary. An example of such a multiprocessor system is shown in FIG.

  In the multiprocessor system 31, the control circuit 32 controls the PLL 33 and the programmable power supply 35 in accordance with required processing capability or in accordance with desired power consumption. The PLL 33 changes the clock frequency output from the oscillation circuit 34 (multiple A / B). The programmable power supply 35 outputs a desired output voltage. In general, when this degeneration operation control method is used, the operating voltage is lowered and the operating frequency is lowered. This is due to the nature of the semiconductor device.

Here, the power consumption P of LSI when m processor cores are used, the capacity per processor core is Cpe,
P = Cpe x (rv x V) ² x (rf x f) x m
Given in. However, the ratio rv (0 <rv ≤ 1) between the maximum operating voltage and the current operating voltage and the ratio rf (0 <rf ≤ 1) between the maximum operating frequency and the current operating frequency are used. The operating voltage was (rv × V) and the operating frequency was (rf × f).

In addition, the processing capability X of the multiprocessor system at this time is assumed that the processing capability per processor core is Xpe.
X = Xpe × m × rf
Given in.

  In the multiprocessor system 31, the number of processor cores to be operated is fixed to 4, and the three operating points are (operating frequency, operating voltage) = (700MHz, 1.65V), (500MHz, 1.5V), (300MHz, 1.25V FIG. 12 shows the relationship between power consumption and processing capacity. The values of these three operating points were the values actually used in Crusoe's LongRun Technology by Transmeta.

  Such a method is described in Patent Documents 2, 3, and 4, for example. For example, Intel (registered trademark) SpeedStep Technology and the above-mentioned Transmeta LongRun Technology are control technologies that realize the above-described degeneration operation, and can naturally be applied to a multiprocessor system, and thus CMP.

  The two methods described above are basic methods for realizing the degenerate operation, and many application methods have been proposed. Furthermore, a method for controlling the degeneration operation combining the above two methods has been proposed.

Note that Patent Document 5 discloses a configuration in which heat generation is reduced by reducing the CPU processing capacity and power consumption depending on the ambient temperature and the semiconductor temperature.
JP 2000-47872 A (publication date: February 18, 2000) JP 2001-67149 A (publication date: March 16, 2001) JP 2000-66776 A (publication date: March 3, 2000) JP 2002-99433 A (publication date: April 5, 2002) JP-A-8-314578 (Publication date: November 29, 1996)

  However, in the conventional method for realizing the degeneration operation, a method for determining the operation point of the degeneration operation in view of the effective use of power consumption and processing capacity has not been proposed, and the optimum operation point is not necessarily selected. Arise.

  That is, in the conventional method for realizing the degeneration operation, although many methods for making the processing capacity and power consumption variable have been proposed, the best operation of the degeneration operation in consideration of both the processing capacity and power consumption. No method for determining points has been proposed.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an optimal operating point and the number of operating processors in consideration of processing capability and power consumption in a multiprocessor system in which processing is assigned to each processor core. It is an object to provide a control method for a multiprocessor system and a multiprocessor system.

In order to solve the above problems, a multiprocessor system control method according to the present invention includes a job processing step of supplying a power supply voltage and a clock to a plurality of desired processors to process a job. In the control method, the first operating point and the second operating point among the operating points that determine the power supply voltage and the clock frequency to be supplied to the processor in the job processing step are the operations at the second operating point. Voltage / operating voltage at the first operating point = rv, operating frequency at the second operating point / operating frequency at the first operating point = rf, m1 the number of processor cores to be operated at the first operating point, and operating at the second operating point the number of processor cores when the m2, if ^{rv 2 × rf <m1 / m2} ≦ rf is satisfied, include a selection step than the first operating point to select a second operating point It is characterized in that there.

  In order to solve the above problems, a multiprocessor system control method according to the present invention includes a job processing step of supplying a power supply voltage and a clock to a plurality of desired processors to process a job. In the control method, for an operating point that determines the power supply voltage to be supplied to the processor and the frequency of the clock in the job processing step, a set of operating points having a higher frequency of the power supply voltage and the clock 1 operation mode, a set of operation points having the lower frequency of the power supply voltage and the clock as a second operation mode, the operation point of the second mode is selected, and the operation point of the first mode is The processing capacity obtained according to the number of processor cores to be operated, the power supply voltage and the frequency of the clock Is characterized in that it contains an operating point selection step of selecting is higher than the throughput in the case of using the maximum number of processor cores that can be used in the second operation mode.

  In order to solve the above-described problems, the multiprocessor system control method according to the present invention is configured so that, in the above configuration, the selection process is performed before a job to be processed in the job processing process is input to the multiprocessor system. Is executed in advance, and the operating point and the number of processor cores to be operated are selected.

  In order to solve the above-described problem, the multiprocessor system control method according to the present invention is configured so that, in the above configuration, the operation point is set before the job to be processed in the job processing step is input to the multiprocessor system. The selection step is executed in advance, and the operating point and the number of processor cores to be operated are selected.

  In order to solve the above problems, a control method of a multiprocessor system according to the present invention includes a processing amount calculation step for calculating a processing amount of a job to be processed and a processing calculated in the processing amount calculation step in the above configuration. And determining the operation point to be selected from the operation points selected in the selection step according to the required processing capability. However, it is a distributed processing step that realizes the operation point determined in the determination step and causes the processor core to be operated to uniformly distribute the job.

  In order to solve the above problems, a control method of a multiprocessor system according to the present invention includes a processing amount calculation step for calculating a processing amount of a job to be processed and a processing calculated in the processing amount calculation step in the above configuration. An operation point determination step for estimating a required processing capacity according to the amount, and further determining an operation point to be selected from the operation points selected in the operation point selection step according to the required processing capacity, The job processing step is a distributed processing step that realizes the operation point determined in the operation point determination step and causes the processor core to be operated to uniformly distribute the job.

  In order to solve the above problems, a multiprocessor system according to the present invention is a multiprocessor system having a plurality of processors, a clock supply unit that supplies a clock to the processor core, and a power supply that supplies a power supply voltage to the processor core A voltage supply unit; and a control circuit that controls at least one of on / off of supply of the clock from the clock supply unit to the processor core and on / off of supply of the power supply voltage from the power supply voltage supply unit to the processor core And the control circuit causes the operation point selected by the selection step in the control method of the multiprocessor system according to claim 1 or the operation point selection step in the control method of the multiprocessor system according to claim 2 to operate. Stores a set of processor cores By referring to the storage unit, and controls the frequency of the clock supplied the clock supply unit, is characterized by controlling the power supply voltage supplied to the power voltage supply unit.

  In order to solve the above problems, a multiprocessor system according to the present invention is characterized in that it is configured on one semiconductor chip in the above configuration.

  In order to solve the above problems, a multiprocessor system according to the present invention includes a job processing amount estimation unit that estimates a processing amount of a job before actually processing the input job in the above configuration, and the control circuit Calculates the required processing capacity according to the processing amount of the job estimated by the job processing amount estimation unit, and refers to the storage unit according to the required processing capability, and the operating point and the operation The number of processor cores to be determined is determined, and the job is equally distributed to the processor cores to be operated according to the determination.

The multiprocessor system control method according to the present invention provides a second operating point for the first operating point and the second operating point among the operating points for determining the power supply voltage and the clock frequency to be supplied to the processor in the job processing step. Operating voltage at operating point / Operating voltage at first operating point = rv, Operating frequency at second operating point / Operating frequency at first operating point = rf, Number of processor cores operated at first operating point, m1, Second operating point When m2 is the number of processor cores to be operated at a point, if rv ² × rf <m1 / m2 ≦ rf is satisfied, a selection step for selecting the second operating point over the first operating point is included. It is a configuration.

  Here, the operating point determines a power supply voltage and a clock frequency to be supplied to the processor, and means a set of the operating voltage and the operating frequency. The power consumption and processing capability of one processor are determined by the operating voltage and the operating frequency supplied. According to the above configuration, it is possible to select a set of an optimal operating point and the number of processor cores to be operated that minimize power consumption for the following reasons.

  First, for the sake of simplicity, it is assumed that the processing capability of each processor is uniform in the above-described multiprocessor system. Further, it is assumed that processing is equally distributed to each processor to be operated. For example, the processing in each processor can be made equal by distributing the data to be processed equally. Note that the configuration of the multiprocessor system is not limited to this, and when the processing capability of the processor is not uniform, data may be distributed in proportion to the processing capability so that the processing is uniform. .

According to the above configuration, for the first operating point and the second operating point arbitrarily selected from the operating points of the multiprocessor system, the operating frequency of the first operating point is f and the operating voltage of the first operating point is When v is the capacity value of one processor and Cpe is used, the power consumption P1 when m1 processor cores are used is given by P1 = Cpe × V ² × f × m1. Further, when the operating frequency of the second operating point is (rf × f) and the operating voltage of the second operating point is (rv × V), the consumption when using m2 processor cores at the second operating point. The power P2 is given by P2 = Cpe × (rv × V) ² × (rf × f) × m2.

  On the other hand, when the processing capability of one processor core is Xpe, the processing capability X1 when m1 processor cores are used at the first operating point is given by X1 = Xpe × m1. Further, the processing capability X2 when m2 processor cores are used at the second operating point is given by X2 = Xpe × m2 × rf.

Therefore, considering the case where the second operating point is preferable to the first operating point and the power consumption is small and the processing capability is large, P1> P2 and X1 ≦ X2 are obtained as conditions. From this condition, rv ² × rf <m1 / m2 ≦ rf is obtained by equation transformation.

That is, if rv ² × rf <m1 / m2 ≦ rf, it is guaranteed that the second operating point consumes less power and has a higher processing capacity than the first operating point.

  Therefore, if the second operation point is selected instead of the first operation point in the selection step for use in the job processing step under the above conditions, and the job is processed in the job processing step based on this selection, Power consumption can be reduced and job processing can be completed in a short time due to its large processing capacity.

  Therefore, after submitting a job for processing, if a processing step is executed by estimating the processing capacity required for processing the job, and the job is processed in the job processing step based on this selection, for example, It becomes possible to operate the multiprocessor system with the minimum power consumption for the processing capacity actually required. When there are three or more operating points to be selected, for example, two operating points may be sequentially selected in ascending order of operating voltage and operating frequency, and the operating point may be determined as described above.

  Therefore, it is possible to provide a method for determining an operating point capable of operating a multiprocessor system at the best operating point in view of both processing capability and power consumption.

  Note that the above-described multiprocessor system control method allocates processing by estimating information (such as operating points) necessary for job allocation before actual job processing. This corresponds to a simple allocation. On the other hand, dynamic allocation is also known that changes the status of job allocation during actual job processing. In this case, however, allocation processing, monitoring processing, and the like are required. Don't be.

Further, the above-described control method of the multiprocessor system can be expressed as follows. That is, the multiprocessor system includes a clock supply control unit for each processor core, a variable frequency clock supply unit for the processor core, and a variable operation voltage supply unit for the processor core. The processing amount is evenly distributed, has at least two operating points with different operating voltages and operating frequencies, and sets the operating point with the higher operating voltage and operating frequency as the first operating point, and the operating voltage and operating frequency. The lower operating point is the second operating point, the operating voltage of the second operating point / the operating voltage of the first operating point = rv, the operating frequency of the second operating point / the operating frequency of the first operating point = rf, the number of processor cores to operate in one operating point m1, the number of processor cores to operate in the second operating point is taken as m2, if ^{rv 2 × rf <m1 / m2} ≦ rf is satisfied, the operating point 1 Instead, it is configured to control and select the operating point 2, and can be expressed.

  Further, the control method of the multiprocessor system according to the present invention is such that the power supply voltage and the clock having the higher frequency are operating points that determine the power supply voltage and the clock frequency to be supplied to the processor in the job processing step. A set of operating points is set as a first operating mode, a set of operating points with the lower frequency of the power supply voltage and the clock is set as a second operating mode, the operating point of the second mode is selected, and the first mode is selected. When the maximum number of processor cores that can be used in the second operation mode is used, the processing capability obtained in accordance with the number of processor cores to be operated and the frequency of the power supply voltage and the clock is used. This is a configuration including an operating point selection step that is selected when the processing capability is higher.

  Here, the operating point determines a power supply voltage and a clock frequency to be supplied to the processor, and means a set of the operating voltage and the operating frequency. The power consumption and processing capability of one processor are determined by the operating voltage and the operating frequency supplied.

  When a semiconductor device is used as a processor, the operating frequency increases as the operating voltage increases due to the characteristics. The power consumption of the processor increases in proportion to the product of the square of the voltage and the frequency, while the processing capacity increases in proportion to the frequency. For this reason, the lower the operating voltage and the operating frequency, the lower the power consumption per processing capacity is expected.

  Therefore, an operating point included in the second operation mode having a low operating voltage and operating frequency is selected regardless of the number of processor cores to be operated. In other words, among the operating points of the first operation mode, operating points having a processing capability lower than the processing capability when using the maximum number of processor cores that can be used in the second operating mode are not used. In this way, the power consumption can be reduced as compared with the case where the operating point of the first operation mode that gives the same processing capability is selected. Note that the processing capability can be estimated as the processing capability X is proportional to (m × f) when the operating point (the operating frequency f, the operating voltage v), and the number m of processor cores to be operated are, for example.

  Further, in order to obtain a processing capability higher than that when using the maximum number of processor cores that can be used in the second operation mode, the operating point of the first operation mode having a processing capability higher than this processing capability. Select.

  As described above, if the operation point selection step is performed for the operation point of the first operation mode and the operation point of the second operation mode, and the job is processed in the job processing step based on this selection, the power consumption can be further reduced. In addition, job processing can be completed in a short time due to its large processing capacity.

  In addition, after submitting a job for processing, if the processing point selection process is executed by estimating the processing capacity required for processing the job, and the job is processed in the job processing process based on this selection, For example, the multiprocessor system can be operated with the minimum power consumption for the processing capacity actually required.

  Therefore, it is possible to provide a method for determining an operating point capable of operating a multiprocessor system at the best operating point in view of both processing capability and power consumption.

  Note that the above-described control method of the multiprocessor system can also be expressed as follows. That is, the multiprocessor system includes clock supply control means for each processor core, variable frequency clock supply means for the processor core, and variable operating voltage supply means for the processor core, and the operating voltage and operating frequency are different. It has at least two operating points and distributes the processing amount evenly to the processor cores to be operated. A set of operating points having a higher operating voltage and operating frequency is set as operating mode 1, and the operating voltage and operating frequency are set. When the set of operation points with lower values is set as the operation mode 2, the operation point of the operation mode 1 having a processing capability lower than the processing capability at the time of the maximum processor core operation in the operation mode 2 is not selected as the operation point. It can also be expressed as.

  Further, in the above-described configuration, the multiprocessor system control method according to the present invention executes the selection step in advance before a job to be processed in the job processing step is input to the multiprocessor system. The configuration may be such that the operating point and the number of processor cores to be operated are selected. Also, before the job to be processed in the job processing step is submitted to the multiprocessor system, the operation point selection step is executed in advance to select the operation point and the number of processor cores to be operated. It may be configured to be kept.

  If a set of operating points determined in this way and the number of processor cores to be operated is stored in, for example, an LUT (Look Up Table), the necessary processing capacity is estimated, and then the LUT is referred to immediately after estimating the required processing capacity. An optimum operating point and the number of processor cores to be operated can be obtained. Further, it is possible to easily obtain the optimum operating point and the number of processor cores to be operated without hindering job processing in the job processing step.

  Note that the above-described control method can also be expressed as a configuration including a step of determining a set of operating points to be selected in advance according to necessary processing capability.

  In addition, the control method of the multiprocessor system according to the present invention requires the processing amount calculation step for calculating the processing amount of the job to be processed and the processing amount calculated in the processing amount calculation step in the above configuration. And a determination step for determining an operation point to be further selected from the operation points selected in the selection step according to the required processing capability, and the job processing step is included in the determination step. The operation point determined in this way may be realized, and the processing core may be a distributed processing step that uniformly distributes the job to the operating processor core. Also, a processing amount calculation step for calculating the processing amount of the job to be processed, and a necessary processing capacity is estimated according to the processing amount calculated in the processing amount calculation step, and the operation point is determined according to the necessary processing capacity. An operation point determination step for determining an operation point to be further selected from the operation points selected in the selection step, and the job processing step realizes the operation point determined in the operation point determination step. A configuration may be a distributed processing step in which the above-described job is uniformly distributed to the processor core to be operated.

  According to the above configuration, optimal data processing in the multiprocessor can be reliably realized.

  That is, in the above configuration, in the processing amount calculation step, for example, the amount of data to be processed is estimated. The processing time required for processing is determined in advance according to the content of the processing, for example. For example, when printing is performed by performing image processing, the processing time may be determined according to the time limit of the actual image forming process. In the operating point determination step, for example, the necessary processing capacity is estimated by dividing the amount of data to be processed by the processing time. Then, the optimum operating point having a processing capacity higher than the estimated processing capacity is extracted by the method described above. In the distributed processing step, in order to realize the extracted optimum operating point and number of operating processors, for example, data is evenly distributed to each processor and is processed uniformly.

  When the processing capabilities of the processors are different, the amount of jobs and the amount of data to be input may be proportionally distributed according to the processing capabilities of the processors. Such a configuration can be applied to an image processing system including, for example, a multiprocessor system, and an image processing system that divides an image to be processed into processor cores.

  Further, the control method having the above-described configuration includes the step of predicting the processing amount of the job in advance before the job processing starts, the step of determining the operating point using the control method described above, and the job equally for each processor. It can also be expressed as a configuration including a step of distributed processing by the core.

  In order to solve the above problems, a multiprocessor system according to the present invention includes a clock supply unit that supplies a clock to a processor core, a power supply voltage supply unit that supplies a power supply voltage to the processor core, and the clock supply unit. A control circuit that controls at least one of on / off of supply of the clock from the power supply to the processor core and on / off of supply of the power supply voltage from the power supply voltage supply unit to the processor core, and the control circuit includes: With reference to the storage unit storing the set of the operation point selected by the selection step in the control method of the multiprocessor system described above or the operation point selection step in the control method of the multiprocessor system described above and the number of processor cores to be operated, Controls the frequency of the clock supplied by the clock supply unit. It is configured to control the power supply voltage supplied to the power voltage supply unit.

  In the above multiprocessor system, a single processor operates when a clock is supplied from a clock supply unit and a power supply voltage is supplied from a power supply voltage supply unit. In addition, the control circuit controls the on / off of the supply of the clock from the clock supply unit to the processor core, or the on / off of the supply of the power supply voltage from the power supply voltage supply unit to the processor core. Selected.

Here, in a processor to which a clock and a power supply voltage are supplied, the power consumption and processing capability of the processor are determined by the power supply voltage (operating voltage) and the clock frequency (operating frequency) supplied to the processor. The control circuit controls the operating voltage and the operating frequency supplied to the processor with reference to the operating point determined using the above-described multiprocessor system control method and the number of processor cores to be operated. If the job is processed in this state, for example, the multiprocessor system can be operated with the minimum power consumption for the required processing capacity.

  In addition, a set of the operating point determined in this way and the number of processor cores to be operated is stored in a storage unit such as an LUT (Look Up Table), and the necessary processing capacity is estimated, and then the storage unit is referred to Therefore, the optimum operating point and the number of processor cores to be operated can be obtained immediately. Further, it is possible to easily obtain the optimum operating point and the number of processor cores to be operated without hindering job processing in the job processing step.

  Note that the multiprocessor system is expressed as a configuration having a lookup table in which a set of operating points of the multiprocessor system is determined and stored in advance using the above-described multiprocessor system control method. You can also.

  Further, the multiprocessor system according to the present invention may be configured on one semiconductor chip in the above configuration.

  Here, being configured on one semiconductor chip means that it is configured as a single chip that is not separable, for example, not a discrete semiconductor chip connected on a connection substrate. means.

  Since the multiprocessor system performs job processing at the operating point determined by the control method of the multiprocessor system, the multiprocessor system can be operated with minimum power consumption for a certain amount of processing. Therefore, a multiprocessor system configured on one semiconductor chip can be operated with a minimum heat generation amount. For this reason, the heat dissipation of the semiconductor chip can be made easier, and the possibility of malfunction or failure of the semiconductor chip can be reduced.

  The multiprocessor system according to the present invention further includes a job processing amount estimation unit that estimates a processing amount of a job before actually processing the submitted job in the above configuration, and the control circuit includes the job processing amount. The required processing capacity is calculated according to the processing amount of the job estimated by the estimation unit, and the operating point and the number of processor cores to be operated are determined by referring to the storage unit according to the required processing capacity. A configuration may be used in which the job is uniformly distributed to the processor cores that are determined and operated according to the determination.

  With this configuration, the job can be processed with the optimum power consumption for the required processing capacity. Note that to evenly distribute jobs to processor cores to be operated includes, for example, when image processing is performed on predetermined image data, image data is evenly distributed to processor cores with equal processing capabilities. .

  It should be noted that the above-described multiprocessor system predicts the processing amount of the job in advance before job processing starts, determines the operating point using the control method of the multiprocessor system described above, and distributes the job equally to each processor. It can also be expressed as having a control unit that causes the core to perform distributed processing.

  An embodiment of the present invention will be described below with reference to FIGS.

  The multiprocessor system according to the present embodiment is a control unit of the image forming apparatus. The control unit performs a predetermined setting operation so as to reduce power consumption during image processing.

  As shown in FIG. 2, the image forming apparatus 1 of this embodiment includes a control unit (multiprocessor system) 2, a memory 3, an image reading unit 4, an image forming unit 5, a communication unit 6, and an operation unit 7. .

  The control unit 2 controls the image forming apparatus 1. The control unit 2 of this embodiment is formed on one semiconductor chip. The control unit 2 will be described later.

  The memory 3 is a storage device of the image forming apparatus 1.

  The image reading unit 4 is for reading an image of a document. The image reading unit 4 outputs the read image data of the document to the control unit 2. The control unit 2 stores the image data in the memory 3.

  The image forming unit 5 is for printing on a print sheet according to image data. The image forming unit 5 carries out the print sheets accumulated in a tray (not shown) of the image forming unit 5 at a predetermined timing under the control of the control unit 2. Then, the image forming unit 5 prints on the print sheet according to the image data read from the memory 3 by the control unit 2 and subjected to predetermined image processing.

  The communication unit 6 is an input / output interface of the image forming apparatus 1. The image forming apparatus 1 can also print image data input from the outside via the communication unit 6 and accumulated in the memory 3. The image forming apparatus 1 can also output image data read by the image reading unit 4 to the outside via the communication unit 6.

  The operation unit 7 is a user interface of the image forming apparatus 1. The image forming apparatus 1 performs, for example, reading of a document by the image reading unit 4 or printing by the image forming unit 5 in accordance with a user instruction detected by the operation unit 7.

  Here, the control unit 2 will be described in detail. The control unit 2 of the present embodiment functions as an image processing unit that performs predetermined image processing on image data read by the image reading unit 4 and stored in the memory 3. The control unit 2 performs a degeneration operation for reducing power consumption during image processing as follows. Here, the degeneration operation is an operation for reducing the processing capacity as necessary in order to reduce power consumption.

  As shown in FIG. 2, the control unit 2 includes a control circuit 10, a job processing amount estimation unit 11, an operating point LUT (storage unit) 12, a PLL (clock supply unit) 13, an oscillation circuit (clock supply unit) 14, and a programmable unit. A power supply (power supply voltage supply unit) 15, Gating circuits 16 a to 16 d, and processor cores (processors) 17 a to 17 d are provided. A control signal is input / output to / from the control unit 2 via a predetermined control circuit 10 and a data signal is input / output via the bus line B.

  The control circuit 10 controls the control unit 2. The control circuit 10 will be described later.

  The job processing amount estimation unit 11 is a processing unit for estimating in advance the amount of a job to be processed by the control unit 2 as an image processing unit before actual processing after the job is submitted.

  An operating point LUT (Look Up Table) 12 is a storage element. The operating point LUT 12 of this embodiment stores a set of operating points selected by a predetermined selection process and the number of processors to be operated when realizing the operating points as a look-up table (LUT). . The process for selecting the contents to be stored in the operating point LUT 12 will be described later. The control circuit 10 accesses the operating point LUT 12, extracts a stored operating point set, etc., and selects an optimal operating point according to the required processing capability.

  A PLL (Phase Locked Loop) 13 changes the clock frequency output from the oscillation circuit 14 (desired A / B times). The oscillation circuit 14 oscillates a clock having a predetermined frequency.

  The programmable power supply 15 outputs a desired power supply voltage. The Gating circuits 16a to 16d turn on and off the clocks respectively supplied from the PLL 13 to the processor cores 17a to 17d in accordance with a control signal (enable signal) from the control circuit 10.

  The processor cores 17a to 17d are processors that perform processing with a predetermined processing capability according to a supplied clock frequency (operating frequency) and power supply voltage (operating voltage). Each processor core 17a-17d of this embodiment has the same processing capability. In the present embodiment, the processor cores 17a to 17d are supplied with clocks having the same power supply voltage and the same frequency, as described above. The processor cores 17a to 17d are connected to each other via a bus line B.

  Here, the control circuit 10 will be described. When the control unit 2 performs image processing, the control circuit 10 of the present embodiment estimates the processing capability required for image processing, and then operates with the least power consumption according to the required processing capability. The number of processors used is selected, and the respective processor cores 17a to 17d are processed. The processing capacity estimation will be described later.

  The control circuit 10 adjusts the operating frequency by controlling the PLL 13 according to the required processing capability or according to the power consumption to be operated. The control circuit 10 controls the programmable power supply 15 to adjust the operating voltage. In addition, the control circuit 10 controls on / off of each of the processor cores 17a to 17d by a control signal to the Gating circuits 16a to 16d.

  On the other hand, the PLL 13 changes the clock signal from the oscillation circuit 14 to a desired frequency according to the control signal from the control circuit 10 and outputs it to the Gating circuits 16a to 16d. Moreover, the programmable power supply 15 outputs the desired output voltage according to the control signal from the control circuit 10 to the processor cores 17a to 17d, respectively.

  Here, in addition to the clock signal from the PLL 13, a control signal (Enable signal) from the control circuit 10 is input to the Gating circuits 16 a to 16 d. In response to the control signal from the control circuit 10, the supply signals (clocks) from the Gating circuits 16a to 16d to the processor cores 17a to 17d are turned on and off as follows.

  Here, an example of the configuration of the Gating circuits 16a to 16d is shown in FIG. As shown in FIG. 3, the Gating circuit 16 includes a mask register and an AND gate. An example of drive signals (input signal, output signal) in the Gating circuit 16 is shown in the timing chart of FIG.

  An inverted signal of the clock signal (SystemCLK) from the PLL 13 and an enable signal (Enable) from the control circuit 10 are input to the mask register. Since the enable signal is delayed and output in accordance with the inverted signal of the clock signal, the output of the mask register is the EnableOut signal shown in the timing chart of FIG. The output of the mask register is input to one terminal of the AND gate. The clock signal (SystemCLK) from the PLL 13 is input to the other terminal of the AND gate. As a result, the output of the AND gate becomes the PeCLK signal shown in the timing chart of FIG. The output of the AND gate is supplied to the clock pin of the processor core 17 as an example of the configuration of the processor cores 17a to 17d.

  In this way, the supply signals to the processor cores 17 a to 17 d can be turned on / off by the enable signal from the control circuit 10. Of the processor cores 17a to 17d, the processor core whose clock supply has been stopped does not operate and cannot be used for processing. Since this processor core does not operate, it does not consume power.

  Through the above operation, the number of processors selected by the control circuit 10 operate at the operating frequency and operating voltage selected by the control circuit 10 to perform processing.

  Next, estimation of processing capability required for image processing executed in the control unit 2 will be described. Here, the necessary processing capacity is obtained by dividing the amount of data to be processed by the processing time available for processing.

  For execution of image processing as a job, the control circuit 10 determines a processing time that can be used for processing by the control unit 2 in accordance with the amount of processing and the content of the processing. For example, a processing time that can be used in advance is determined in accordance with the processing amount and the content of the processing, and is stored in a storage unit (not shown), and the control circuit 10 reads the processing time from the storage unit. In addition, for example, when image processing of one sheet of image data is performed for use in printing, processing that can be used for processing in accordance with the time limitation of the actual image forming process. Time can be taken. In this way, the processing time may be determined by an external factor for the control unit 2.

  On the other hand, the job processing amount estimation unit 11 estimates the job processing amount and the data size. The job processing amount estimation unit 11 of the present embodiment accesses the memory 3 to estimate the size of image data to be printed, and transmits the obtained job processing amount to the control circuit 10.

  The control circuit 10 divides the job processing amount by the processing time to obtain a necessary processing capacity. The control circuit 10 accesses the operating point LUT 12 to obtain the optimal operating point and the optimal number of processors that are determined in advance according to the processing capability.

  The control circuit 10 controls the PLL 13 and the programmable power supply 15 as described above to realize an optimum operating frequency and an optimum operating voltage. Further, as described above, the control circuit 10 realizes the optimum number of processors by the enable signals to the Gating circuits 16a to 16d.

  Further, the control circuit 10 equally divides data to be processed according to the set number of operating processor cores and distributes the data to the processor cores to be operated. As a result, the processing is evenly distributed to the processor cores to be operated. An example of image data distribution will be described with reference to the schematic diagram of FIG.

  For example, when all four of the processor cores 17a to 17d are used, the control unit 2 equally divides the image data D shown in FIG. 5 into four as indicated by the cutting lines L1, L3, and L5. For example, when three of the processor cores 17a to 17d are used, the image data D is equally divided into three as indicated by the cutting lines L2 and L4.

  The control circuit 10 outputs the equally divided image data to the bus line B via a path (not shown) and transmits it to a desired processor core.

  Among the processor cores 17a to 17d, the processor core to which the enable signal from the control circuit 10 is input performs the same type of image processing on the distributed image data. In this way, equal processing in the processor core can be reliably realized.

  In this way, by referring to the operating point LUT 12 that selects and holds the operating point of the degenerate operation in advance from the processing amount estimated by the job processing amount estimating unit 11, the operating frequency, operating voltage, and operating processor core are referred to. The number can be determined immediately and appropriately. Based on the determination result, the control circuit 10 appropriately sets the operating frequency, the operating voltage, and the number of operating processor cores.

  Next, a description will be given of a method in which the control unit 2 configured as described above determines an optimal operating point set in advance and records it in the operating point LUT 12 in order to select an optimal operating point.

Here, the power consumption P of one processor is given by P = C × V ² × f, where V is the operating voltage, f is the operating frequency, and C is the capacity (the sum of the internal capacity and the load capacity).

In the control unit 2 of the present embodiment, the capacity per processor core is Cpe. Further, it is assumed that all the processor cores are uniform, and the number of processor cores used is m. That is, a model is used in which the total power consumption matches (completely proportional to) the sum of the power consumption of each processor core. Also consider the case of symmetric multiprocessing where each processor core is the same. At this time, the power consumption in the control unit 2 is given by P = Cpe × V ² × f × m. As described above, the control unit 2 is a multiprocessor system that can stop clock input to a processor core that is not being used.

  A case where three operation modes are set in the control unit 2 of the present embodiment will be described. Here, the operation mode represents a set of operation points including an operation voltage and an operation frequency.

  First, two operation modes of a normal operation mode (mode 1) and a different operation mode (mode 2: low power consumption mode) will be described.

  The operating point of each mode (mode1, mode2) and the number of processors to be operated are set as shown in Table 1 below.

ここで、各モードの動作周波数の比を表すrf、動作電圧の比を表すrvは、それぞれ 0<rf<1、 0<rv<1 を満たす。この条件の下で、それぞれのモードにおける処理性能と消費電力と見積ると、以下の表２のようになる。

Here, rf representing the operating frequency ratio of each mode and rv representing the operating voltage ratio satisfy 0 <rf <1 and 0 <rv <1, respectively. Under these conditions, the processing performance and power consumption in each mode are estimated as shown in Table 2 below.

ここで、Xpeとは、１つのプロセッサコアが通常モードで動作したときの処理能力である。また、Ｃpeとは、プロセッサコアの静電容量である。このように、消費電力は、周波数に比例し、かつ、電圧の２乗に比例する。一方、処理能力は、クロックの速さに比例するので、実質的に周波数に比例する。

Here, Xpe is processing capability when one processor core operates in the normal mode. Cpe is the capacitance of the processor core. Thus, the power consumption is proportional to the frequency and proportional to the square of the voltage. On the other hand, since the processing capacity is proportional to the speed of the clock, it is substantially proportional to the frequency.

  Regarding the three operation modes of the control unit 2 of the present embodiment, for the sake of simplicity, each operation mode has one operation point. It is assumed that mode1, mode2, and mode3 have operating points of (operating frequency, operating voltage) = (700 MHz, 1.65 V), (500 MHz, 1.5 V), and (300 MHz, 1.25 V), respectively. The values of these three operating points were the values actually used in Crumeta's LongRun Technology by Transmeta. FIG. 6 shows a normalized graph of the relationship between the processing capability and power consumption in this case so that the processing capability and power consumption in mode 1 of one processor core are both 1.

  Points m11, m12, m13, and m14 indicate processing capability and power consumption when the number of processor cores to be used is 1, 2, 3, and 4, respectively, in mode1. Points m21, m22, m23, and m24 indicate processing capability and power consumption when the number of processor cores to be used is 1, 2, 3, and 4, respectively, in mode2. Points m31, m32, m33, and m34 indicate processing capability and power consumption when the number of processor cores to be used is 1, 2, 3, and 4, respectively, in mode 3.

  From the graph of FIG. 6, it can be seen that there is a state where mode2 is more advantageous than mode1 (or mode3 is more advantageous than mode2) in both power consumption and processing performance.

  That is, for example, when comparing the point m12 and the point m23, both the power consumption and the processing capability are close to each other, but the point m23 has less power consumption and a larger processing capability than the point m12. That is, in this case, both the processing performance and the power consumption are more advantageous when the operating point has a low operating frequency and a low operating voltage. Further, for example, the same applies to the point m22 and the point m34.

  Thus, the conditions under which both the processing performance and the power consumption are advantageous at the operating point of the low operating frequency and the low operating voltage will be considered based on Table 2.

According to Table 2, the conditions in this case can be expressed as P1> P2 for power consumption and X1 ≦ X2 for processing capacity. That is,
Cpe × V ² × f × m1> Cpe × (rv × V) ² × (rf × f) × m2 (Formula 1)
Xpe × m1 ≦ Xpe × m2 × rf (Formula 2)
It is. Here, since both Expression 1 and Expression 2 use positive numbers,
m1> rv ² × rf × m2,
From Equation 2
m1 ≦ rf × m2
Can be obtained. Therefore, when the above conditions are combined into one,
rv ² × rf <m1 / m2 ≦ rf (Formula 3)
It becomes. In other words, when the condition of Equation 3 is satisfied, the use of mode 2 which is a low power consumption mode can reduce the power consumption while maintaining the processing capacity equal to or higher, so the resources of the multiprocessing system can be used effectively. can do. Therefore, when the condition of Expression 3 is satisfied, the operating point of mode2 is selected instead of the operating point of mode1. The operating point, the number of operating processor cores, and the like are stored in the operating point LUT 12. The operating point LUT 12 may store the processing capability and power consumption obtained when the operating point and the number of operating processor cores are selected.

  Based on the above consideration, in the control unit 2 of the present embodiment, the optimum operating point and the number of processors are selected in advance as follows and stored in the operating point LUT 12. In brief, the control unit 2 of the present embodiment selects the operating point and the number of processors included in the region R from the operating points and the number of processors shown in FIG. 6 and stores them in the operating point LUT 12. Here, the region R is a region that includes an operating point with lower power consumption and the number of processors even with the same processing capability.

  The selection of the region R in FIG. 6 is performed as follows. First, consider an operating point (mode 3) that is expected to consume the least power and has the lowest operating voltage and the lowest operating frequency. Since this operating point consumes less power, it is preferable to select this operating point as much as possible if the required processing capability can be achieved by changing the number of processor cores. As a result, points m31, m32, m33 and m34 shown in FIG. 6 are selected.

  The reason for this selection is that the operating frequency increases as the operating voltage increases due to the nature of the semiconductor device, and the power consumption of the multiprocessor system increases in proportion to the product of the square of the voltage and the frequency. On the other hand, the processing capability increases in proportion to the frequency. That is, the lower the operating voltage and the operating frequency, the lower the power consumption even if the processing capacity is the same. For this reason, as long as necessary processing capability can be obtained, it is advantageous to select the one having the lower operating voltage and operating frequency.

  Here, consider the case of the maximum number of processor cores at the operating point (mode 3) with the lowest power consumption, that is, the point m34. Then, a set of other operating points having a processing capability lower than this point is not used because it increases power consumption. That is, in FIG. 6, the points m21, m22, and m11 are not used, but are outside the region R. In this way, in the range where the required processing capability is smaller than the processing capability at the point m34, it is possible to reliably select the operating point with the least power consumption regardless of the number of processor cores.

  Note that the selection method for selecting the set A1 = {points m31, m32, m33, m34} while not using the set B1 = {points m21, m22, m11} is determined by the above-described formula 3. The conditions are also met. That is, the power consumption obtained by the operating point and the number of operating processor cores selected from the set A1 is P1, and the processing capacity is X1, and the power consumption obtained by the operating point and the number of operating processor cores selected from the set B1 is P2. Is set to X2, it is clear that P1> P2 in terms of power consumption and X1 ≦ X2 in terms of processing capacity are satisfied, and therefore Eq. 3 equivalent to this is satisfied.

  Then, consider the operating point (mode 2) that has the next lowest frequency and the next lowest power consumption. For this operating point, all operating points other than the operating points m21 and m22 determined not to be used as described above, that is, operating points having a processing capability higher than that of the point m34 are selected. That is, points m23 and m24 are selected. In this way, it is possible to select an operating point with the optimum power consumption among the selectable combinations for the processing capability that cannot be realized at the operating point with the lowest power consumption.

  Here, consider the case of the maximum number of processor cores at the operating point (mode 2), that is, the point m24. Then, a set of other unselected operating points having a processing capability lower than this point is not used because it only increases power consumption. That is, in FIG. 6, the point m12 is not used and is positioned outside the region R. In this way, in the range where the required processing capability is smaller than the processing capability at the point m24, it is possible to reliably select the operating point with the lowest power consumption regardless of the number of processor cores. Also in this case, the selection method for selecting the set A2 = {points m23, m24} while not using the set B2 = {points m12} is the same as the above-described reason, and the determination condition according to the above-described equation 3 is used. Is also satisfied.

  Next, for mode1, all operating points other than the operating points m11 and m12 determined not to be used as described above, that is, operating points with higher processing capability than the processing capability at point m24 are selected. That is, points m13 and m14 are selected.

  FIG. 6 shows a region R including the points m31, m32, m33, m34, m23, m24, m13, and m14 selected by the above procedure. In addition, the region R does not include the points m21, m22, m11, and m12.

  In this way, the operating point of lower power consumption (lower operating voltage, lower operating frequency), processing capacity below the processing capacity when operating with the maximum number of processor cores in the set of processors (operation mode) Corresponding combinations of operating points and processor numbers in the higher power consumption operating mode are not selected as operating points for the degenerate operation.

  On the other hand, an operating point with low power consumption and a set of processors (operation mode) are selected. Further, the combination of the operating point and the number of processors in the operation mode with high power consumption is selected when the processing power is higher than the processing capability at the maximum number of processors in the operating point with low power consumption and the number of processors. . As a result, the optimum operating point can be determined in view of both processing capability and power consumption.

  Processing in the control unit 2 as described above will be described with reference to FIG. For example, in the image forming apparatus 1, when a document image is read by the image reading unit 4, the obtained image data is subjected to image processing by the control unit 2 and printed by the image forming unit 5, the control unit 2 To work.

  In the control unit 2, the control circuit 10 reads out the image data of the document read by the image reading unit 4 from the memory 3, and the job processing amount estimation unit 11 estimates the required job processing amount and data size (S1).

  Further, the control circuit 10 determines a processing time that can be used for processing in the control unit 2 according to the speed of the image forming process in the image forming apparatus 1, and the job processing amount obtained from the job processing amount estimation unit 11 and The required processing capacity is calculated using the determined processing time (S2). In the image forming apparatus 1 of the present embodiment, the processing time is stored in advance in a storage unit (not shown), and the control circuit 10 accesses the storage unit to obtain a processing time according to the content of the processing.

  The control circuit 10 extracts the optimum operating point and the number of operating processors from the operating point LUT 12 according to the required processing capacity (S3, S4). Here, for example, if the processing capability and power consumption obtained by a predetermined operating point / number of operating processors are also stored in the operating point LUT 12, the operating point / operating processor having higher processing capability than necessary processing capability. Among the numbers, the combination of the operating point and the operating processor number with the lowest power consumption is selected. If the processing point and power consumption are not stored in the operating point LUT 12, the processing power and power consumption are newly calculated based on the operating point and the number of operating processors, and the processing power is higher than the required processing power. The operating point / number of operating processors with the lowest power consumption is selected from the operating point / number of operating processors.

  The operating point and the number of operating processors selected as described above are realized as follows. The control circuit 10 outputs a control signal to the PLL 13 and the programmable power supply 15 in order to realize the operating point extracted from the operating point LUT 12. Further, the control circuit 10 divides the image data as shown in FIG. 5, for example, according to the number of processors used. The control circuit 10 distributes the divided data from the bus line B shown in FIG. 1 to the processor cores 17a to 17d via a path (not shown).

  The divided data is input to each of the processor cores 17a to 17d. The processor cores 17a to 17d are supplied with a clock and an operating voltage which are controlled and changed by the control circuit 10 and have the optimum operating frequency. As a result, each of the processor cores 17a to 17d performs the processing with the least power consumption, that is, the optimum processing that satisfies the required processing capability.

  As described above, the image forming apparatus 1 according to the present embodiment includes the control unit 2 as a multiprocessor system. The control unit 2 selects the operating point and the number of processors that have the same processing capability and that consume less power, or that have greater processing capability and less power consumption. In the operating point LUT 12, a set of operating points (operating frequency, operating voltage) and the number of operating processors selected and calculated in advance before actual job processing is stored as a table. Further, the processing capacity and power consumption in that case may be included in the table. In actual processing, the control circuit 10 reads the table stored in the operating point LUT 12, and the operating point corresponding to the processing capability higher than the required processing capability has the lowest power consumption. And the operating point and the number of processors are extracted. As a result, the optimum (lowest power consumption) operating point / number of operating processors according to the required processing capacity obtained by the estimation can be obtained immediately.

  In addition, the operating point and the number of operating processors are realized for the processor cores 17a to 17d, and the data is equally distributed to the operating processor cores, so that an equivalent process can be realized.

  In the above-described embodiment, a configuration has been described in which processing is evenly distributed by equally distributing data to the processor cores 17a to 17d having the same processing capability. However, the present invention is not limited to this. It is not a thing. For example, even when the processing capacities of the processor cores are not the same, the processing can be similarly performed by proportionally distributing the input amount of the input image data according to the processing capacities.

  In the above-described embodiment, the control circuit 10 performs the process of dividing and distributing the processed image data to each processor core. However, the present invention is not limited to this. For example, the configuration may be such that one processor core in a multiprocessor system is a master, the other core is a slave, and the processor core that is the master executes the process of dividing the processed image data. In addition, a configuration may be provided in which a dedicated circuit block is provided.

  Moreover, although the control part 2 demonstrated in the above-mentioned embodiment is the structure by which a control signal is transmitted from another control circuit 10 with respect to each processor core 17a-17d, the control part 2 is restricted to this structure. Instead, for example, a master-slave configuration in which one of the processor cores 17a to 17d is a master and the other is a slave may be employed.

  Further, in the above-described embodiment, the configuration has been described in which the control unit 2 distributes data evenly by distributing the data evenly to the processor cores 17a to 17d. However, the configuration for performing equal distribution of processes is not limited to this, and for example, the equal distribution of processes can also be realized by an operating system implemented in a multiprocessor system.

  Further, the job processing amount estimation unit 11 and the operating point LUT 12 described in the above embodiment are not limited to the above configuration. When the multiprocessor system has a master / slave configuration, the master processor core may execute the function of the job processing amount estimation unit 11 and the recording unit (not shown) may be responsible for the function of the operating point LUT 12.

  Note that the above-described multiprocessor system may function as the control circuit 10 by causing a processor to read and execute a program (microprogram) recorded in a storage medium (not shown). With this configuration, the details of the control of the control circuit 10 can be easily changed by changing the program. Further, in the control unit 2 described above, the selection result of the control circuit 10 can be changed by changing the contents of the table stored in the operating point LUT 12.

  Further, in the above-described embodiment, the configuration in which the control unit 2 uses the control circuit 10 and the Gating circuits 16a to 16d to turn on and off the clock supply to the processor cores 17a to 17d has been described. Alternatively, power supply from the programmable power supply 15 to the processor cores 17a to 17d may be turned on / off using the control circuit 10 and a switch (switching element).

  As described above, the present invention relates to a multiprocessor system control method and a multiprocessor system for operating a plurality of processors. The present invention also provides a clock supply control means for each processor core, a variable frequency clock supply means for the multiprocessor system, and a variable operating voltage supply means for the multiprocessor system in a multiprocessor system having a plurality of processor cores. In this case, it can be expressed that the present invention relates to a control method and a multiprocessor system for determining the best operating point in view of both power consumption and processing performance.

  Here, with the rapid development of semiconductor technology, the number of gates incorporated in one LSI has increased dramatically, and CMP in which a plurality of processor cores are mounted on a single chip has been used. . For example, CMP has already been adopted in IBM's "POWER4" and SUN's "MAJC-5200", and Intel (registered trademark) is also considering its adoption.

  On the other hand, reduction of power consumption related to electronic devices is an important issue. This is because, in battery-driven electronic devices, power consumption is an important issue in relation to battery drive time. For example, some notebook personal computers employ Intel (registered trademark) SpeedStep Technology. This SpeedStep Technology is a technique for reducing the power consumption of the CPU and increasing the battery driving time by lowering the operating voltage and operating frequency of the CPU when driving the battery than when driving the AC power supply. Another similar technology is Transmeta's LongRun Technology.

  In addition, electronic devices that can be driven infinitely by commercial power sources are also recommended to save power from the socio-ecological viewpoint of limited resources and the prevention of global warming.

  Furthermore, due to a dramatic increase in the number of gates, the amount of heat generated by the LSI has become enormous. Since large heat generation causes functional deterioration and failure of electronic devices, LSIs are generally required to reduce power consumption and suppress heat generation.

  Here, the above-mentioned Patent Document 4 (Japanese Patent Laid-Open No. 2002-99433) discloses a configuration including a PLL and a power source for each processor. That is, a multiprocessor system has been proposed in which the operating voltage and operating frequency of each processor core can be set separately. As a result, the power of the multiprocessor system can be reduced with very high flexibility.

  However, this configuration requires at least the same number of PLLs and programmable power supplies as the number of processor cores. Therefore, application to consumer products is difficult in terms of cost, and application of the patent is difficult unless it is directed to an expensive system. Furthermore, for a multiprocessor system that assigns processing equally to each processor core, the invention of this patent causes a significant increase in cost, and cannot be the optimal solution. Further, a method for actually determining an optimum value is not disclosed.

  Therefore, as described above, in a multiprocessor system that assigns processing equally to each processor core, an optimum operating point is determined in view of processing capability and power consumption, and is used.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and a configuration obtained by appropriately combining technical means disclosed in the embodiments, respectively, It is included in the technical scope of the present invention.

  The specific embodiments or examples described above are merely to clarify the technical contents of the present invention, and the present invention is not limited to such specific examples and should not be interpreted in a narrow sense. Various modifications can be made within the scope of the claims, and the modified embodiments are also included in the technical scope of the present invention.

  The multiprocessor system can also be applied to an image forming apparatus that performs image processing as described above.

1 is a block diagram showing an embodiment of a multiprocessor system according to the present invention. It is a block diagram which shows an example of the image forming apparatus containing the said multiprocessor system. It is a logic circuit diagram which shows a part of said multiprocessor system. 4 is a timing chart showing input / output characteristics of the logic circuit shown in FIG. 3. It is a figure for demonstrating the data distribution in the image processing by the said multiprocessor system. It is a graph for demonstrating the operating point selected in the said multiprocessor system, and the number of processors. It is a flowchart for demonstrating selection of the operating point in the said multiprocessor system, and the number of processors. It is a block diagram which shows an example of the conventional multiprocessor system. It is a block diagram which shows another example of the conventional multiprocessor system. 10 is a graph showing a relationship between processing capability and power consumption in the multiprocessor system shown in FIG. 8 or FIG. 9. It is a block diagram which shows another example of the conventional multiprocessor system. 12 is a graph showing a relationship between processing capability and power consumption in the multiprocessor system shown in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Control part (multiprocessor system)
DESCRIPTION OF SYMBOLS 10 Control circuit 11 Job processing amount estimation part 12 Operating point LUT (memory | storage part)
13 PLL (clock supply unit)
14 Oscillator circuit (clock supply unit)
15 Programmable power supply (power supply voltage supply unit)
16a-16d Gating circuit 17a-17d Processor core (processor)

Claims (9)

In a control method of a multiprocessor system including a job processing step of processing a job by supplying a power supply voltage and a clock to a desired processor among a plurality of processors,
Of the operating points that determine the power supply voltage and the clock frequency to be supplied to the processor in the job processing step, the first operating point and the second operating point.
Operating voltage at second operating point / Operating voltage at first operating point = rv,
Operating frequency of the second operating point / Operating frequency of the first operating point = rf,
The number of processor cores to be operated at the first operating point is m1,
When the number of processor cores to be operated at the second operating point is m2,
A control method for a multiprocessor system comprising a selection step of selecting a second operating point over a first operating point when rv ² × rf <m1 / m2 ≦ rf is satisfied. In a control method of a multiprocessor system including a job processing step of processing a job by supplying a power supply voltage and a clock to a desired processor among a plurality of processors,
For an operating point that determines the power supply voltage and the clock frequency to be supplied to the processor in the job processing step, a set of operating points having the higher power supply voltage and the clock frequency is defined as a first operation mode. , A set of operating points with the lower frequency of the power supply voltage and the clock as the second operation mode,
In addition to selecting the operating point of the second mode, the processing capability obtained according to the number of processor cores to be operated, the power supply voltage, and the frequency of the clock is selected as the operating point of the first mode. A control method for a multiprocessor system, comprising: an operating point selection step that is selected when the processing capacity is higher than the processing capacity when the maximum number of processor cores that can be used in the system is used.   Before the job to be processed in the job processing step is submitted to the multiprocessor system, the selection step is executed in advance to select the operating point and the number of processor cores to be operated. The method of controlling a multiprocessor system according to claim 1.   Before the job to be processed in the job processing step is submitted to the multiprocessor system, the operation point selection step is executed in advance to select the operation point and the number of processor cores to be operated. The method of controlling a multiprocessor system according to claim 2. A processing amount calculation step for calculating the processing amount of the job to be processed,
The required processing capacity is estimated according to the processing amount calculated in the processing amount calculation step, and an operating point to be further selected from the operating points selected in the selection step is determined according to the required processing capacity. Including a determination step,
The job processing step is a distributed processing step that realizes the operation point determined in the determination step and causes the processor core to be operated to uniformly distribute the job. A control method of a multiprocessor system. A processing amount calculation step for calculating the processing amount of the job to be processed,
Estimate the required processing capacity according to the processing amount calculated in the processing amount calculation step, and select an operating point to be further selected from the operating points selected in the operating point selection step according to the required processing capability. An operating point determining step to determine,
The job processing step is a distributed processing step that realizes the operation point determined in the operation point determination step and causes the processor core to be operated to uniformly distribute the job. A control method of the multiprocessor system described. In a multiprocessor system having a plurality of processors,
A clock supply unit that supplies a clock to the processor core; a power supply voltage supply unit that supplies a power supply voltage to the processor core; and on / off of the supply of the clock from the clock supply unit to the processor core and the power supply voltage supply unit A control circuit for controlling at least one of on / off of the supply of the power supply voltage to the processor core,
The control circuit selects the operation point selected by the selection step in the control method of the multiprocessor system according to claim 1 or the operation point selection step in the control method of the multiprocessor system according to claim 2 and the number of processor cores to be operated. A multiprocessor system that controls the frequency of the clock supplied by the clock supply unit and controls the power supply voltage supplied by the power supply voltage supply unit with reference to a storage unit storing a set .   8. The multiprocessor system according to claim 7, wherein the multiprocessor system is formed on one semiconductor chip. It has a job processing amount estimation part that estimates the processing amount of the submitted job before actually processing it,
The control circuit calculates a necessary processing capability according to the processing amount of the job estimated by the job processing amount estimation unit, and refers to the storage unit according to the required processing capability and operates the operating point. 8. The multiprocessor system according to claim 7, wherein the number of processor cores to be operated is determined, and the job is equally distributed to the processor cores to be operated in accordance with the determination.

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