JP2004288087A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor which enables not only an LCD but also a control part, and the like, to reduce power consumption in a power-saving display mode, even during standby (a state of sleep). <P>SOLUTION: A PDA is constituted with a main control part 1 for controlling a normal display mode and a power-saving display control part 2 for controlling the power-saving display mode; in a normal display mode, the main control part 1 becomes active state and controls the normal display mode; and in a power-saving mode, the main control part 1 becomes the sleep state, the power-saving display control part 2 becomes the active state and controls the power-saving display mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a portable information processing apparatus having a display unit, and particularly to a configuration for reducing power consumption of a display control unit and its control.
[0002]
[Prior art]
In recent years, a portable information processing device has a large display screen, and accordingly, power consumption has also increased.
[0003]
In order to reduce the power consumption, a portable terminal that divides a display area of an LCD panel into a plurality of areas and displays the divided areas has been proposed (for example, see Patent Document 1).
[0004]
In the portable terminal disclosed in Patent Document 1, power consumption is reduced by displaying a large display area in a display mode with a large amount of display information and displaying a small display area in a display mode with a small amount of display information. It is carried out.
[0005]
Further, a liquid crystal display device in which a display area of a liquid crystal panel is divided into a plurality of regions has been proposed (for example, see Patent Document 2).
[0006]
In the liquid crystal display device of Patent Literature 2, power consumption is reduced by dividing a display area into partial display areas and displaying the display area based on the amount of information to be displayed.
[0007]
[Patent Document 1]
JP 2001-103152 A (page 3-4, FIG. 1)
[0008]
[Patent Document 2]
JP-A-6-95621 (page 2-3, FIG. 1)
[0009]
[Problems to be solved by the invention]
By the way, in the conventional devices described in Patent Documents 1 and 2 described above, no consideration is given to reducing the power consumption on the control unit side, and the control unit side is increased with the increase in the size of the LCD panel. There was a problem of increased power consumption.
[0010]
SUMMARY An advantage of some aspects of the invention is to provide an information processing apparatus capable of reducing power consumption on a control unit side.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, an information processing apparatus according to the present invention is an information processing apparatus having a normal display mode and a power saving display mode, wherein a display unit is controlled to be displayed in the normal display mode and the power saving display mode. Main control means for controlling the information processing apparatus and being in an active state in the normal display mode to control the display means, and in a sleep state in the power saving display mode; and an active state in the power saving display mode. The power-saving display control means that controls the display means and enters a sleep state in the normal display mode.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
1 to 13 show an embodiment in which the present invention is applied to a PDA (PERSONAL DIGITAL ASSISTANTS). 1 to 7 show a first embodiment of the present invention, FIG. 1 is a block diagram of a main part of a PDA, FIG. 2 is a circuit diagram of a power control circuit of the PDA, and FIG. FIG. 4 is a time chart showing the display control of the PDA, and FIGS. 5 to 7 are flowcharts showing the display control of the PDA.
[0014]
FIGS. 8 and 9 show a second embodiment of the present invention. FIG. 8 is a block diagram of a main part of the PDA, and FIG. 9 is a time chart showing display control of the PDA. FIGS. 10 and 11 show a third embodiment of the present invention. FIG. 10 is a block diagram of a main part of the PDA, and FIG. 11 is a time chart showing display control of the PDA. 12 and 13 show a fourth embodiment of the present invention. FIG. 12 is a block diagram of a main part of the PDA, and FIG. 13 is a time chart showing display control of the PDA.
[0015]
(First Embodiment)
A first embodiment of a PDA to which the present invention is applied will be described with reference to FIGS.
[0016]
FIG. 1 is a block diagram of a main part of a PDA to which the present invention is applied. The main part of the PDA includes a main control unit 1, a power saving display control unit 2, a main control unit 1, or a power saving display control unit 2. The display 4 is constituted by an LCD 4 or the like on which display data is selected and displayed by a MUX (multiplexer) 3.
[0017]
The main control unit 1 includes a first clock unit 10, a first control unit 20, a key input unit 30, and the like, and controls a main operation of the PDA and a normal display related thereto.
[0018]
The power saving display control unit 2 includes a second clock unit 40, a second control unit 50, and the like, and performs power saving display control when the PDA is on standby.
[0019]
Based on the MUX switching signal 21a from the main control unit 1, the MUX 3 displays the display data 24a in the normal display mode output from the main control unit 1 and the display data in the power saving mode output from the power saving display control unit 2. One of them is selected and supplied to the LCD 4.
[0020]
Now, the main control unit 1 and the power saving display control unit 2 can switch the operation mode between the sleep state and the active state. In the sleep state, the main function of the PDA is stopped, and only the necessary minimum functions are operated, and a power saving state is set. On the other hand, in the active state, all functions of the PDA operate.
[0021]
At that time, the main control unit 1 and the power saving display control unit 2 independently switch between the sleep state and the active state. In order to perform this switching, the power supply to the blocks indicated by the dotted lines in FIG. 1 is controlled by different control lines.
[0022]
In the sleep state of the main control unit 1, the power of the first control unit 20 is off, the power of the first clock unit 10 is off, and the power of the key input unit 30 is on. This is because the key input unit 30 detects a key operation by the user during the sleep state and generates an interrupt signal for switching to the active state. In the active state, all of the above devices are on. In the sleep state, the power of the first control unit 20 that controls the main function and consumes a large amount of power is in an off state, and thus exhibits an energy saving effect. In the sleep state of the power-saving display control unit 2, the power of the second control unit 50 is off and the power of the second clock unit 40 is on or off depending on the situation. In the active state, all of the above devices are on.
[0023]
Regarding the above power control, a power control circuit of the first clock unit 10 will be described with reference to FIG. The flip-flop circuit 14 is set by the key input signal 30a input to the "ON" input terminal of the first clock unit 10, and the Q-bar output goes low. When the Q-bar output goes low, the transistor 15 is turned on, and the power supply voltage Vdd is supplied to the RTC circuit (REAL TIME CLOCK) 11 and the Vdd terminal of the RAM 13 that constitute the first clock unit 10, One clock unit 10 is turned on.
[0024]
Next, when the main control sleep signal 21d from the central processing unit 21 is input to the "OFF" input terminal of the first clock unit 10, the flip-flop circuit 14 is reset, and the Q-bar output goes high. . When the Q bar output goes high, the transistor 15 is turned off, the supply of the power supply voltage Vdd to the RTC circuit 11 and the RAM 13 of the first clock unit 10 is stopped, and the first clock unit 10 is turned off.
[0025]
When the RTC circuit 11 and the RAM 13 constituting the first clock unit 10 include a power supply control circuit equivalent to that shown in FIG. 2, the RTC circuit 11 and the RAM 13 can be provided without providing the power supply control circuit shown in FIG. A similar operation is performed by directly inputting the signals 30a and 21d to the on / off input terminals of the.
[0026]
Next, a detailed configuration of each block will be described. The first clock unit 10 includes an RTC circuit 11, a crystal oscillator 12, a RAM 13, and the like. The first clock unit 10 can count time and hold time information in the first clock unit 10.
[0027]
The RTC circuit 11 is one that is physically incorporated in a general-purpose CPU chip constituting the central processing unit 21. However, the power control is controlled by the system as described above.
[0028]
The first control unit 20 includes a central processing unit 21, a ROM 22, a RAM 23, a first display controller 24, and the like. The central processing unit 21 incorporates a CPU and an I / O control unit, and controls the entire PDA according to a program in the ROM 22 using the RAM 23 as a work area. Further, the central processing unit 21 outputs a MUX switching signal 21a to the MUX 3 in order to switch the display mode of the LCD 4. The first display controller 24 performs display control when the main function of the PDA is operating, and outputs the display data 24 a converted to the image form of the LCD 4 to the MUX 3.
[0029]
The first control unit 20 is a part that controls the main functions of the entire PDA. Since the power consumption is large, power control is performed by a power control circuit equivalent to that in FIG. In this case, the operation of the first control unit 20 itself is stopped by the main control sleep signal 21d of the central processing unit 21.
[0030]
The key input unit 30 is configured by touch keys or the like, and a key operation is performed by a user. The key input unit 30 is always in operation when the main power of the PDA is turned on.
[0031]
On the other hand, the second clock unit 40 of the power saving display control unit 2 is configured by an RTC circuit 41, a crystal oscillator 42, a RAM 43, etc., performs time counting, and in the second clock unit 40, Time information can be held. Further, power control similar to that of the first clock unit 10 is performed. In the second clock unit 40, the power-saving display active signal 21c from the central processing unit 21 becomes a power-on signal, and the power-saving display sleep signal 21b from the central processing unit 21 becomes a power-off signal.
[0032]
The second control unit 50 includes a second display controller 51 and the like, and performs power control similar to that of the first control unit 20. The second display controller 51 performs display control in the power saving display mode of the PDA, and outputs display data 51a converted to an image form of the LCD 4 to the MUX 3. The power of the second control unit 50 is turned on by the power saving display active signal 21 c from the central processing unit 21 and the one-minute elapsed signal 41 b from the RTC circuit 41. The power is turned off by the power saving display sleep signal 21b from the central processing unit 21.
[0033]
The LCD 4 has a normal display mode and a power saving display mode. In the normal display mode, as shown in FIG. 3A, display is performed on the entire display screen, and the display colors are displayed in all display colors. In the power saving display mode, as shown in FIG. 3B, a so-called partial display is performed by using a part of the display screen, and the display colors are displayed in a small number of display colors.
[0034]
As is well known, the LCD 4 dynamically scans pixel portions arranged in a matrix in the XY directions, sequentially displays pixels at intersections in the XY directions, and dynamically switches the display of pixels. ing. The drive portion of each pixel has a parasitic capacitance, and an image remains for a short time after scanning is completed, but disappears immediately. Therefore, even if it is a still image, the image is continued by repeatedly scanning the same image several tens of times per second, and the image is recognized by the user as an image.
[0035]
The same image may be sent from outside the LCD 4, but in order to reduce the load on the outside, the LCD 4 has a RAM inside and stores the image. Then, when new image data is not sent from the outside, the LCD 4 itself reads out the image data stored in the internal RAM and repeats scanning, that is, self-refresh is performed. The self-refresh is performed while reversing the polarity of the voltage applied to the pixel, which is also to prevent burn-in of the LCD screen.
[0036]
By the way, since this RAM is provided inside the LCD 4, it is generally not limited to a large capacity in consideration of cost and the like, but is limited to a screen for a partial display for a power saving display mode. The colors are limited and the RAM capacity is kept small.
[0037]
Therefore, in the power saving display mode, when the same image is displayed, the LCD 4 performs self-refresh using this RAM. On the other hand, in the normal display mode, when the same image is used, since the RAM capacity is too small to hold the same image, the same image is sent from outside the LCD 4 to the LCD 4 to refresh the LCD 4.
[0038]
The display control of the LCD configured as described above will be described with reference to FIG. 1, FIG. 4, and FIG.
[0039]
When the PDA is operating in the normal display mode, the PDA is in the display mode while there is a key input by the user from the key input unit 30 or while the first control unit 20 is performing internal processing in response thereto. (Timing T0 in FIG. 4, Step S8 in FIG. 5).
[0040]
Therefore, in the normal display mode, the main control unit 1 is in the active state, the first clock unit 10 and the second control unit 20 are turned on, and control the LCD 4. On the other hand, the power saving display control unit 2 is in a sleep state, and the second clock unit 40 and the second control unit 50 are in an off state.
[0041]
Then, the MUX 3 switches so as to select the display data 24 a from the first display controller 24 in response to the MUX switching 21 a signal from the central processing unit 21. When the central processing unit 21 also instructs the first display controller 24 to perform the normal display mode, the first display controller 24 sets the LCD 4 to the normal display mode.
[0042]
Further, the central processing unit 21 transmits the image data to the first display controller 24. The first display controller 24 converts the image data into the format of the LCD 4 and transmits it as a display data 24a signal to the LCD 4 via the MUX 3. The LCD 4 displays this display data.
[0043]
In the normal display mode, when the image data from the central processing unit 21 changes, new display data is transmitted from the first display controller 24 to the LCD 4. On the other hand, when the image data from the central processing unit 21 does not change, the same display data held in the first display controller 24 is read out and transmitted to the LCD 4 at a frequency of several tens of times per second.
[0044]
Next, control when switching from the normal display mode to the power saving display mode will be described. The central processing unit 21 watches a state where there is no key input from the key input unit 30 or internal processing, and when a state where there is no operation has passed for a predetermined time (for example, 20 seconds) (step S9), a normal display is performed. The mode is switched to the power saving display mode (step S20).
[0045]
Assuming that the switching timing is T1, a series of processes at that time will be described below. In response to the designation from the central processing unit 21, the first display controller 24 switches the display mode of the LCD 4 from the normal display mode to the power saving display mode (step S21). The MUX 3 selectively outputs the display data 51a from the second display controller 51 in response to the MUX switching 21a signal from the central processing unit 21 (step S22). The power saving display active signal 21c from the central processing unit 21 is output to the second clock unit 40 and the second control unit 50 (step S23), and the second clock unit 40 and the second control unit 50 are output. Is turned on, and the power saving display control unit 2 is activated (step S50).
[0046]
Next, the central processing unit 21 checks the current time as follows. The RAM 13 in the first clock unit 10 stores the time at a certain point in the past and the counter value of the RTC circuit 11 at that time. The central processing unit 21 reads the current counter value of the RTC circuit 11 from the counter 11a. Then, the current time is calculated from the difference between the past counter value from the RAM 13 and the current counter value from the RTC circuit 11. Then, the central processing unit 21 writes the calculated current time and the counter value of the RTC circuit 11 at that time into the RAM 13 (step S24).
[0047]
Assuming that the current time obtained by the above calculation is, for example, “12:45:30”, the central processing unit 21 displays “12:45” as the time display data of the second display unit 50 in the active state. The data is transmitted to the second display controller 51 (step S25).
[0048]
Then, the central processing unit 21 outputs the main control sleep signal 21d, whereby the first clock unit 10 and the first control unit 20 are turned off, and as a result, the main control unit 1 is put into the sleep state. (Step S26). As a result, the central processing unit 21 itself is turned off (step S27).
[0049]
In step S23, the second display controller 51 of the second control unit 50 that has been turned on (step S50) enters the state of step S50, and the current time “12:45” transmitted from the central processing unit 21. Is transmitted to the LCD 4 via the MUX 3 as a display data 51a signal (step S51), and “12:45” is displayed on the LCD 4 as shown in FIG.
[0050]
Further, the current time “12:45:30” transmitted from the central processing unit 21 is recorded in the RAM 43 via the second display controller 51 and is also preset in the RTC circuit 41 (step S52). . As a result, the time information of the first clock unit 10 is loaded into the second clock unit 40.
[0051]
When the above processing is completed, the second display controller 51 outputs a second control off signal 51b signal (step S53), turns off the second control unit 50 (step S54), and sets the second control unit 50 at the timing T1. The process ends. Thereby, the power saving display control unit 2 enters the sleep state (timing T12).
[0052]
In the sleep state at the timing T12, only the second control unit 50 is turned off, and the power of the second clock unit 40 is not turned off. Therefore, it is necessary to continue the time counting by the second clock unit 40.
[0053]
Next, control during the power saving display will be described. The LCD 4 performs self-refresh during a period T12 when no display data is sent.
[0054]
FIG. 6 shows the operation of the second clock unit 40 during the power saving display. The second clock unit 40 controls the one-minute elapsed signal 41b at the timing T2 of 12:46:00 which is 30 seconds after the above-described timing T1 (12:45:30) (step S41). Output to the unit 50 (step S42). This is performed by setting the RTC circuit 41 to output the one-minute elapsed signal 41b at “00 seconds”. The switching of the time display is for switching the display from “12:45” to “12:46” when, for example, the time has changed from 12:45:59 to 12:46:00.
[0055]
At the timing T2, the second control unit 50 is turned on again by the one minute elapsed signal 41b, the power saving display control unit 2 is activated, and the operation of the second display controller 51 starts (step S55). ). The second display controller 51 checks the current time, and the time information at this time uses the time information of the second clock unit 40. That is, the second display controller 51 reads the current counter value of the RTC circuit 41 from the counter 51a. Then, the second display controller 51 calculates the current time from the difference between the past counter value from the RAM 43 and the current counter value from the RTC circuit 41. Then, the second display controller 51 writes the calculated current time and the counter value of the RTC circuit 41 into the RAM 43 (Step S56).
[0056]
When the current time "12:46:00" is obtained, the second display controller 51 transmits "12:46" to the LCD 4 as a display data 51a signal (step S57), and the LCD 4 displays "12:46". : 46 "is displayed.
[0057]
When the above processing is completed, the second display controller 51 outputs the second control off signal 51b (step S58), the second control unit 50 is turned off (step S59), and the processing at timing T2. To end. Also at this time, the power of the second clock unit 40 is not turned off, and the time counting by the second clock unit 40 is continued.
[0058]
Next, the LCD 4 performs a self-refresh during the period T23 when no display data is sent. After the timing T3, the same process as the timing T2 is repeated every minute, and the time display in the power saving display mode is continued.
[0059]
Next, control when switching from the power saving display mode to the normal display mode will be described with reference to FIG. When the user performs a key operation during the power saving display mode, a key input presence signal 30a is output from the key input unit 30, whereby the first clock unit 10 and the first control unit 20 are turned on. . As a result, the main control unit 1 becomes active (steps S31 and S32), and the processing of the central processing unit 21 starts (step S1).
[0060]
Assuming that the timing at which a key operation is performed by the user is Tn, a series of processing at that time will be described below. The central processing unit 21 reads a signal from the key input unit 30 via the bus 20a and determines that the input is a key input by the user (step S2). Next, the central processing unit 21 transmits the MUX switching signal 21a to the MUX 3, and switches to select the display data 24a from the first display controller 24 (step S3). Next, the central processing unit 21 specifies the normal display mode to the first display controller 24, and switches the display mode of the LCD 4 from the power saving display mode to the normal display mode (Step S4). Next, the central processing unit 21 outputs a power saving display active signal 21c to the power saving display control unit 2. Thereby, the second control unit 50 of the power saving display control unit 2 is turned on (step S5). Note that the second clock unit 40 is kept on.
[0061]
When turned on (step S55), the second display controller 51 of the second control unit 50 reads a past time, a past counter value, and a current counter value from the second clock unit 40, and The current time is calculated (updated) by the same method as that described above. Then, the current time and the current counter value calculated similarly are written in the RAM 43 (step S56).
[0062]
Next, the central processing unit 21 transmits the current time obtained from the second clock unit 40 to the first clock unit 10 via the second display controller 51 (Step S6). When the processing is completed, the central processing unit 21 outputs the power saving display sleep signal 21b to the power saving display control unit 2, turns off the second clock unit 40 and the second control unit 50, and enters the sleep state. (Step S7). Thus, the processing of the second display controller 51 ends (step S57).
[0063]
Thereafter, the timing T0 of the normal display mode (step S8) continues, and the key input is similarly checked (step S9).
[0064]
Note that the above description is a process in a state where the user turns on the main power of the PDA. After the user turns off the power of the PDA, the first clock unit 10 is always backed up by a backup battery or the like, and the time is continuously counted. When the PDA is turned on, it operates in the normal display mode.
[0065]
A specific numerical example of the power consumption in the power saving display mode in the first embodiment is roughly calculated below. Generally, the PDA device has a long waiting time during which the user does nothing. Therefore, the power consumption in the power saving display mode during the standby greatly affects the battery consumption.
[0066]
In FIG. 4, it is assumed that the main control unit 1 performs the rewriting process of the display data such as the timings T2 and T3 in the power saving display mode, and the timings T12, T23, T34. It is assumed that the power consumption during the self-refreshing is about 10 mW. At the timings T1, T2, T3, etc., the main control unit 1 is set to the active state and performs clock display. Then, the power consumption of the main control unit 1 is about 300 mW. The active periods such as the timings T1, T2, T3,... Are about 1 second.
[0067]
Therefore, the average power consumption ACP in the power saving display mode is
ACP = 10 mW + (300 mW × 1 second / 60 seconds) = 10 mW + 5 mW = 15 mW
It becomes.
[0068]
Although the operation of the first control unit 20 is performed once a minute, the average power consumption is about 5 mW, which is larger than the power consumption during refreshing of 10 mW.
[0069]
Next, the same calculation is performed for the first embodiment of the present invention.
[0070]
The power consumption during the self-refresh at timings T12, T23, T34, etc. is about 10 mW in the same manner as described above. At the timings T1, T2, T3, etc., the power saving display control unit 2 is in the active state and performs clock display. The main function of the power saving display control unit 2 is only display during standby, and the power consumption is about 30 mW. Further, the active periods such as the timings T1, T2, T3,...
[0071]
Therefore, the average power consumption ACP in the power saving display mode is
ACP = 10 mW + (30 mW × 1 second / 60 seconds) = 10 mW + 0.5 mW = 10.5 mW.
[0072]
10.5mW / 15mW = 0.7
That is, the power consumption can be reduced by about 30% as compared with the average power consumption when the control is performed only by the main control unit 1. This means that the use time of the battery during standby can be extended by about 30%.
[0073]
According to the PDA of the first embodiment, display control during standby (sleep state) is performed by the power-saving display control unit 2 without using the main control unit 1 that consumes a large amount of power. A power saving effect can be obtained.
[0074]
In a PDA using a cheap general-purpose CPU chip, the counter signal 11a cannot be directly connected from the RTC circuit 11 of the first clock unit 10 to the first display controller 51. It is necessary to transmit to the first display controller 51. In order to execute this, it is necessary to turn on the central processing unit 21 of the control unit 20 which consumes a large amount of power, which increases the power consumption.
[0075]
On the other hand, in the PDA of the first embodiment, the second clock unit 40 is newly provided, so that only the first clock unit 10 and the second clock unit 40 are in the normal display mode and are omitted. In the power display mode, it is only necessary to repeat the on / off state mutually, and power consumption can be suppressed. Even when the second clock unit 40 is newly provided, the time information is transmitted without any problem by transmitting each other's time information at the time of switching between the normal display mode and the power saving display mode.
[0076]
(Second embodiment)
Second Embodiment A PDA according to a second embodiment of the present invention will be described with reference to FIGS.
[0077]
In the first embodiment, it has been described that the time information of the main control unit 1 and the power saving control unit 2 are loaded on each other so that the time information is inherited without any problem. However, the accurate time is counted. For this purpose, both the oscillation frequencies of the RTC circuit 11 and the RTC circuit 41 need to be highly accurate.
[0078]
Therefore, the second embodiment is applied to the case where the oscillation frequency of the RTC circuit 11 is high precision and the oscillation frequency of the RTC circuit 411 is low precision.
[0079]
Hereinafter, the same portions as those in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted, and different portions will be described.
[0080]
The high-accuracy clock unit 101 is always in an on state without power control. The oscillation accuracy of the RTC circuit 11 and the crystal oscillator 12 is high as in the first embodiment.
[0081]
A one-hour elapsed signal 411c from the low-accuracy clock unit 401 is newly added to the “ON” condition of the power supply control circuit of the second control unit 201. New processing accompanying the processing is executed by the central processing unit 211 and the ROM 221.
[0082]
The oscillation accuracy of the RTC circuit 411 and the crystal oscillator 421 of the clock unit 401 with low precision is lower than that of the clock unit 101. The RTC circuit 411 is configured to output a one-hour elapsed signal 411c.
[0083]
In addition, a low-precision one-hour signal 411c from the second clock unit 401 is newly added to the “on” condition of the power supply control circuit of the second control unit 501. A new process accompanying this is executed by the second display controller 511.
[0084]
The operation of the PDA configured as described above will be described with reference to FIG. In the normal display mode (timing T0) at the time of the normal operation, the main control unit 1a is in the active state, and controls the functions of the entire PDA and the display control on the LCD 4, as in the first embodiment.
[0085]
At the time of switching from the normal display mode to the power saving display mode (timing T1), the time information of the first clock unit 101 is loaded into the second clock unit 401, as in the first embodiment. Next, the main control unit 1a shifts to a sleep state. In this sleep state, only the first control unit 201 that performs the main function is turned off, and the high-accuracy clock unit 101 remains on. Continue counting time.
[0086]
Displaying the time every minute (timing T2, T3,...) In the power saving display mode is performed by the power saving display control unit 2a as in the first embodiment. In addition, in the gap, the LCD 4 performs a self-refresh (timing T12, T23, T34,...).
[0087]
By the way, the low-precision clock unit 401 outputs a one-hour elapsed signal 411c at a certain time after switching to the power saving display mode, for example, one hour (timing Tm), and outputs the first control unit 201 and the first control unit 201. The second control unit 501 is turned on, and the main control unit 1a is once set to the active state.
[0088]
A series of processes at the timing Tm will be described below. The central processing unit 211 of the first control unit 201 that has been turned on reads the counter value, the past time, and the like from the high-accuracy first clock unit 101, and calculates the current time as described above. Then, the calculated time information is transmitted to the second display controller 511 of the second control unit 501 which has been turned on. The second display controller 511 sets the time information in the low-accuracy clock unit 401 and sets the time to a correct time.
[0089]
When the processing is completed, the central processing unit 211 outputs the main control sleep signal 211d, turns off the first control unit 201, and puts the main control unit 1 into the sleep state. As a result, the central processing unit 211 itself is turned off.
[0090]
In addition, the second display controller 511 outputs the second control off signal 511b and the second control off signal 511b to turn off the second control unit 501 and put the power saving display control unit 2a into the sleep state. Thus, the second display controller 511 itself is turned off. With the above processing, the processing at the timing Tm ends.
[0091]
Thereafter, the processing at the timing Tm is repeated every hour, and the main control unit 1a consuming a large amount of power becomes active. However, the processing is performed for about 1 second, and the increase in the power consumption is almost negligible. .
[0092]
Next, at a timing Tn, when a user inputs a key from the key input unit 30, the main control unit 1a enters an active state, while the power saving display control unit 2a remains in a sleep state. At this time, the time of the low-accuracy second clock unit 401 is not loaded into the high-accuracy first clock unit 101.
[0093]
According to the PDA of the above-described second embodiment, display control during standby (sleep state) is not performed by using the main control unit 1 that consumes a large amount of power, as in the first embodiment described above. By performing the operation by the power display control unit 2, a great power saving effect can be obtained. Further, even if the second clock unit 401 has low accuracy, a time error can be reduced, and the inexpensive second clock unit 401 can be used.
[0094]
(Third embodiment)
Third Embodiment A PDA according to a third embodiment of the present invention will be described with reference to FIGS.
[0095]
The third embodiment is applied to a case where the oscillation frequency of the RTC circuit 112 is low precision and the oscillation frequency of the RTC circuit 412 is high precision.
[0096]
Hereinafter, the same portions as those in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted, and different portions will be described.
[0097]
The low-precision oscillation accuracy of the RTC circuit 112 and the crystal unit 122 of the first clock unit 102 is lower than that of the high-accuracy second clock unit 402.
[0098]
The first control unit 202 is configured to newly execute time processing in the normal display mode by the central processing unit 212 and the ROM 222.
[0099]
The high-accuracy second clock unit 402 is always on without any power control. The oscillation accuracy of the RTC circuit 412 and the crystal oscillator 422 is higher than that of the low-accuracy first clock unit 102. Further, the RTC circuit 412 outputs a one-hour elapsed signal 412c to the second control unit 502.
[0100]
A high-precision one-hour signal 412c from the second clock unit 402 is newly added to the “on” condition of the power supply control circuit of the second control unit 502. The display controller 512 is configured to execute a new process accompanying it.
[0101]
The operation of the PDA configured as described above will be described with reference to FIG. In the third embodiment, during the power saving display mode, the power saving display control unit 2b repeats the active state to display the time.
[0102]
At the time of switching from the power saving display mode to the normal display mode (timing Tn), similarly to the first embodiment, the high-accuracy time information of the second clock unit 402 is replaced with the low-accuracy first clock unit. Send to 102. However, thereafter, the high-accuracy second clock unit 402 is not turned off, and the time counting is continued while the high-accuracy second clock unit 402 remains on.
[0103]
Now, during the normal display mode, the central processing unit 212 performs time management based on the low-accuracy first clock unit 102. However, since the first clock unit 102 has low accuracy, the time may gradually shift.
[0104]
Therefore, the second clock unit 402 outputs a one-hour elapsed signal 412c at a point in time when a certain time, for example, one hour has elapsed (timing Tp) after switching to the normal display mode, and outputs the second control unit 402. 502 is turned on, and the power saving display control unit 2b is once activated.
[0105]
The one-hour count may be performed by the central processing unit 212 in the active state, and the second control unit 502 may be turned on by outputting the power-saving display active signal 212c as a one-hour elapsed signal.
[0106]
A series of processing at this timing Tp will be described below. The second display controller 512 of the second control unit 502 that has been turned on reads the count value, past time, and the like from the high-accuracy second clock unit 402, and calculates the current time as described above. . Then, the calculated current time is notified to the central processing unit 212 by interruption or the like.
[0107]
When the central processing unit 212 receives the current time from the high-accuracy second clock unit 402 via the second display controller 512, the central processing unit 212 sets the current time in the low-accuracy first clock unit 102 and sets the correct time. Set to.
[0108]
Next, the second display controller 512 outputs the second control off signal 512b to turn off the second control unit 502 and put the power saving display control unit 2b into the sleep state. As a result, the second display controller 512 itself is turned off. With the above processing, the processing at the timing Tp ends. Thereafter, the processing at the timing Tp is repeated every hour.
[0109]
Even during the normal display mode, the user sometimes wants to know the time, and may perform a key operation of the key input unit 30 to display the time. In that case, the central processing unit 212 can display the time using the low-precision time information of the first clock unit 102 set to the correct time every hour.
[0110]
Next, in the normal display mode, if the state without key input continues for a certain period of time, for example, 20 seconds, the central processing unit 212 puts the main control unit 1b into the sleep state at the timing Tq and performs the power saving display control. The unit 2b is set to the active state and the mode is switched to the power saving display mode.
[0111]
According to the PDA of the third embodiment described above, even if the first clock unit 102 has a low accuracy, the error of the clock display can be reduced, and the inexpensive first clock unit 102 is used. be able to.
[0112]
(Fourth embodiment)
A fourth embodiment of the PDA to which the present invention is applied will be described with reference to FIGS. In the fourth embodiment, the clock unit that counts the time is only the clock unit 403 of the power saving display control unit 2c. The clock section of the main control section 1c is deleted in consideration of the case where there is no use other than the time count.
[0113]
Hereinafter, the same portions as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
[0114]
The main control unit 1c does not include a clock unit. Even when a general-purpose CPU chip has a built-in RTC circuit, its function is not used.
[0115]
The first control unit 203 is configured so that the central processing unit 213 and the ROM 223 newly execute time processing during the normal display mode.
[0116]
The clock unit 403 does not include power control and is always on. The oscillation accuracy of the RTC circuit 41 and the crystal unit 42 is high as in the first embodiment.
[0117]
The second display controller 513 of the second control unit 503 is newly configured to have time processing in the normal display mode.
[0118]
The operation of the PDA configured as described above will be described with reference to FIG. Also in the fourth embodiment, during the power saving display mode, the power saving display control unit 2c repeats the active state to display the time.
[0119]
Further, at the time of switching from the power saving display mode to the normal display mode, time information is not transmitted. Simply, the main control unit 1c is activated. Then, the clock unit 403 continues to count the time in the on state.
[0120]
Now, in the normal display mode, the time when time information is required, such as displaying time according to a user's instruction or attaching time to an email, is defined as Tr. Then, at that time, the central processing unit 212 outputs the power saving display active signal 213c to the second control unit 503, and turns on the control unit 503.
[0121]
Next, a series of processes at the timing Tr will be described below. In the normal display mode, the second display controller 513 of the second control unit 503 that has been turned on reads the counter value, the past time, and the like from the high-precision clock unit 403, and sets the current time as described above. calculate.
[0122]
Then, the central processing unit 212 receives the current time from the clock unit 403 via the second display controller 513, and uses the current time for displaying the time on the LCD 4, and the like. After that, the central processing unit 212 outputs the power saving display sleep signal 213b to the second control unit 503, and turns off the second display controller 513. Thus, the process at the timing Tr ends.
[0123]
Next, assuming that a timing in which no key input has been performed for a predetermined time, for example, 20 seconds, in the normal display mode is Tq, the central processing unit 213 puts the main control unit 1c into a sleep state and sets the power saving display control unit 2c. To the active state, and switch to the power saving display mode.
[0124]
According to the PDA of the above-described fourth embodiment, display control during standby (sleep state) is performed without using the main control unit 1 that consumes a large amount of power, as in the above-described first embodiment. By performing the operation by the power display control unit 2, a great power saving effect can be obtained. Furthermore, even if there is one clock unit, it can be shared in the power saving mode and the normal display mode, and power can be saved with an inexpensive configuration.
[0125]
In each of the embodiments described above, the present invention is applied to a PDA, but it goes without saying that the present invention can be effectively applied to a mobile phone and the like.
[0126]
【The invention's effect】
According to the present invention, the power saving display in the standby state (sleep state) is performed by the dedicated power saving display control unit, and the main control unit with large power consumption is set to the sleep state. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a block diagram of a PDA showing a first embodiment according to the present invention.
FIG. 2 is a circuit diagram of a power supply control circuit of the PDA shown in FIG.
FIG. 3 is a display screen diagram of a general LCD.
FIG. 4 is a time chart showing display control of the PDA shown in FIG. 1;
FIG. 5 is a flowchart showing display control of the PDA shown in FIG. 1;
FIG. 6 is a flowchart showing display control of the PDA shown in FIG. 1;
FIG. 7 is a flowchart showing display control of the PDA shown in FIG. 1;
FIG. 8 is a block diagram of a PDA showing a second embodiment according to the present invention.
FIG. 9 is a time chart showing display control of the PDA shown in FIG. 8;
FIG. 10 is a block diagram of a PDA showing a third embodiment according to the present invention.
FIG. 11 is a time chart showing display control of the PDA shown in FIG. 10;
FIG. 12 is a block diagram of a PDA showing a fourth embodiment according to the present invention.
13 is a time chart showing display control of the PDA shown in FIG.
[Explanation of symbols]
1, 1a, 1b, 1c Main control unit
2, 2a, 2b, 2c Power saving display control unit
3 Multiplexer
4 LCD
10, 101, 102 First clock unit
11, 112, RTC circuit
12,122 Quartz resonator
13 RAM
14 flip-flops
15 transistors
20, 201, 202, 203 First control unit
21, 211, 212, 213 Central processing unit
22, 221, 222, 223 ROM
23 RAM
24 First Display Controller
30 Key input section
40, 401, 402, 403 Second clock section
41, 411, 412 RTC circuit
42, 421, 422 crystal oscillator
43 RAM
50, 501, 502, 503 Second control unit
51, 511, 512, 513 Second display controller

Claims (13)

In an information processing apparatus having a normal display mode and a power saving display mode,
A display unit that is display-controlled in the normal display mode and the power saving display mode, and controls the information processing device and is in an active state during the normal display mode to control the display unit; in the power saving display mode, Main control means for entering a sleep state;
An information processing apparatus comprising: the power-saving display control unit that is in an active state to control the display unit in the power-saving display mode and is in a sleep state in the normal display mode. The main control unit includes a first clock unit that controls time and a first control unit that controls the information processing device.
The information according to claim 1, wherein at least the first control unit is in an off state in the sleep state, and the first clock unit and the first control unit are in an on state in the active state. Processing equipment. The power saving display control unit includes a second clock unit that controls time and a second control unit that performs display control of the display unit.
2. The information processing apparatus according to claim 1, wherein at least the second control unit is in an off state in the sleep state, and the second clock unit and the second control unit are in an on state in the active state. apparatus. In an information processing apparatus having a normal display mode and a power saving display mode,
A display unit that is controlled to be displayed in the normal display mode and the power saving display mode; a first clock unit that controls time; and a first control unit that controls the information processing apparatus; A main control unit in which the first clock unit and the first control unit are turned on to control the display unit in a mode, and at least the first control unit is turned off in the power saving display mode;
A second clock unit for controlling time; and a second control unit for controlling display of the display unit, wherein the second clock unit and the second control unit are turned on in the power saving display mode. An information processing apparatus, comprising: the power-saving display control means for controlling the display means and turning off at least the second control unit in the normal display mode. In the normal display mode, the first clock unit performs time control,
When shifting from the normal display mode to the power saving display mode, time information from the first clock unit is set in the second clock unit,
In the power saving display mode, the second clock unit performs time control,
5. The information processing apparatus according to claim 4, wherein time information from the second clock unit is set in the first clock unit when shifting from the power saving display mode to the normal display mode. 6. The time accuracy of the first clock unit is higher than the time accuracy of the second clock unit,
The first clock section always counts time,
When shifting from the normal display mode to the power saving display mode, time information from the first clock unit is set in the second clock unit,
5. The information processing apparatus according to claim 4, wherein in the power saving display mode, time information generated by performing the time counting by the second clock unit is displayed on the display unit by the second control unit. 7. The information processing apparatus according to claim 6, wherein time information from the second clock unit is not set in the first clock unit when the display mode shifts from the power saving display mode to the normal display mode. 7. The information processing apparatus according to claim 6, wherein in the power saving display mode, time information from the first clock unit is set in the second clock unit at regular intervals. The time accuracy of the second clock unit is higher than the time accuracy of the first clock unit,
The second clock section always counts time,
In the power saving display mode, the second clock unit displays time information generated by performing time counting on the display unit by the second control unit,
When shifting from the power saving display mode to the normal display mode, time information from the second clock unit is set in the first clock unit,
5. The information processing apparatus according to claim 4, wherein the first clock section performs time counting in the normal display mode. 10. The information processing apparatus according to claim 9, wherein the time information from the first clock unit is not set in the second clock unit when the normal display mode shifts to the power saving display mode. 10. The information processing apparatus according to claim 9, wherein time information from the second clock unit is set in the first clock unit at regular intervals in the normal display mode. In an information processing apparatus having a normal display mode and a power saving display mode,
Display means for controlling display in the normal display mode and the power-saving display mode; and a first control unit for controlling the information processing device, wherein the first control unit is in an on state in the normal display mode Controlling the display means, the main control means that the first control unit is turned off in the power saving display mode,
A clock unit for controlling time; and a second control unit for controlling display of the display unit. In the power saving display mode, the clock unit and the second control unit are turned on to display the display. An information processing apparatus comprising: a power-saving display control unit that controls a power supply unit and turns off at least the second control unit in the normal display mode. 13. The information processing apparatus according to claim 12, wherein time information from the clock unit is set in the first control unit in the normal display mode.

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