JP2003091501A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device for efficiently perform data transmission when a plurality of bus acquiring requests are simultaneously generated from a plurality of bus masters. SOLUTION: The information processing device is equipped with a plurality of bus masters such as CPU 3, DMA controllers 2a to 2c, etc., a plurality of buses 100 to 102 that can perform data transmission independently and a plurality of memories 5, 7 and 9 equipped in connection with these buses 100 to 102, respectively. When a plurality of bus acquiring requests 103a to 103d are simultaneously generated from the plurality of bus masters, a bus controller 1 conducts arbitration for each of the buses 100 to 102 independently of one another to perform parallel transmission of the plurality of buses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of bus masters and a plurality of buses. In particular, the present invention relates to an information processing device that improves bus transfer efficiency by operating a plurality of masters in parallel.

[0002]

2. Description of the Related Art In the latest mobile communication, not only voice processing but also image processing and data processing are required to be executed simultaneously. Further, in order to smoothly display the screen, it is required to transfer a considerable amount of data within a certain time. Further, it is necessary to transfer the data taken in from a serial bus such as USB to the data processing memory sooner than the next data is updated. As described above, a bus used in an information processing device for mobile communication is required to transfer a large amount of data in a short time.

FIG. 3 shows the configuration of a conventional information processing apparatus. In FIG. 3, 31 is a bus controller, 32a, 32
b and 32c are DMA controllers, 33 is a CPU, 34
Is serial input / output (I / O) such as USB, UART, 3
6 is an image processing circuit, 38 is a voice processing circuit, and 40 is an external memory.

The I / O 34, the image processing circuit 36 and the audio processing circuit 38 are respectively provided in the DMA controller 32.
DMA activation request 205 for a, 32b, and 32c
a, 205b, 205c are output. Upon receiving the DMA activation request signal, the DMA controllers 32a, 32b, 32c request the bus acquisition request 203 to the bus control device 31.
a, 203b, 203c are output. The CPU 33 also outputs the bus acquisition request 203d to use the bus.

The bus control unit 31 arbitrates these requests and gives a bus use permission to a partner who permits the bus. Here, as the bus use permission, 204a, 204
One of b, 204c and 204d is asserted. Peripheral circuits that have obtained permission to use the bus exchange data with the external memory 40 via the bus 200.

When the bus acquisition requests from the peripheral circuits occur simultaneously, the bus controller 31 gives permission to use the bus 200 to the peripheral circuit having the highest priority among the preset priorities. When the high-order transfer is completed, the right to use the bus is transferred to the peripheral circuit having the second highest priority. That is, the transfer time is the sum of the transfer times of all the peripheral circuits.

FIG. 4 shows a conventional circuit devised to shorten the transfer time. This conventional circuit uses I / O
44, the image processing circuit 46, and the peripheral circuits of the audio processing circuit 48 are independent buses, that is, I / O.
It has a bus 300, an image bus 301, and an audio bus 302.
The DMA controllers 42a, 42b, 42c use the DMA activation requests 305a, 305b, 305 from the peripheral circuits.
Receiving c, it outputs the address of the external memory 50 and the R / W signals 351a, 351b, 351c. CPU43
Address and R / W of the external memory 50 and each peripheral circuit
The signal 351 is output. The bus control device 41 receives these address and R / W signals and transfers data.

When DMA activation requests from the peripheral circuits are simultaneously generated, the bus control device 41 makes use of a plurality of buses, and, for example, transfers data from the I / O 44 to the external memory 50 and from the external memory 50 to the image processing circuit 46. And the data transfer from the external memory 50 to the voice processing circuit 46 are performed at the same time. However, since there is only one external memory 50, there is only one external memory 50 on the bus.
Only one transfer is running.

[0009]

As described above, in the conventional information processing apparatus, only one transfer can be executed when the bus acquisition requests are simultaneously issued from a plurality of masters.
The transfer for each peripheral circuit is executed in order, and the transfer time is the sum of the transfer times of all the peripheral circuits or the sum of the access times of the external memories. When it is necessary to transfer a large amount of data within a fixed time as in mobile communication in recent years, the length of this transfer time becomes a problem.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an information processing apparatus capable of high-speed data transfer even if bus acquisition requests from a plurality of masters occur simultaneously.

[0011]

In order to solve this problem, an information processing apparatus according to the present invention is provided with a plurality of buses, a plurality of bus masters, a bus control unit, and the plurality of buses. A plurality of data storage units for storing transfer data, each of the plurality of bus masters is directly connected to each of the plurality of buses, and when two or more bus acquisition requests are simultaneously issued from the plurality of bus masters, The bus control unit performs arbitration independently for each bus and performs parallel transfer on a plurality of buses.

The bus master includes a DMA controller or CPU. According to this configuration, since the plurality of data storage units for storing the transfer data are provided corresponding to the plurality of buses, when a plurality of bus acquisition requests for different buses are simultaneously issued from the plurality of bus masters, The bus control unit performs arbitration independently for each bus, so that data is transferred from each bus master to each data storage unit and vice versa, independently of other buses. As a result, it is possible to provide an information processing device capable of high-speed data transfer by performing parallel transfer using a plurality of buses.

In the information processing apparatus, the bus control unit has a priority storage unit that stores a priority order among a plurality of bus masters for each of the plurality of buses, and obtains two or more buses for one bus. When the requests conflict, it is preferable to refer to the priority storage unit to determine the priority of use of the bus.

According to this structure, when there are a plurality of bus masters issuing an acquisition request to one bus, the priority order is set in consideration of the functions of these bus masters so that one bus Even if two or more acquisition requests compete with each other, data transfer can be efficiently performed without significantly affecting the processing efficiency of the entire information processing apparatus.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, 1 is a bus controller, 2a, 2b and 2c are DMA controllers, 3 is a CPU, 4 is serial input / output (I / O) such as USB and UART, 5 is an I / O memory, and 6 is image processing. Reference numeral 7 is an image memory, 8 is an audio processing circuit, and 9 is an audio memory. 100, 101, 102 are respectively
It is a dedicated bus for I / O, image, and audio data, and each can execute data transfer independently.

The I / O 4, the image processing circuit 6 and the audio processing circuit 8 are respectively DMA controllers 2a, 2b and 2c.
To the DMA start request signals 105a, 105b, 10
5c is output. DMA controllers 2a, 2b, 2c
When receiving the DMA start request signal, the bus acquisition request signals 103a, 103b, 103c are sent to the bus control device 1.
Is output. In order to use the bus, the CPU 3 outputs a bus acquisition request signal 103d and a bus selection signal 106 that selects one of the three buses.

The bus control device 1 arbitrates these requests and gives a bus use permission to a partner who permits the use of the bus. At this time, the bus control device 1 asserts one or more of the bus use permission signals 104a, 104b, 104c, 104d. The peripheral circuit receiving the bus use permission signal is permitted to use the bus and can perform the transfer.

FIG. 2 is a block diagram showing the internal configuration of the bus controller 1 and the DMA controller 2a.

As shown in FIG. 2, the bus controller has a priority register 51 for setting priorities and an arbitration circuit 52.
It has and. The priority register 51 is an arbitration circuit 52.
The priority signal 120 is output to. The arbitration circuit 52 uses the priority signal 120 and the DMA controllers 2a, 2
bus acquisition request signal 103 from b, 2c and CPU 3
a, 103b, 103c, 103d, and performs bus arbitration signals 104a, 104b, 104
c, 104d to the DMA controllers 2a, 2b, 2c
And to CPU3.

The DMA controller 2a also includes a start control circuit 53, a transfer count control circuit 54, an address control circuit 55, and a bus interface circuit 56. The activation control circuit 53 receives the DMA activation request signal 105a from the I / O 4, and receives the DMA activation request signal 105a from the arbitration circuit 5 of the bus control device 1.
2, the bus acquisition request signal 103a is asserted. The transfer number control circuit 55 obtains the remaining transfer number by subtracting 1 from the value of the counter for each transfer, and outputs this as the transfer remaining number signal 121 to the activation control circuit 53. When the value represented by the remaining transfer count signal 121 becomes 0, the activation control circuit 53 negates the bus acquisition request signal 103a.

In the address control circuit 55, an initial value of an address to read / write is set. Also, 1
The address is added or subtracted for each transfer to indicate the next transfer address. The bus interface circuit 56 is I
Address and read / write signals are issued to the / O bus 100 to read / write data.

The DMA controllers 2b and 2c are also
It has the same structure as the above-mentioned DMA controller 2a,
Do the same.

Here, the operation when a plurality of DMA activation requests are simultaneously generated from the peripheral circuits will be described in detail. I / O
Each of the bus 100, the image bus 101, and the audio bus 102 has an exclusive memory, that is, an I / O memory 5, an image memory 7, and an audio memory 9. The CPU 3 reads necessary data from these memories, processes the data, and stores the processed data in the same memory again. Each of the DMA controllers 2a, 2b, 2c has an I / O bus 1
00, the image bus 101, and the audio bus 102 are transferred.

Therefore, a plurality of DMA activation request signals 105a, 105b, 105c for the respective DMA controllers 2a, 2b, 2c are simultaneously generated from the peripheral circuits I / O 4, the image processing circuit 6, and the audio processing circuit 8. However, because these are transfers in different buses,
The bus control device 1 includes all DMA controllers 2a,
2b and 2c, the bus use permission signal 104a,
Asserts 104b and 104c. This gives I /
Transfer between the O4 and the I / O memory 5 via the I / O bus 100, transfer between the image processing circuit 6 and the image memory 7 via the image bus 101, and the audio processing circuit 8. Transfers to and from the audio memory 9 via the audio bus 102 occur simultaneously. That is, parallel transfer by a plurality of buses is executed.

The operation when there is a transfer request from the CPU 3 is as follows. The priority order register 51 of the bus control device 1 stores the order of priority among the masters on each bus. Here, for example, the I / O bus 100
, The DMA controller 2a has a higher priority than the CPU 3, and the image bus 101 is DMA
The controller 2b has a higher priority than the CPU 3, and for the audio bus 102, the DMA controller 2
It is assumed that c has a higher priority than the CPU 3 and is set in the priority register 51.

Bus acquisition request 1 of DMA controller 2b
When the 03 signal b and the bus acquisition request signal 103d for the image bus 101 of the CPU 3 occur at the same time, the bus control device 1 determines that these requests are conflicts on the same bus.
When it is determined that parallel execution is not possible, the bus use permission is first given to the DMA controller 2b according to the priority order, and the DMA
When the transfer of the controller 2b is completed, the bus use permission is given to the CPU 3.

On the other hand, for example, the I / O bus 10 of the CPU 3
When the bus acquisition request signal 103d for 0 and the bus acquisition request signal 103b of the DMA controller 2b occur at the same time, the bus control device 1 performs these transfers on different buses and can execute them in parallel. Then, the DMA controller 2b is given permission to use the image bus 101, and the CPU 3 is given permission to use the I / O bus 100.

As described above, according to the configuration of this embodiment, since the plurality of memories corresponding to the respective peripheral circuits are directly connected to the plurality of buses corresponding to the respective peripheral circuits, a plurality of DMAs are provided. Even when a plurality of bus acquisition requests are simultaneously issued from the controller or the CPU, the bus controller performs arbitration independently for each bus, so that each DMA controller transfers data to each memory, or vice versa. Data transfer is performed independently. As a result, it is possible to provide an information processing device capable of high-speed data transfer by performing parallel transfer using a plurality of buses.

Further, according to the configuration of the present embodiment, the priority order of the bus use permission is set for the DMA controller and the CPU that issue the acquisition request to one bus, so that one bus can be used. Even if two or more bus acquisition requests compete with each other, data transfer can be efficiently performed without significantly affecting the processing efficiency of the entire information processing apparatus.

The present embodiment does not limit the present invention, and various modifications can be made within the scope of the invention.
For example, the number of DMA controllers and CPUs as bus masters, the type and number of peripheral circuits, the number of buses, and the like are not limited to the examples shown in this embodiment.
It is optional.

[0032]

As described above, according to the present invention,
Even if a plurality of DMA requests are simultaneously issued from a plurality of bus masters, high speed data transfer can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail the internal configurations of a DMA controller and a bus controller in the information processing apparatus.

FIG. 3 is a block diagram showing an example of a conventional information processing device (single bus configuration).

FIG. 4 is a block diagram showing an example of a conventional information processing device (multi-bus configuration).

[Explanation of symbols]

1 Bus control device 2a-2c DMA controller 3 CPU 4 I / O 5 I / O memory 6 Image processing circuit 7 Image memory 8 Audio processing circuit 9 Voice memory 10 External memory 51 priority register 52 Arbitration circuit 53 Start control circuit 54 Transfer count control circuit 55 Address control circuit 56 bus interface circuit 100 I / O bus 101 image bus 102 voice bus 103a to 103d Bus acquisition request signal 104a to 104d bus use permission signal 105a to 105c DMA start request signal 106 Bus selection signal 121 Remaining transfer count signal

Claims (2)

[Claims] 1. A plurality of buses, a plurality of bus masters, a bus control unit, and a plurality of data storage units which are provided corresponding to the plurality of buses and store transfer data. When each is directly connected to each of the plurality of buses and two or more bus acquisition requests are simultaneously issued from the plurality of bus masters, the bus control unit performs arbitration independently for each bus and performs parallel transfer on the plurality of buses. An information processing device characterized by performing. 2. The bus control unit has a priority storage unit that stores the priority of a plurality of bus masters for each of the plurality of buses, and two or more bus acquisition requests compete for one bus. In this case, refer to the priority storage section,
The information processing apparatus according to claim 1, wherein the priority of use of the bus is determined.