JP2003066123A - Test method, test apparatus and method for constructing test apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of constructing a tester for semiconductor device suitable to respective programs described in a tester language while reducing the required test cost. SOLUTION: One apparatus is constituted so as to be changeable into a plurality of testers of different architecture, e.g. a logic tester capable of inspecting a logical circuit including a combination logic effectively or a memory tester capable of inspecting a memory circuit effectively. The apparatus is changed by selecting any one of the plurality of changeable testers and an object to be tested is tested using the changed apparatus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technique for testing a semiconductor device such as a semiconductor memory or a logic integrated circuit, and a technique for constructing a tester suitable for testing a semiconductor device to be inspected. For example, the present invention relates to a tester using a variable logic circuit that can configure any logic.

[0002]

2. Description of the Related Art As a test method of a semiconductor device such as a logic integrated circuit (hereinafter referred to as a logic IC), a device called a tester generates test pattern data, inputs the test pattern data to the logic IC, and outputs the test pattern data. There is a method of comparing and determining the data signal and the expected value. Also, recently, flip-flops on the input / output side of an internal logic circuit, which means a combinational logic circuit inside a semiconductor device, are connected so as to form a shift register during a test operation, and test data is input to this shift register. There is also a scan path system in which the internal logic circuit is operated based on the data held in the flip-flop, the output of the internal logic circuit is serially output through the shift register, and the output is inspected.

Further, there is a BIST (Built in self test) type test technique having a built-in pattern generating circuit for generating a random test pattern such as a pseudo random number generating circuit. The tester also performs input / output of the test pattern in the scan path method, comparison / judgment of the scanned out data with the expected value, designation of the operation mode in the BIST method, and the like.

A tester capable of inspecting a logic circuit including the above combinational logic is generally called a logic tester. In addition to such a logic tester, there is a memory tester for inspecting a memory. A memory is also a type of logic circuit, but it is often used as a memory-only tester because the test pattern generation algorithm differs from that of a tester of a combinational logic circuit. Further, among the logic testers, the scan path type or BIST type tester is called a structural tester because it is configured to focus on the logical structure of the device under test and generate a test pattern suitable for the logical structure. .

By the way, the testers currently offered to the market by the tester makers use their own tester languages, and the user refers to the tester language manual provided by the tester makers to test the testers. It is common to create programs and test patterns. On the other hand, in recent years, a company called a test house developed by a semiconductor device manufacturer to undertake testing of semiconductor devices has appeared, and horizontal division of labor is also progressing.

[0006]

The conventional tester can perform as many various test items as necessary and can be tested in order to test a wide variety of newly developed semiconductor devices. With respect to the performance and the number of pins of a semiconductor device, the device is configured to be compatible with a wide range of operating frequencies and the expected maximum number of pins, and is provided as an extremely versatile device. Therefore, there is a problem that it is very expensive.

Further, when a user tests a newly developed semiconductor device, depending on the scale of the semiconductor device to be tested, only some of the functions of the tester may be used, and the conventional tester is extremely redundant. It is a highly flexible device, and it may be replaced by the unit price of chips,
If the cost cannot be increased due to the competition in the market and the demand, the cost will be broken.

In order to reduce the huge cost of such a tester, horizontal division of labor by a test house is effective, but the test house has the same tester as the tester of a semiconductor device manufacturer or a design company, which is a customer. There is a problem that the load on the test house is large because it is necessary to convert the test pattern created by the customer into a test pattern suitable for the tester owned by the test house.

An object of the present invention is to provide a technique capable of constructing a tester for a semiconductor device which requires less required test cost. Another object of the present invention is to provide a technique capable of constructing a semiconductor device tester suitable for each test program written in a tester language. Still another object of the present invention is to provide a technique capable of easily constructing a tester for a semiconductor device. Still another object of the present invention is to provide a technique capable of constructing an arbitrary tester having a different architecture. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, one device is configured to be changeable into a plurality of testers having different architectures such as a logic tester capable of effectively inspecting a logic circuit including combinational logic and a memory tester capable of effectively inspecting a memory circuit, and the above-mentioned change is possible. It is configured such that any one of the plurality of testers is selected to change the device, and the inspection target is tested by using the changed device. In this specification, such a device is referred to as a variable tester.

Here, the variable tester that can be changed to any of a plurality of testers is, for example, an FPGA (field
This can be realized by configuring a main part of the tester by using a variable logic integrated circuit called a programmable gate array) capable of configuring any logic. According to the above-mentioned means, a tester having a desired function can be built in the variable tester by using the tester construction data described in HDL (Hardware Description Language: Hardware Description Language). By carrying out the test of the semiconductor device to be tested by using, it is possible to carry out the test without using a commercially available tester. Moreover, because the tester that is most suitable for the tester language to be used can be built in the variable tester, you can test the test program or test pattern created in any tester language without converting it. The total cost required for the test can be reduced.

The tester construction data may be generated based on a test program written in the tester language. That is, a general engineer involved in the test recognizes the tester architecture relatively easily by analyzing the test program for the test target semiconductor device described in the tester language and examining the test pattern generation algorithm. Therefore, the description of the tester (tester construction data) can be generated by HDL based on the recognized architecture.

Further, the description of the tester in HDL is such a function entry tool (for example, "Vis provided by AT Service Co., Ltd.").
ual Test ") is provided by the EDA vendor, and can be efficiently performed by using the tool. Also, a tool (for example, "Leonardo") that builds logic in the FPGA from the HDL description is
Since it is provided by the DA vendor, the logic of the tester can be easily built in the FPGA by using the tool. Furthermore, the data for constructing the tester for testing the semiconductor device to be tested in the FPGA based on the test program written in the tester language can be created on the computer.

Therefore, for example, a test house receives a test program created by a semiconductor maker or a design company regarding a semiconductor device for its own design from the semiconductor maker or the design company via the Internet or the like, and the test program is used as a tester program. Recognize the architecture and F
Create data for building in PGA. And
By using the tester construction data, it is possible to construct a tester having the same function as the tester owned by the semiconductor manufacturer or the design company in the variable tester configured by the FPGA owned by the test house to test the semiconductor device. it can.

As a result, the test of the semiconductor device, which is created by the semiconductor maker or the design company and is effective for the semiconductor device related to the design of the semiconductor maker or the design company, is executed without conversion, and the test of the semiconductor device is executed. As a result, it is possible to shorten the test time and improve the fault coverage.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an embodiment of a variable tester according to the present invention. In FIG. 1, 100
Is a tester main body, 200 is a test station in which a semiconductor device DUT which is a device under test is mounted, 300 is the test station 200 and the tester main body 100.
And a cable for connecting the variable tester 100.
Engineering that sends and controls data to
Workstation-like computer 510,5
Reference numeral 20 is a data file for storing the data sent to the variable tester 100. The data file 510 stores tester construction data, and the data file 520 stores test programs and test patterns.

The tester main body 100 includes a system configuration board 110 having a plurality of LSIs mounted therein and a power supply board 120 for generating a power supply voltage supplied to a semiconductor device which is a device under test.
A plurality of FPGAs 130 capable of forming an arbitrary logic are mounted on 10. Also, the system configuration board 110
An analog test circuit 170 that generates an arbitrary waveform and observes the analog signal waveform output from the device under test and measures the DC level is mounted on some of the boards.

Most of the system configuration board 110 in the tester main body 100 shown in FIG. 1 is a board on which an FPGA is mounted. This is because the logic scale of the FPGA currently provided is not yet large enough to construct a tester, and several tens to several hundreds of FPGAs are considered necessary. However, once an FPGA with a large logic scale becomes available, it will be possible to use one
It is also possible to configure the tester with several boards.

The FPGA is composed of a plurality of variable logic circuits and variable wiring means which is composed of, for example, an orthogonal wiring group and a switch matrix and which can arbitrarily connect the plurality of variable logic circuits. A logic circuit forms a basic circuit such as a logic gate circuit such as a NAND circuit or a NOR circuit or a flip-flop circuit, and the variable wiring means connects these logic gate circuits or basic circuits to each other. It is configured so that a circuit having a logical function can be constructed.

As such an FPGA, for example, a one-chip LSI (model number EP with a scale of 130K gates from Altera, Inc.
Since the F10K130E) is provided, each system configuration board 110 and the tester main body 100 can be configured by using it. The analog test circuit 170 is also an analog F that can configure any analog circuit.
It may be constructed using PGA. Above FPG
It is desirable that A and the analog FPGA are assembled on the same board. This is because it becomes easier to transmit and receive signals to and from each other, the number of power supply voltages required for each board can be reduced, and the connection with the interface board in the test station can be easily performed.

In the test station 200, for example, a plurality of interface boards 210 called pin electronics connected to the input / output terminals of the semiconductor device DUT which is the device under test are radially arranged, and the device under test (DUT) is arranged in the center thereof. Are arranged. The interface board 210 and the device under test DUT can be connected in the same manner as in the existing tester, and thus the description of the specific example is omitted. Although only one test station is shown in FIG. 1, a plurality of similar test stations are provided for one tester main body so that a plurality of devices under test can be tested at the same time. .

FIG. 2 shows a more detailed configuration example of the tester main body 100 that enables an arbitrary test circuit to be configured using the FPGA. As shown in the figure, the tester main body 100 includes a plurality of sub-boards 111 having a plurality of FPGAs 130 mounted in parallel and an FPG.
A plurality of system configuration boards 110 provided with a plurality of memories 112 for storing connection information of A and system control information and an input / output IC 113 are incorporated. An external computer 50 is installed in the tester main body 100.
I / O interface circuit 181 for transmitting / receiving data to / from 0, control circuit 182 for controlling the entire system including signal transmission between system configuration boards 110, clock generation for generating a clock signal inside the system The circuit 183 and the like are incorporated.

The tester main body 100 of the embodiment includes an FP on the system configuration board 110 from an external computer 500.
A test circuit having a desired test function is constructed by writing FPGA connection information in the GA 130 or the memory 112. Then, the external computer 50
I / O interface circuit 18
1 to the control circuit 182, and the control circuit 182 receives each system configuration board 11 based on this input signal and the clock signal from the clock generation circuit.
It is configured to operate as a test circuit by forming a control signal for 0 and operating the FPGA on the board in cooperation.

FIG. 3 shows a schematic configuration when the tester is functionally represented. As shown in FIG. 3, the tester 100 includes a power supply unit 12 that supplies a power supply voltage to a semiconductor device DUT as an electronic component that is a device under test.
0 ′, a pattern generator 140 that generates test data and an expected value that are input to the semiconductor device DUT, a timing generator 150 that generates an application timing of a signal that is input to the semiconductor device DUT, and a voltage level detection of an output pin. DC test circuit 1 for performing DC test
70 'and a controller 160 for controlling these circuits
Etc.

The power supply unit 120 'shown in FIG. 3 is composed of the power supply board 120 shown in FIG. The DC test circuit 170 'is composed of the analog test circuit 170 shown in FIG. The power supply unit 120 ′ and the DC test circuit 170 ′ are not like a test program that is replaced when the tester changes, and it is not necessary to change the configuration according to the device under test, and they are common circuits. be able to. In addition to the above, the tester 100 of FIG. 3 includes a driver 220 that inputs a signal to an input pin of a semiconductor device DUT to be tested and a comparator that compares a signal output from an output pin of the semiconductor device DUT with an expected value signal. 230 are shown, which are provided on the interface board 210 of the test station 200 in FIG.

In the variable tester of this embodiment, the interface boards 210 of the test station 200 do not all have the same configuration, and, for example, depending on the frequency of the signal transmitted / received to / from the semiconductor device DUT, for example, Three types of interface boards for high speed, low speed and medium speed are prepared. From the viewpoint of the function of the tester, it is most preferable that all the interface boards 210 have a high-speed specification, but if this is done, the performance requirements for the hardware of the tester become very strict and the cost of the tester increases.

On the other hand, paying attention to the semiconductor device DUT to be tested, it is expected that future semiconductor devices will adopt a test facilitation technique and will be equipped with a scan test path and a BIST circuit. The pins do not have to be fast. Therefore, as described above, if three types of interface boards for high speed, low speed, and medium speed are prepared, the test can be executed, and for low speed and medium speed, the hardware requirements are not as severe as for high speed. The price of the tester can also be kept low.

Specifically, as shown in FIG. 4, the semiconductor device DUT to be tested has a speed of 50 to 200 MHz with respect to the input / output pin SCAN of the scan test path, and the semiconductor device DUT is scanned by the test data. Clock pin CLK for operating the combinational circuit in the device DUT and for executing the test by the BIST circuit
With respect to, it is considered that a speed of 800 MHz or more will be required. On the other hand, the transmission / reception between the BIST circuit and the tester has a short operation time only by giving an initial value or a start command before the test starts, so that the speed required for the input / output pins of the BIST circuit is much lower than 10 kHz.
The following speeds are considered good.

Regarding the number of pins of the semiconductor device DUT, it is expected that the number of clock pins is the smallest, followed by the number of scan-in / scan-out pins and the largest number of input / output pins for the BIST circuit. Therefore, in the tester of this embodiment, several hundred interface boards FFB for scan test (128 to 256) are provided for one to two interface boards CKB for clock supply.
Number of interface boards RFB for BIST
000 sheets (512 to 4100 sheets) and several interface boards DTB for DC test are prepared. By providing the three types of interface boards at such a ratio, the conditions for the circuits configured on the system configuration board in the tester main body are also relaxed except for the clock. As a result, it is possible to realize a tester that can execute all required tests while suppressing the increase in the price of the tester.

Next, the FPGA 130 on the system configuration board 110 in the tester main body 100 and the driver 220 and comparator 230 on the interface board 210.
And the semiconductor device DU of the device under test.
An example of the configuration (architecture) of a test circuit that generates a test signal and an expected value signal to be given to T, and compares the signal output from the semiconductor device DUT with the expected value to determine
This will be described with reference to FIGS.

Although not particularly limited, the circuits of FIGS. 5 and 6 generate signals with various timings such as a test signal and an expected value signal for the input / output pins of the scan test of the device under test DUT. An example of a possible circuit is shown. The circuit of FIG. 5 has an ALPG (Algorithmi) that can generate a test pattern according to a predetermined procedure.
c Memory Pattern Generator) has a similar configuration to a circuit called. For example, regarding a combinational logic circuit, there is known an efficient test pattern generation method called a D algorithm based on the fault assumption method and the idea that there is one fault in one circuit.
Also in the circuit of this embodiment, the ALPG using this method is used.
Can be

The circuit shown in FIG. 5 has an instruction memory 4 in which a microprogram consisting of a plurality of microinstruction groups described according to a predetermined test pattern generation algorithm is stored.
11, a program counter 412 for designating a micro instruction to be read from the instruction memory 411, an instruction memory 4
11, an instruction decoding control circuit 430 that decodes the instruction code in the micro instruction read from 11 to form a control signal for the program counter 412 and the like, a timing generator 420 that forms a timing control signal based on the reference clock φ0, The timing generator 4 based on the timing setting bit MFd (TS bit) in the micro instruction.
Data register set 417 for outputting control data for 20 and timing setting bit MF in the microinstruction
A decoder 418 for decoding d (TS bits) and reading control data from the data register set 417 is provided.

In the circuit of this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 418 is composed of 2 bits, and the data register set 417 stores seven pieces of control data. One of these control data is data “RATE” that defines the test cycle, and the remaining six control data are two types of data that give the output timing of the high level signal or the low level signal for each generated signal. Control data “AC
LK1 ”,“ ACLK2 ”and two types of control data“ BCLK1 ”, which give rise timing of the pulse signal,
Two types of control data "CCLK1" and "CCLK2" that give the comparison output timing of "BCLK2" and the fall timing of the pulse signal and the expected value.

When each of these control data is supplied to the timing generating section 420, a signal RATE of a predetermined timing is supplied to the program counter 412 for the control data RATE, and the micro instruction code from the instruction memory 411 is supplied. Capture is performed. Further, when “ACLK1” to “CCLK2” are supplied as the control data to the timing generation section 420, the clock corresponding to the control code is output from the timing clocks ACLK1 to CCLK2 to the driver & comparator circuit 240. Connections and selections for use of each clock are appropriately performed as needed.

Further, in the circuit of FIG. 5, the incrementer 421 for incrementing the value of the program counter 412 to "+1" and the incrementer 42 are provided.
A multiplexer 422 which selects either 1 or a jump destination address in the address field MFa and supplies it to the program counter 412; an index register 423 which holds the number of repetitions in the operand field MFc;
The decrementer 424 for decrementing the value of the index register 423 by "-1", the working register 425 holding the value decremented by "-1", the presence or absence of transfer of the operand used in a predetermined instruction to the program counter 412 Flag 427, registers 423, 42
A multiplexer 428 that selectively supplies the value of 5 to the decrementer 424, a demultiplexer 429 that distributes the value of the decrementer 424 to any plane of the working register 425, and the like are provided.

In the circuit of this embodiment, since the microinstruction code is provided with the operand field MFc for storing the number of repetitions of the instruction and the index register 423 for holding the number of repetitions, the same test signal is repeatedly generated. be able to. Further, in the circuit of this embodiment, since the index register 423, the working register 425, and the flag 427 are provided in a plurality of planes (four in the figure), a sub-loop process in a loop process and a sub-loop process in the sub-loop process are performed. Processing and the like can be easily executed.

FIG. 6 shows an embodiment of the driver & comparator circuit 240. In the circuit of FIG. 6, only the driver and the comparator provided on the interface card 210 corresponding to one of the input / output pins of the device under test are shown as a representative, but in reality, the interface card 210 A predetermined number of circuits shown in FIG. 6 are provided. The control circuit 410 of the embodiment of FIG.
Is provided as a common control circuit for a plurality of driver & comparator circuits 240 that generate output signals or expected value signals for a plurality of input / output pins of the device under test, and can form a plurality of signals with one microinstruction. Is configured.

As shown in FIG. 6, the driver & comparator circuit 240 of this embodiment compares a driver circuit (signal forming circuit) 220 which forms a signal to be output with an input signal and an expected value signal to obtain a match / match. A comparator circuit (comparison circuit) 230 for comparing disagreements, and a switching circuit 26 for switching between the driver circuit 220 and the comparator circuit 230.
It consists of 0 and. The switching circuit 260 includes a transmission gate TG1 provided between the driver circuit 220 and the input / output node Nio, and a transmission gate TG2 provided between the input / output node Nio and the comparator circuit 230. In response to a signal "I / O" based on the input / output control bit supplied from the instruction memory 411, one of them is opened and the other is cut off.

The driver circuit 220 receives the signal "TP" based on the input / output control bit TP by the timing clock ACLKn supplied from the timing generator 420 and holds the edge trigger flip-flop 34.
1 and O which is the logical sum of the timing clocks BCLKn and CCLKn supplied from the timing generator 420.
An R gate 342, a J / K flip-flop 343 which receives the output of the OR gate 342 and the output of the edge trigger type flip-flop 341 as input signals, and the J / K
A signal "C" based on the output of the flip-flop 343 and the input / output control bit CONT supplied from the instruction memory 411.
AND gate 344 having ONT "as an input signal, and an AND gate having an output of the edge trigger flip-flop 341 and a signal" CONT "based on the input / output control bit CONT supplied from the sequence control circuit 410 as input signals 345 and these AND gates 344,
It is composed of a driver 346 which operates by the output of 345.

On the other hand, the comparator circuit 230 includes an input determination circuit 360 for determining a signal supplied via the transmission gate TG2, a timing clock CCLKi supplied from the timing generator 420, and an input / output supplied from the instruction memory 411. Signal "C" based on control bit CONT
AND gate 351 whose input signal is "ONT", and AND gate 35 whose input signal is the output (determination result signal) of this AND gate 351 and the input determination circuit 360
3 and a flip-flop 354 that latches the output of the AND gate 353, and a signal obtained by taking the logical sum of the outputs of all the comparator circuits 230 is output as a total fail signal TFL.

The input judging circuit 360 judges whether the input signal is higher than a predetermined level VOH or not.
1a, a comparator 361b that determines whether the input signal is lower than a predetermined level VOL, and a comparator 361.
The signal "CO" based on the output signal of a and the control bit CONT
AND gate 362a that receives "NT" and an output signal of the comparator 361b and a signal "CONT" that is based on the control bit CONT.
b, the output signal of the comparator 361a and “CON
NAND gate 363a receiving the inverted signal of T "as an input
And the output signal of the comparator 361b and "CONT"
A NAND gate 363b which receives the inverted signal of
An OR gate 364 which receives the output signals of the NAND gates 363a and 363b, and the D-type flip-flop 3 described above.
41 output (expected value) and gates 362a, 362b, 3
AND gates 353 and 35 having the output of 64 as an input signal
4,355 and OR with the output of these gates as input
It is composed of a gate 356 and outputs a signal indicating a result of comparison between an input signal and an expected value.

By the way, as shown in FIG. 5, the micro instruction stored in the instruction memory 411 includes an address field MFa in which a PC address indicating a jump address of an instruction used in the jump instruction is stored. Opcode field MFb in which the sequence control code is stored
An operand field MFc for storing the number of times of instruction repetition, a timing setting field MFd for storing a timing setting bit TS for reading a control signal for the timing generator 420 from the data register set 14, and the driver & The input / output control field MFe stores the input / output control bit of the comparator circuit 240.

The timing setting bit TS stored in the timing setting field MFd is 2 bits in this embodiment as described above, but may be 3 bits or more. Further, the input / output control bits stored in the input / output control field MFe have a set of 3 bits of the driver bit TP, the I / O bit and the control bit CONT corresponding to the n input / output pins. , N sets are provided. Of these bits, I / O
The bit is a control bit for specifying input or output. When it is "1", the transmission gate TG1 is opened and TG2 is cut off to output the output signal of the driver. When it is "0", the transmission gate TG1 is cut off and TG2 is opened to input the input signal to the input / input determination circuit 352 for comparison. The driver bit TP and the control bit CONT specify a high output or a low output, a positive pulse or a negative pulse output, an input invalid state, or an output high impedance state according to the combination.

Table 1 shows the input / output control bits TP and I.
The relationship between / O, CONT and the test signal (test pattern) output from the driver & comparator circuit 240 is shown.

[0045]

[Table 1]

As shown in Table 1, when the input / output control bits TP, I / O and CONT are "111", the driver circuit 230 outputs a high level signal and "01".
When it is "1", the driver circuit 230 outputs a low-level signal, when it is "110", the driver circuit 230 outputs a positive pulse signal, and when it is "010", the driver circuit 230 outputs a negative pulse signal. The control is performed to Also, the input / output control bits TP, I / O, CONT
Is "101", the comparator circuit 220 expects a high-level input signal, and when "001", the comparator circuit 220 expects a low-level input signal.
When it is "00", the control is performed so that the comparator circuit 220 expects a high impedance state as an input.

In the embodiment shown in FIG. 6, a comparator 361 for comparing the input signal with VOH and VOL in the input judgment circuit 360.
Since a and 361b are provided, it is possible to detect an input high impedance state in which the node Nio is at a high level and a low level intermediate level. In the driver & comparator circuit 240 of this embodiment, the state in which the control bits TP, I / O, and CONT are "100" has no meaning.

FIG. 7 shows the timing clock ACLK supplied from the timing generator 420 in the above embodiment.
1 to CCLK2 and an example of signals output from the driver & comparator circuit 240 are shown. In FIG. 7, (a) shows the supplied reference clock φ0 as (b)-
(G) shows the waveforms of the timing clocks ACLK1 to CCLK2, and (h) shows the waveform of the output signal of the terminal in which "1" is specified as the test pattern in Table 1 and ACLK1 is selected as the clock. Further, (i) shows the waveform of the output signal of the terminal in which "0" is designated as the test pattern in Table 1 and ACLK2 is selected as the clock.
Further, (j) shows the waveform of the output signal of the terminal in which "P" is designated as the test pattern in Table 1 and BCLK1 and CCLK1 are selected as the clocks. Furthermore, (k)
Shows the waveform of the output signal of the terminal in which "N" is designated as the test pattern in Table 1 and BCLK2 and CCLK2 are selected as the clocks.

As can be seen from FIG. 7, the input / output control bits TP, I / O, CONT are set to "111", and the clock ACLK1 is supplied from the terminal designated by the clock ACLK1.
1 outputs a high level signal as shown in FIG. 7 (h), sets TP, I / O, CONT to "011" and designates the clock ACLK2 from the terminal to which the clock AC is supplied.
A low level signal as shown in FIG. 7 (i) is output according to LK2, TP, I / O, CONT are set to "110", and clocks ACLK1, BCLK1, and CCLK1 are set by the clock ACLK1 from the designated terminals. FIG. 7 with BCLK1 and CCLK1 as edges according to the data.
A positive pulse as shown in (j) is output, and TP, I / O, C
ONT is set to "010" and clocks ACLK2, B
CLK2 and CCLK2 are output from the specified terminals according to the data set by the clock ACLK2.
A negative pulse as shown in FIG. 7 (k) having CLK2 as an edge is output.

Although not shown, the input / output control bit T
At the terminal where P, I / O and CONT are set to "101" and the clock CCLK1 is designated, the expected value is set to the high level and the clock CCLK1 of FIG. 7 (f) is used as the strobe signal for comparison. Furthermore, TP, I / O, C
At the terminal where ONT is set to "001" and the clock CCLK2 is designated, the expected value is set to the low level, and the expected value is set to FIG.
The clock CCLK2 is used as a strobe signal for comparison. The selection of clocks is not limited to the above, and any combination can be used.

FIG. 8 shows an example of a circuit that generates a signal whose timing is not so important and whose logic level is important, such as a test signal and an expected value signal for an input / output pin for BIST of the device under test DUT. 9 is a driver & comparator circuit 24 used in the circuit of FIG.
A configuration example of 0 is shown. Also in this embodiment, the driver &
The comparator circuit 240 is provided on a plurality of interface boards, and the control circuit 410 of FIG. 8 is provided as a common control circuit for the plurality of driver & comparator circuits 240 so that one micro instruction can form a plurality of signals. Is configured.

The control circuit 410 shown in FIG. 5 and FIG.
8 is different from the control circuit 410 shown in FIG. 8 in that the circuit of FIG. 8 controls the timing in the data register set 417 specified by the data (TS bit) stored in the timing setting field MFd of the microinstruction. There are few types of data and the input / output control field MFe
Has two control bits TP and I according to the test pattern.
Only / O is stored (no CONT bit). Also, in this embodiment, the timing generation circuit 420
Timing clock output from ACLK1, CC
It is two of LK1. Further, since the input / output control bits of the instruction memory 411 are two, TP and I / O,
The driver & comparator circuit 240 has a simpler configuration than the circuit of FIG.

Table 2 shows the input / output control bits TP, I / O and the driver & comparator circuit 24 in the circuit of FIG.
The relationship with the test signal (test pattern) output from 0 is shown.

[0054]

[Table 2]

As shown in Table 2, the driver circuit 23 when the input / output control bits TP and I / O are "11".
Control is performed so that 0 outputs a high level signal, and when it is "01", the driver circuit 230 outputs a low level signal. Also, the input / output control bits TP, I / O
When the value is "10", the comparator circuit 220 expects a high-level input signal, and when the value is "00", the comparator circuit 220 expects a low-level input signal. Further, in this embodiment, since it is not necessary to judge the intermediate level of the input, the input judging circuit 3 shown in FIG.
Instead of 60, it is possible to replace it with a simpler exclusive OR gate.

FIG. 10 shows a configuration example of a circuit for generating a high-frequency clock signal input to the clock pin of the logic IC, and FIG. 11 shows a configuration example of the driver circuit 220 used in the circuit of FIG.

The control circuit 410 shown in FIG. 8 and FIG.
The difference from the control circuit 410 shown in FIG.
In the circuit of FIG. 10, the number of kinds of timing control data stored in the data register set 417 is smaller, and the micro instruction does not have the timing setting field MFd and the input / output control field MFe, and the clock pattern CKPT is designated instead. The point is that the field MFf is provided. In this embodiment, the control circuit 41
0 is configured as a circuit common to the driver & comparator circuits 240 of a plurality of (two in the figure) pins. The driver and comparator circuit 240 includes the driver circuit 22.
Only 0 is provided, and the comparator circuit 230 and the input / output switching circuit 260 are omitted.

The driver circuit 220 outputs the timing clock ACLK output from the timing generation circuit 420.
1, BCLK1, CCLK1 and a clock pattern CKPT read from the field MFf of the microinstruction, a clock signal of a predetermined timing is generated. Circuits composed of FPGAs generally have a slower circuit operation, but with the circuit configurations shown in FIGS. 10 and 11, a high-speed clock signal can be generated.

Next, a method of constructing a test circuit having the configuration shown in FIGS. 5, 8 and 10 in the FPGA in the tester main body 100 of the variable tester including the FPGA of the embodiment of FIG. 1 will be described. It is also good to use the pin-multi method, which is generally used in testers, to increase the speed. In this case, first, the logic function of the test circuit as shown in FIG. 5, FIG. 8 and FIG. 10 is changed to HDL (Hardware Description.
(Language). The logic description in HDL may be manually made by an engineer, but for example, from RT Service Co., Ltd., “Visual
A feature entry tool called "Test" is provided so that it can be used on a computer. After that, a test circuit is constructed in the FPGA using the data described in HDL. Also, HDL
As a support tool for constructing the logic in the FPGA from the description, for example, "MA provided by Altera Co., Ltd."
X + plusll ”is available, so that it can be automatically performed by the computer.

The function entry tool displays the logic circuit on the screen of the display device in a drawing such as a block diagram and each block (called a module).
It is a tool that has a function of automatically creating an HDL description when connections between them, setting of input / output directions of signals, etc. are selected, and a module is selected and an instruction symbol, operation content, etc. are input.

By the way, if the tester manufacturer has circuit design data of the tester, based on the design data, the tester having the same function as the tester designed by himself is set in the variable tester composed of the FPGA of the embodiment of FIG. It can be built relatively easily using tools. However, even a person who does not have the circuit design data of such a tester can construct a test circuit that generates a test pattern from the test program in the FPGA if there is a test program. In other words, a semiconductor manufacturer engineer or a test house engineer who has received a test request from the semiconductor manufacturer recognizes the tester architecture from the test program created by the semiconductor manufacturer and recognizes the FPG.
A test circuit that executes the test program can be configured in A.

Specifically, first, the engineer analyzes the test program from the passed test program and the manual of the tester language describing the test program, and as a result, what the test program means, that is, what It is possible to clarify the processing procedure and what kind of data is formed. By this, the architecture of the test circuit to be supported by the test program is recognized. That is, it is possible to determine the format of the ALPG to be constructed by extracting the test pattern generation algorithm corresponding to the semiconductor device to be tested, that is, the schematic configuration (block diagram configuration of the circuit).

For example, when the semiconductor device to be tested is a memory, an ALPG for generating an address and data
Is determined, and in the case of a logic LSI, the format of ALPG for generating input data and expected value data is determined, so that the algorithm according to the semiconductor device to be tested and the format of ALPG embodying it are determined. To be done. For a normal testing engineer, a test program written in a tester language and a test operation can be recognized from the tester language manual, and the tester's architecture can be recognized from the test operation, even without a tester circuit diagram. Therefore, the format of the ALPG (test circuit) of the semiconductor device to be tested can be determined from the test program.

Next, A having the determined architecture
LPG to HDL (hardware description
The test circuit is constructed in the variable tester of the present invention, which is composed of FPGA, by using the data described in LANG) and the data described in HDL. This allows the variable tester to execute a test according to the test program delivered from the semiconductor manufacturer.

Further, according to the variable tester of the present invention, once the test by the test circuit once constructed is completed, the test circuit is reconstructed so that another tester language requested by another semiconductor manufacturer can be used. It is also possible to execute a test using the written test program. By registering the test circuit construction data that has been generated once in a database, when performing a test according to another test program written in the same tester language, you can select and change the optimum test circuit for that test program. It can be built in the tester and the test can be executed promptly.

Next, with reference to FIGS. 21 to 28, a specific procedure for generating the above-described tester (ALPG) construction data using the function entry tool will be described. Here, as an example, a case will be described in which ALPG construction data for generating a test pattern for testing a memory is generated.

The function entry tool used in this embodiment is shown in FIGS.
As shown in the figure, a drawing such as a circuit block diagram is displayed, the input / output signals of each block (hereinafter referred to as a module) and the connection between the modules are connected, and the module is selected and the command symbols and operation contents are input from the keyboard. When input, it has a function of automatically creating an HDL description sentence as shown in FIGS. The details of the function will be described below.

FIG. 21 is a description screen of the top module, and the block on the right side represents ALPG. The block on the left side is the clock signal CLK input to the ALPG.
, Reset signal RST, write enable signal WE_B
The signal source (source) that gives AR or the like to activate the ALPG and the destination (destination) of the address or data output from the ALPG are virtually represented as one block test-bench. That is,
FIG. 21 is a screen showing all the input / output signals of ALPG. Use the tool on the left side of this screen to
After all the input / output signals of the PG have been written, if the pointer is placed on the right block and clicked, the next screen appears. On this screen, as shown in FIG. 22, the basic configuration of ALPG is shown in a block diagram, and each block B1, B2
Connection between B3, B4 and B5 and setting of signal input / output direction are performed.

In FIG. 22, for example, block B2 (Se
When you click (quence Controller), the screen for the sequence control circuit appears. On this screen, as shown in FIG. 23, the contents of control by the sequence control circuit are shown in a flow chart, command symbols or processing, conditions, etc. are described in each block, and for commands such as “NOP” and “JN1”, click the block. Then, for example, "PC + 1 →
The operation contents such as "PC" are input from the keyboard. Then, the HDL description sentence regarding the sequence control circuit as shown in FIG. 26 is automatically created.

The same applies to the instruction memory, as shown in FIG.
When the block B1 is clicked in to display the next screen and the flowchart as shown in FIG. 24 is created to define conditions and processing in each block, the HDL description sentence as shown in FIG. 27 is automatically generated. Created. The same applies to the data operation circuit, and in FIG.
Click 3 to display the next screen, create a flowchart as shown in FIG. 25, define processes and registers in each block, and input the operation contents. Then, the HDL as shown in FIG. Descriptive text is created automatically.
The same applies to the address operation circuit (block B5 in FIG. 22), and an HDL description sentence as shown in FIG. 28 is automatically created.

FIG. 12 shows an example of a test procedure using the variable tester according to the present invention. First, the power of the variable tester 100 and the workstation 500 connected to the variable tester 100 is turned on (step S).
1). Next, the format (architecture) of the tester is selected from the test program of the semiconductor device to be tested (step S2). Then, the workstation 500 reads the tester construction data described in HDL of the tester having the selected architecture from the data file 510 and writes the data to the FPGA 130 or the memory 112 on the system configuration board 110 in the variable tester 100. Build a tester (step S3). Further, an OS (operating system) suitable for the tester built in the variable tester 100 is read into the workstation 500 from the data file 510 or 520 (step S4).

Subsequently, a start-up inspection before the test of the variable tester 100 is started (step S5). Then, the test program is read from the data file 520 into the workstation 500 (step S6). Then, the device under test is mounted on the test station 200, and the interface board 210 and the corresponding input / output pins of the device under test are connected. Then, a test is executed by the test program read in step S6 (step S7). When all the devices under test to be inspected have been tested, the process returns to step S2, a tester type suitable for the next device under test is selected from the test program, the tester is rebuilt in the variable tester, and another tester is constructed. The semiconductor device can be tested.

Further, the variable tester of the embodiment uses the FPGA in the tester main body to generate an AL for memory that generates a pattern for testing the memory according to a predetermined algorithm.
Since the PG can be constructed, it can also be used as a memory tester. Regarding the ALPG for the memory, the international publication WO98 previously filed by the present inventors
/ 47152 and the like, the illustration of the ALPG for memory is omitted, but such an ALPG
21 is described with reference to FIGS. 21 to 29, by using the support tool to describe in HDL, the HDL description data can be used to construct a memory tester in the FPGA in the variable tester.

FIG. 13 shows a concrete example of the analog test circuit 170 provided in the variable tester of the embodiment shown in FIG. The analog test circuit of this embodiment includes a waveform generation circuit 710 that generates an analog signal Ain input to the device under test DUT and a waveform observation circuit 720 that observes the waveform of the analog signal Aout output from the device under test DUT. Composed. Of these, the analog waveform generation circuit 710 includes DA conversion circuits 712a and 712b that DA-converts the data read from the memories 711a and 711b that store the data of the waveform to be generated, and a DA conversion circuit 712a that removes high-frequency components. , 712b to smooth the output of the filter 713a, 713b
And output amplifiers 714a and 714b for converting the voltage or current to a desired level and outputting the voltage or current.
The controller 182 stores desired waveform data in the memory 7
11A and 711b, the analog waveform generating circuit 710 is operated to store the device under test D
The analog signal Ain input to the UT can be generated and output.

On the other hand, the waveform observing circuit 720 includes input amplifiers 721a and 721b for amplifying an analog signal output from the device under test DUT, and input amplifiers 721a and 721a.
AD conversion circuit 722 for AD converting the output signal of 21b
a and 722b, memories 723a and 723b for storing data converted into digital signals, and a Fourier transform arithmetic circuit 724. It should be noted that the analog waveform generation circuit 710 and the waveform observation circuit 720 configured as described above are provided.
May be configured using a general-purpose LSI or IC, or may be configured using an analog FPGA capable of configuring an arbitrary analog circuit. Such an analog FPG
As A, International Publication WO9 filed by the present inventors earlier
Since there is one disclosed in 8/57282 or the like, it can be used.

A technique for constructing a test circuit for testing an analog circuit in an FPGA is disclosed in Japanese Patent Application No. 11-258554 previously proposed by the present inventors, and it can be used. You can In addition,
Analog HDL or SHDL (Spectrum HDL) is suitable as a language for describing data for constructing a test circuit for testing an analog circuit in FPGA.

FIG. 14 shows an embodiment of an analog FPGA. In FIG. 14, what is indicated by reference numeral SUB is one semiconductor substrate (chip) such as single crystal silicon. In the center of this chip, an analog variable function part APFB including a circuit cell block whose function can be changed from the outside and a variable wiring means which can also change the state of the wiring connection from the outside is provided. Has been. The analog variable function unit APF is provided around the analog variable function unit AFB (on the left side and the upper side in the figure).
An X decoder circuit X-DEC and a Y decoder & writing circuit Y-DEC & WDR for selecting a control data memory or a wiring connection information storage memory cell (described later) provided in B and writing the data are provided. ,
Input / output buffer cells IOB are arranged along the periphery of the chip so as to surround these circuits. Most of the input / output buffer cells IOB are the above analog variable function part A.
Although it handles an input / output signal for the PFB, some of the input / output buffer cells IOC have the above X decoder circuit X-.
It is used as a circuit that handles an input signal to the DEC or Y decoder & writing circuit Y-DEC & WDR.

The analog variable function part APFB is composed of a plurality of circuit cell blocks (CCB) arranged in an array.
1 and wiring groups 2 and 3 that are arranged vertically and horizontally and intersect each other in a cross shape between these blocks. These wiring groups 2 and 3 are arranged in a switch matrix (SM
X) circuit 4 allows corresponding lines in the vertical and horizontal directions to be connected to each other, and each circuit cell block 1 is connected to a vertical wiring group 3 by a cross point switch (CSW) circuit 5 and also crossed. The point switch circuit 6 enables connection with the wiring group 2 in the vertical direction.

The wiring groups 2 and 3 utilize the multilayer wiring technique, one (for example, the wiring group 2) along the lateral direction of the chip, and the other (for example, the wiring group 3) along the longitudinal direction of the chip. Are formed so as to be insulated from each other by different wiring layers. Although not shown in FIG. 14, the analog variable function unit APFB has a memory for storing wiring connection information such as a control data memory in the circuit cell block (CCB) 1 and a switch matrix (SMX) circuit 4. The wirings forming the data write lines and the selection signal lines for the cells are also formed by using the multilayer wiring technique.

Although not particularly limited, each of the wiring groups 2 and 3 is composed of a plurality of connection lines parallel to each other, and these connection lines are arranged in pairs of two. Among the connection lines of each pair, one line is a force line for transmitting an output signal from one circuit cell block to another circuit cell block, and the other line is a signal from the other circuit cell block to the source circuit cell block. A connection is made to function as a sense line for feeding back. Although six circuit cell blocks 1 are shown in FIG. 14 for convenience of illustration, the number of circuit cell blocks 1 is not limited to this, and may be any number. In practice, it is desirable to integrate as many circuit cell blocks as there are elements that make up the IC to be simulated.

FIG. 15 shows a circuit diagram of a configuration example of the circuit cell block 1. Each circuit cell block 1
An input amplifier 11 that amplifies an analog input signal, and an A / that converts the amplified analog input signal into a digital signal
A D conversion circuit 12, a signal processing circuit 13 having a configuration similar to that of a known digital signal processor that calculates and outputs a desired output value based on the converted signal, and the calculation result in the signal processing circuit 13 is an analog signal. And a D / A conversion circuit 14 for converting the converted signal into an output amplifier 15 for attenuating the converted signal and outputting the attenuated signal. The signal processing circuit 13 further includes a computing unit DSP including a multiplier, an adder, a register, and a sequence control circuit for operating these in a predetermined procedure according to the processing content, and a control for giving a processing procedure in the computing unit DSP. It is composed of a control data memory CDM for holding data and data used for calculation.

The signal processing circuit 13 performs arithmetic processing according to the control data stored in the control data memory CDM. Through this arithmetic processing, the signal processing circuit 13 can function as a circuit that reproduces the input / output characteristics of an arbitrary element or circuit. That is, if, for example, control data for reproducing a signal output from a circuit such as a diode, a resistor, a transistor, or an operational amplifier when a certain input signal is given to the control data memory CDM, an arbitrary input A desired input / output characteristic can be given to the signal, and an output according to the input / output characteristic can be obtained from the signal processing circuit 13.

Further, on the input side of the circuit cell block 1, there are provided a pair of input terminals 16a and 16b to which the connection lines (force line FL and sense line SL) of the pair of the wiring groups 2 and 3 are respectively connected. The force line FL and the sense line SL connected to this input terminal are connected to each other in the circuit cell block 1 to form a so-called Kelvin contact, which is connected to the input terminal of the input amplifier 11. At the same time, the output side of the circuit cell block 1 has an output terminal 17 to which the output terminal of the output amplifier 15 and one input terminal are connected.
a, 17b are provided, and the output terminals 17a, 1
A force line FL is connected to 17a of 7b, and a sense line SL is connected to the output terminal 17b.

As described above, the sense line SL is provided separately from the force line FL, and the signal of the input terminal of the circuit cell block of the next stage is fed back to the output amplifier 15 of the circuit cell block of the previous stage. Even if contains a parasitic resistance, it is possible to prevent an error from occurring in the input signal of the circuit cell block of the next stage due to the parasitic resistance. That is, if a feedback loop is formed by directly connecting the output terminal and one of the input terminals of the output amplifier 15 in each circuit cell block or via a resistor, the distance to the circuit cell block at the next stage is long and the force line FL is long. If the parasitic resistance is so large that it cannot be ignored, a correct input signal cannot be transmitted to the circuit cell block of the next stage.

On the other hand, when the sense line SL is provided and the signal at the input terminal of the circuit cell block of the next stage is fed back to the output amplifier 15 of the circuit cell block of the previous stage, the output amplifier 15 will be output to the circuit cell block of the next stage. Error occurs due to the parasitic resistance of the force line FL with respect to the input signal of the circuit cell block of the next stage, because it operates so as to match the signal of the other input terminal (the signal from the D / A conversion circuit 14). Will not occur. Signal processing circuit 13
Since a device having the same structure as a known digital signal processor can be used, a detailed description of the structure will be omitted.

FIG. 16 shows the switch matrix (S
The configuration example of the MX) circuit 4 is shown. However, this is just an example. The switch matrix circuit of FIG. 16 has wirings 2a, 2 arranged in directions orthogonal to each other.
.. and 3a, 3b, 3c ... are provided with programmable switch elements capable of selectively setting the presence or absence of connection. On the MOSF
A circuit including an on / off switch 21 made of ET or the like and a storage element 22 for storing connection information thereof, that is, on / off information is used. As the memory element 22, for example, an SRAM cell including a CMOS latch circuit and a transmission gate MOSFET can be used.

In FIG. 16, reference numerals 23 and 24 respectively supply the selection signal and the write data signal to the storage element 22 to turn desired data (for example, the corresponding switch 21 into the ON state) to the storage element 22. This is a signal line for setting data "1" and "0" when it is desired to turn it off. One end of each of these signal lines 23 and 24 has X decoder circuits X-DEC and Y shown in FIG. It is connected to the decoder & write circuit Y-DEC & WDR.

As shown in FIG. 14, an X-decoder circuit X-DEC and a Y-decoder & write circuit for writing connection information to the programmable switch elements 22 constituting the switch matrix circuit 4 and the crosspoint switch circuit 5 are provided. The Y-DEC & WDR is provided around the LSI chip, and the signal line 23 as a word line from the X decoder circuit X-DEC and the signal line 2 as a data line from the Y decoder & write circuit Y-DEC & WDR are provided.
4 is extended in the analog variable function part APFB and connected to the internal storage element 22.

The cross-point switch circuits 5 and 6 can have substantially the same structure as the switch matrix circuit 4. Further, as a programmable switching element forming the switch matrix circuit 4 and the cross point switch circuits 5 and 6, a fuse can be used instead of the circuit including the MOSFET 21 and the storage element 22 provided between the wirings. Further, as the storage element 22, a non-volatile storage element can be used instead of the SRAM cell.

FIG. 17 shows the F constituting the variable tester of FIG.
An example of PGA is shown. The FPGA of this embodiment is an FPGA using a variable logic cell with a delay element disclosed in Japanese Patent Application Laid-Open No. 10-194633 filed by the present inventors. When a logic circuit having a desired logic function is configured using a conventional general FPGA, the signal delay time varies depending on the positional relationship of the variable logic circuit used. On the other hand, in the tester, the timing of the generated signal is important, but currently available FPGA
At the operating frequency of 1, it may be impossible to generate a signal that changes at the timing of the minimum resolution, such as 0.1 ns, required for the device under test. In such a case, if an FPGA using a variable logic cell with a delay element shown in FIG. 17 is used, a signal with such a delicate timing can be generated.

The FPGA shown in FIG. 17 is between the logic cells LC11, LC12, ... LC43 and the logic cells LC11, LC12 ,. Orthogonal wiring groups Lx1, Lx2, ... Lx4 and L
y1, Ly2, ... Ly4 are connected to arbitrary wirings in these orthogonal wiring groups, or to arbitrary input / output terminals of the logic cell and arbitrary wirings in the inter-cell wiring group. Switch matrix S as variable wiring means
SM43 and variable delay circuits DLY11, DLY12, ... Provided corresponding to the logic cells LC11, LC12 ,.
... DLY43 and these variable delay circuits DLY11 and D
LY12, ... Delay provided with a register REG that can externally set data for determining the delay amount in DLY43, and a DA converter DAC that DA-converts control data of the register to form a control signal of the variable delay circuit. Control signal generation circuit CNT and the above register REG
The variable delay circuit D converts the signal obtained by DA converting the control data of
LY11, DLY12, ... DLY43, and signal lines 11, 12, 13, ...

The register REG for setting the control data of the delay time is the variable delay circuits DLY11, D.
LY12, ... May be provided in a one-to-one relationship with DLY43, or may be provided as a common register for a predetermined number of variable delay circuits, and control data for a desired variable delay circuit may be provided by a separately provided selector. Signal (or voltage) obtained by DA conversion of
It may be configured to supply via 1, 1, 2, 13.

Although not shown, data is stored in the memory cells in the logic cell LC and the switch matrix SM around the area where the logic cell LC, the switch matrix SM and the variable delay circuit DLY are arranged in a matrix. Peripheral circuits including an address decoder for writing, a write circuit, and a buffer circuit for supplying data input from outside the chip to these circuits are provided.

The logic cell LC has ADN, OR,
A circuit including a logic configuration element such as MOSFET that realizes a plurality of logic functions such as NAND, NOR, EOR, and NOT, and a logic storage element that stores information for specifying a logic function to be realized in the logic cell. With regard to the circuit having such a function, various configurations have been conventionally proposed, and any configuration may be used in the present embodiment. On the other hand, as the switch matrix SM, a circuit having a configuration similar to that of the switch matrix of the analog FPGA as shown in FIG. 16 can be used.

The variable delay circuit D shown in FIGS.
Specific circuit examples of LY11, DLY12, ... DLY43 are shown. Among them, the variable delay circuit DLY of the embodiment of FIG. 18 is composed of an operational amplifier AMP whose non-inverting input terminal is connected to a constant voltage such as Vcc / 2, and a variable capacitance element VC which is connected to its inverting input terminal. The capacitance value of the variable capacitance element VC is controlled by the control signal Vs from the delay control signal generation circuit CNT so that a circuit having a desired delay time is set. Variable capacitance element VC of this embodiment
Since the control signal Vs for controlling the control signal is an analog signal, a DA conversion circuit for converting the set control data into an analog signal is provided at the next stage of the register in the delay control signal generation circuit CNT.

The variable delay circuit DLY shown in FIG. 19 has a plurality of inverters IN connected in cascade.
V1 to INVn and input nodes n1 to n of each inverter
Variable capacitance elements vc1 to vcn respectively connected between n
The capacitance values of the variable capacitance elements vc1 to vcn are controlled by the control data vs, and the delay time between the inverters can be set. Further, the number of inverters can be controlled in advance by cutting or short-circuiting the wiring. The delay amount per set composed of each inverter and the variable capacitance element is equivalent,
By setting the number of inverters to n, a delay time equal to the sum of delay times passing through each inverter can be obtained.

In the case of the variable delay circuit configured as an analog circuit as in the embodiment of FIG. 18, when the signal Vin which changes from the low level to the high level as shown in FIG. 20A is input to this variable delay circuit. The slope of the potential Vin ′ of the input terminal of the operational amplifier AMP changes according to the capacitance value of the variable capacitance VC as shown in FIG. As a result, the delay time tdp of the output of the operational amplifier AMP changes as shown in FIG.

In the case of the variable delay circuit configured as a digital circuit as in the embodiment of FIG. 19, when the signal Vin which changes from the low level to the high level as shown in FIG. 20 (a) is input to this variable delay circuit. Since the switch MOSFET in the ON state differs depending on the control data, the number of inverters through which the input signal passes changes. as a result,
The change timing of the output signal Vout of this delay circuit is
It changes like FIG.20 (c). This allows the timing of the generated signal to be adjusted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above-described embodiment, a case has been described as an example where a tester for performing a scan path test (structural test) by the FPGA in the variable tester and a BIST test is constructed, but the logic I having no scan path or BIST is described.
The present invention can also be applied to the case where a tester for testing C, that is, a tester for sequentially inputting test patterns from the external terminals of the device under test to construct a test on the FPGA.

[0100]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, a tester capable of executing a test by a test program written in an arbitrary tester language can be built in the FPGA by using the test circuit construction data written in HDL. By performing the test of the semiconductor device to be tested, the test can be performed without using a commercially available large-scale tester. Moreover, by changing the tester built in the FPGA for each type of test, there is no need to introduce a new tester or to convert the test program, and the cost required for the test can be greatly reduced. .

[Brief description of drawings]

FIG. 1 is a perspective view showing a schematic configuration of an embodiment of a variable tester according to the present invention.

FIG. 2 is a block diagram showing a more detailed configuration example of the tester main body of the embodiment of FIG. 1 that enables an arbitrary test circuit to be configured using FPGA.

FIG. 3 is a block diagram showing a functional configuration of a general tester.

FIG. 4 is a block diagram showing an example of types and ratios of interface boards of the variable tester according to the present invention.

FIG. 5 is a block diagram showing a configuration example of a test circuit (ALPG) that generates a test pattern for inspecting a medium speed pin (full function pin) according to a predetermined algorithm.

FIG. 6 is a logical configuration diagram showing a specific example of a driver & comparator circuit of the test circuit of FIG.

7 is a timing chart showing signal timing in the driver & comparator circuit of FIG.

FIG. 8 is a block diagram showing a configuration example of a test circuit (ALPG) that generates a test pattern for inspecting a low speed pin (reduce pin) according to a predetermined algorithm.

9 is a logical configuration diagram showing a specific example of a driver & comparator circuit of the test circuit of FIG.

FIG. 10 is a block diagram showing a configuration example of a test circuit (ALPG) that generates a clock to be input to a high speed pin (clock pin) according to a predetermined algorithm.

11 is a logical configuration diagram showing a specific example of a driver circuit of the test circuit of FIG.

FIG. 12 is a flowchart showing an example of a test procedure by the variable tester of the present invention.

FIG. 13 is a block diagram showing a configuration example of an analog test circuit for testing an analog input / output pin of a device under test.

FIG. 14 is an analog FP forming the variable tester of the present invention.
It is a block diagram which shows the structural example of GA.

FIG. 15 is a block diagram showing an example of a circuit cell block forming an analog FPGA.

FIG. 16 is a circuit configuration diagram showing an example of a switch matrix circuit forming an analog FPGA.

FIG. 17 is a block diagram showing a specific configuration example of an FPGA that constitutes a variable tester.

18 is a circuit diagram showing a specific example of a variable delay circuit that constitutes the FPGA of FIG.

FIG. 19 is a circuit diagram showing another configuration example of the variable delay circuit.

20 is a timing chart showing the relationship between the input / output signal timing and the delay time in the variable delay circuit of FIG.

FIG. 21 is a display configuration diagram showing a display example of a display screen in a function entry tool that can be used to generate tester (ALPG) construction data.

22 is an ALPG on the display screen of FIG. 21.
It is a display block diagram which shows the further detailed content of FIG.

23 is a display configuration diagram showing detailed contents of the sequence control circuit module on the display screen of the ALPG of FIG.

24 is a display configuration diagram showing detailed contents of an instruction memory circuit module on the display screen of the ALPG of FIG.

FIG. 25 is a display configuration diagram showing detailed contents of a test pattern calculation module on the display screen of the ALPG of FIG. 22.

FIG. 26 is a diagram showing an HDL description sentence regarding a sequence control circuit generated by a function entry tool.

FIG. 27 is a diagram showing an HDL description sentence regarding an instruction memory circuit generated by a function entry tool.

FIG. 28 is a diagram showing an HDL description sentence regarding an address operation circuit generated by a function entry tool.

FIG. 29 is a diagram showing an HDL description sentence regarding a data operation circuit generated by a function entry tool.

[Explanation of symbols]

100 tester body 110 system configuration board 120 power board 130 FPGA 140 pattern generator 150 timing generator 160 controller (CPU) 200 test stations 210 interface board 220 driver circuit 230 comparator circuit 240 Driver & comparator circuit 260 I / O switching circuit 410 ALPG control circuit 500 computer (workstation) DUT device under test

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 11/22 330 G01R 31/28 H // G06F 17/50 656 A (72) Inventor Hiroki Wakamatsu Tokyo 5-22-1 Kamimizuhoncho, Kodaira-shi F-term in Hitachi Super L.S.I Systems Co., Ltd. (reference) 2G132 AA01 AB01 AC03 AC14 AD06 AE16 AE18 AE22 AE23 AE27 AG02 AG08 AH01 AK23 AK29 AL09 5B046 AA08 BA03 5B048 AA01 AA19 BB00 DD05 DD08 FF03

Claims (10)

[Claims] 1. A test apparatus configured to be changeable into a plurality of test apparatuses different from each other is used, and any one test apparatus is selected from the changeable test apparatuses, and the selected apparatus is selected. A test method characterized in that an inspection target is tested by using the test object. 2. One of the plurality of test devices is a logic test device capable of effectively checking a logic function including combinational logic, and another one of the plurality of test devices is a memory. 2. The test method according to claim 1, which is a memory test device capable of effectively inspecting a circuit. 3. The test method according to claim 2, wherein the plurality of test devices include an analog test device capable of effectively testing an analog circuit. 4. The test according to claim 2, wherein the logic test device is a structural test device that transmits / receives data to / from a test circuit provided on the inspection target. Method. 5. A plurality of variable logic integrated circuits capable of forming an arbitrary logic, a control circuit, a power supply circuit for generating a power supply voltage supplied to an inspection target, and the plurality of variable logic integrated circuits. A test apparatus comprising: a signal input / output unit for inputting a signal generated by a test circuit to the inspection target and supplying a signal output from the inspection target to the test circuit. 6. The test apparatus according to claim 5, further comprising a variable analog integrated circuit capable of configuring an arbitrary analog circuit. 7. The signal input / output means includes a first signal input / output means corresponding to the input / output signal of the first frequency to be inspected and an input of a second frequency higher than the first frequency. Second signal input / output means corresponding to the output signal, and the second
6. The test apparatus according to claim 5, comprising a third signal input / output unit corresponding to an input / output signal of a third frequency higher than the frequency of. 8. The number of the second signal input / output means is larger than that of the first signal input / output means, and the number of the third signal input / output means is larger than that of the second signal input / output means. The test device according to claim 7, wherein the test device is more than a number. 9. The variable logic integrated circuit includes a plurality of variable logic circuits and variable wiring means capable of arbitrarily connecting the variable logic circuits, and the variable logic circuit adjusts a signal transmission delay time. 9. The test apparatus according to claim 5, further comprising a variable delay element. 10. A plurality of variable logic integrated circuits capable of forming an arbitrary logic, a power supply circuit for generating a power supply voltage supplied to an inspection target, and a test circuit composed of the plurality of variable logic integrated circuits. A method for constructing a test circuit in an apparatus comprising a signal input / output unit for inputting the generated signal to the inspection target and supplying the signal output from the inspection target to the test circuit, which is described in a tester language. The test program relating to the semiconductor device to be inspected is analyzed, the test pattern generation algorithm is extracted, the configuration of the test circuit is determined based on the algorithm, and the hardware description language is determined based on the determined configuration. A test device that generates description data of a test circuit and has a desired test function for the device based on the description data Method for constructing a test apparatus which is characterized in that so as to build.