JP2010078536A - Pin connection calculation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To calculate a proper connection plan between a DUT pin and an ATE pin by ascertaining accurately whether a connection target of the DUT pin is a high-speed ATE pin or a low-speed ATE pin. <P>SOLUTION: The pin connection calculation device includes a speed determination part 17 for determining whether or not a waveform of a test signal input into the DUT pin or an output signal output from the DUT pin is changed at higher speed than prescribed reference speed, relative to each DUT pin carried by a test object; and a pin allocation part 18 for allocating the high-speed ATE pin capable of handling a signal whose waveform is changed at higher speed than the prescribed reference speed to a DUT pin determined that the waveform of the test signal or the output signal is changed at higher speed than the prescribed reference speed, and allocating the low-speed ATE pin capable of handling only a signal whose waveform is changed at lower speed than the prescribed reference speed to a DUT pin determined that the waveform of the test signal or the output signal is not changed at higher speed than the prescribed reference speed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pin connection calculation device for calculating a pin connection plan between a semiconductor test apparatus in which a high-speed ATE pin capable of outputting a high-speed signal and a low-speed ATE pin corresponding to a low-speed signal are mixed, and an object to be tested.

  A semiconductor test apparatus gives a test signal to an object to be tested such as an IC or an LSI, and determines pass / fail of the object to be tested based on an output signal output from the object to be tested. These test signals and output signals are transmitted on the wiring connecting the plurality of ATE pins on the semiconductor test apparatus side and the plurality of DUT pins on the test target side.

  Also, the semiconductor test equipment has a “symmetrical structure” model in which all ATE pins have the same driver function and comparator function, and “asymmetric” in which all ATE pins have the same driver function and comparator function. "Structure" models. Since the semiconductor test apparatus having a symmetrical structure has the same specifications for all ATE pins, the ATE pin can be arbitrarily selected as a connection destination of each DUT pin.

On the other hand, in order to reduce costs, an asymmetric semiconductor test apparatus has a high-speed ATE pin that can output a signal that changes at a high speed and a low-speed ATE pin that outputs only a signal that changes at a low speed. Yes. By connecting the high-speed ATE pin to the DUT pin to which a signal changing at high speed is input / output, and connecting the low-speed ATE pin to the DUT pin to which a signal changing at low speed is input / output, A test can be performed at low cost (for example, refer patent documents 1 and 2).
JP 2006-71288 A JP 2007-10396 A

  However, in a semiconductor test apparatus having an asymmetric structure, if the ATE pin and the DUT pin cannot be properly connected, the test of the test object cannot be performed. For example, if a low-speed ATE pin is connected to a DUT pin to which a high-speed signal is input, the semiconductor test apparatus cannot input an accurate signal to the DUT pin. The number of high speed ATE pins is limited, and all DUT pins cannot be connected to the high speed ATE pins. In addition, an increase in the number of high-speed ATE pins causes an increase in the cost of a semiconductor test apparatus having an asymmetric structure, and it becomes impossible to perform a test on a test object at a low cost.

  Conventionally, an engineer has proposed a connection plan between an ATE pin and a DUT pin based on the specification of the DUT pin. For example, an engineer assigns a high-speed ATE pin if the DUT pin is a data pin or an address pin, and assigns a low-speed ATE pin if the DUT pin is a control pin based on his own experience.

  However, since the specification of the DUT pin does not always correspond exactly to the change rate of the actual test waveform input to the DUT pin, the connection destination of the DUT pin is determined based on the experience of the engineer as the high-speed ATE. It is not possible to accurately determine whether to use a pin or a low-speed ATE pin. Therefore, it is not always appropriate to determine the type of ATE pin to be connected based only on the specification of the DUT pin.

  The present invention has been made in view of the above problems, and its purpose is to accurately determine whether the connection destination of the DUT pin is a high-speed ATE pin or a low-speed ATE pin. To provide a pin connection calculation device for calculating an appropriate connection plan.

  A first feature of the present invention is a pin connection calculation device that calculates a connection relationship between a plurality of ATE pins included in a semiconductor test apparatus that determines pass / fail of a test target and a plurality of DUT pins included in the test target. A speed determining unit that determines whether the waveform of the test signal input to the DUT pin or the output signal output from the DUT pin changes at a speed faster than a predetermined reference speed for each DUT pin; When the waveform of the test signal or output signal changes at a speed faster than a predetermined reference speed, it is possible to handle a signal whose waveform changes at a speed faster than the predetermined reference speed for the DUT pin determined by the speed determination unit. A high-speed ATE pin is assigned to the DUT pin that is determined by the speed determination unit to determine that the waveform of the test signal or the output signal does not change at a speed faster than a predetermined reference speed. It is to comprise a pin assignment unit handling only signal that changes the waveform at a constant reference speed following slower speed allocates slow ATE pins as possible.

  According to the first feature, a high-speed ATE pin is assigned to a DUT pin that is determined to have a test signal or output signal waveform that changes at a speed faster than a predetermined reference speed, and the test signal or output signal waveform is predetermined. By assigning a low speed ATE pin to a DUT pin that is determined not to change at a speed higher than the reference speed, it is possible to accurately determine whether the connection destination of the DUT pin is a high speed ATE pin or a low speed ATE pin Therefore, the pin connection calculation device can calculate an appropriate connection plan between the DUT pin and the ATE pin.

  A second feature of the present invention is a pin connection calculation device that calculates a connection relationship between a plurality of ATE pins included in a semiconductor test apparatus that determines pass / fail of a test target and a plurality of DUT pins included in the test target. For each DUT pin, the apparatus determines whether the waveform change of the test signal input to the DUT pin satisfies a predetermined regularity, and the waveform change of the test signal has a predetermined regularity. And a pin connection plan calculation unit that calculates a connection plan for connecting the ATE pin to a plurality of DUT pins determined by the regularity determination unit as being satisfied via a predetermined external circuit.

  According to the second feature, there is provided a connection plan for connecting the ATE pin via a predetermined external circuit to a plurality of DUT pins determined that the waveform change of the test signal satisfies the predetermined regularity. By calculating, even when the number of ATE pins is smaller than the number of DUT pins, or when a plurality of test objects are simultaneously performed, the number of ATE pins is not insufficient. An appropriate connection plan between the pin and the ATE pin can be calculated.

  According to the pin connection calculation apparatus according to the present invention, it is possible to accurately determine whether the connection destination of the DUT pin is the high-speed ATE pin or the low-speed ATE pin, and to calculate an appropriate connection plan between the DUT pin and the ATE pin. it can.

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same portions are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
With reference to FIG. 1, the structure of the pin connection calculation apparatus concerning the 1st Embodiment of this invention is demonstrated. The pin connection calculation apparatus according to the first embodiment of the present invention is a connection between a plurality of ATE pins included in a semiconductor test apparatus for determining pass / fail of an object under test such as an IC or LSI and a plurality of DUT pins included in the object under test. An apparatus for calculating a relationship, a processing operation unit 11 having functional means for executing a series of connection plan calculation work, and data for storing data necessary for the connection plan calculation work and calculated connection plan information The storage unit 12 includes at least a program storage unit 13 that stores a connection plan calculation program. The processing operation unit 11 constitutes a part of a central processing unit (CPU) of a normal computer system. The data storage unit 12 and the program storage unit 13 may be configured by a main storage device inside the CPU, or may be configured by a semiconductor memory such as a semiconductor ROM or a semiconductor RAM connected to the CPU, or a storage device such as a magnetic disk device. May be.

  The processing calculation unit 11 determines, for each DUT pin, whether or not the waveform of the test signal input to the DUT pin or the output signal output from the DUT pin changes at a speed faster than a predetermined reference speed. When the waveform of the unit 17 and the test signal or output signal changes at a speed faster than a predetermined reference speed, the waveform changes at a speed faster than the predetermined reference speed with respect to the DUT pin determined by the speed determination section 17. A high-speed ATE pin capable of handling a signal is allocated, and a predetermined reference speed is set for the DUT pin determined by the speed determination unit 17 that the waveform of the test signal or the output signal does not change at a speed higher than the predetermined reference speed. And a pin assignment unit 18 for assigning a low-speed ATE pin capable of handling only a signal whose waveform changes at a low speed as described below. The speed determination unit 17 and the pin assignment unit 18 may be configured by dedicated hardware, respectively, and each is configured as a functional means having a substantially equivalent function by software using a CPU of a normal computer system. Also good.

  The speed determination unit 17 is faster than a predetermined reference speed when the test rate calculation unit 19 that calculates a high-speed test rate and the change interval of the waveform of the test signal or the output signal is twice or more the high-speed test rate width. And a pin speed determination unit 20 that determines that the test signal or the output signal waveform changes at a speed faster than a predetermined reference speed when the change interval of the waveform of the test signal or the output signal is less than twice the high-speed test rate width. Prepare.

  The test rate calculation unit 19 detects a clock cycle as an example of a high-speed test rate. For example, when a simulation waveform of a test target is converted into a waveform (test pattern) of a test signal input to the test target by a semiconductor test apparatus, a test pattern that is continuous on the time axis is displayed at each test rate. It is divided into. At this time, the test rate calculation unit 19 detects the clock cycle as an example of the high-speed test rate.

  The pin speed determination unit 20 will be described later with reference to FIG.

  Further, the pin connection calculation device includes an input device 16 for inputting information necessary for connection plan calculation work, an output device 15 for outputting the created connection plan, and the like. And an input / output control unit 14 for controlling data transmission / reception with the unit 11.

  FIG. 2 shows a connection example between the ATE pin of the semiconductor test apparatus 31 and the DUT pin of the device under test (LSI) 32. The semiconductor test apparatus 31 includes a plurality of (here, L) ATE pins ATE_p1 to ATE_pL. The test object 32 includes a plurality (N in this case) of DUT pins DUT_p1 to DUT_pN.

  As described above, the ATE pin can handle only a high-speed ATE pin capable of handling a signal whose waveform changes at a speed higher than a predetermined reference speed, and a signal whose waveform changes at a speed lower than a predetermined reference speed. And a low-speed ATE pin capable of In other words, the semiconductor test apparatus 31 is an “asymmetric structure” semiconductor test apparatus that does not have a driver function and a comparator function in which all ATE pins are equal.

In the first embodiment, there is a one-to-one connection between the ATE pin and the DUT pin.
The wiring connecting the pins and the DUT pins is formed on the interface guard 33 such as a printed board or a circuit board. Therefore, the pin connection calculation device can design the wiring on the interface guard 33 by calculating the connection relationship between the plurality of ATE pins and the plurality of DUT pins. For example, the connection relationship between a plurality of ATE pins and a plurality of DUT pins is stored in the data storage unit 12 in FIG. 1 and transferred to an external printed circuit board CAD tool, which is useful for designing a printed circuit board that connects the ATE pins and the DUT pins. Can do.

  FIG. 3A shows an example of a waveform of a test signal that changes at a low speed with respect to a predetermined reference speed, and FIG. 3B shows a waveform of a test signal that changes at a high speed with respect to a predetermined reference speed. An example is shown and FIG.3 (c) shows the waveform of a clock signal.

  The pin speed determination unit 20 sets each cycle of the clock signal in FIG. 3C calculated by the test rate calculation unit 19 as a predetermined reference speed to each of the test signals shown in FIG. 3A and FIG. It is determined whether or not the signal changes in waveform at a speed faster than a predetermined reference speed. For example, since the change interval of the waveform of the test signal shown in FIG. 3A is twice or more the high-speed test rate (clock cycle) width, the pin speed determination unit 20 changes at a speed faster than a predetermined reference speed. Judge not to. On the other hand, since the change interval of the waveform of the test signal shown in FIG. 3B is less than twice the high-speed test rate (clock cycle) width, the pin speed determination unit 20 changes at a speed faster than a predetermined reference speed. Judge that.

  The pin assignment unit 18 in FIG. 1 assigns and connects a high-speed ATE pin to a DUT pin to which a test signal determined by the speed determination unit 17 is input when the waveform changes at a speed faster than a predetermined reference speed. A draft is prepared, and a low-speed ATE pin is assigned to a DUT pin to which a test signal determined by the speed determination unit 17 is input if the waveform does not change at a speed faster than a predetermined reference speed. In this way, the pin connection calculation device connects the high-speed ATE pin to the DUT pin to which the test signal whose waveform changes at high speed is input, and connects the DUT pin to which the test signal whose waveform changes at low speed is input. On the other hand, a connection plan for connecting the low-speed ATE pin can be created.

  In general, there are a plurality of types of tests performed by a semiconductor test apparatus on one test target, and the waveform of a test signal input to one DUT pin is different for each type of test. Therefore, it is desirable to determine whether each DUT pin is connected to the high-speed ATE pin or the low-speed ATE pin in consideration of the change speed of the waveform of the test signal in the plurality of tests.

  Next, an example of a pin connection calculation method using the pin connection calculation apparatus shown in FIG. 1 will be described with reference to FIG.

(A) First, in step S01, n = 1 is initially set as a variable n for specifying the DUT pin DUT_pn. Proceeding to step S03, m = 1 is initially set as a variable m for specifying a test TESTm to be executed by the semiconductor test apparatus 31 for a specific object under test 32. Here, a case where a total of M tests TEST1 to TESTM are performed on a specific object under test 32 will be described.

(B) Proceeding to step S05, the test rate calculator 19 detects a clock cycle as an example of a high-speed test rate in the test TEST1. Proceeding to step S07, the pin speed determination unit 20 determines whether or not the change interval of the waveform of the test signal input to the DUT pin DUT_p1 in the test TEST1 is twice or more the high-speed test rate (clock cycle) width. . If it is more than twice the clock cycle width (YES in S07), it is determined that the test signal is a signal whose waveform does not change at a speed faster than a predetermined reference speed, and the process proceeds to step S09, where the pin assignment unit 18 , A low-speed ATE pin is set as an allocation candidate for the DUT pin DUT_p1. Then, it progresses to S13 stage.

  (C) On the other hand, if it is not more than twice the clock cycle width (NO in S07), it is determined that the test signal is a signal whose waveform changes at a speed faster than a predetermined reference speed, and the process proceeds to step S11. The allocation unit 18 sets the high-speed ATE pin as an allocation candidate for the DUT pin DUT_p1. Then, it progresses to S13 stage.

  (D) In step S13, it is determined whether m = M. If m = M is not satisfied (NO in S13), the process proceeds to step S15, m is incremented by 1 and the process returns to step S05, and for all remaining tests TEST2 to TESTm to be performed on a specific test object, S05 is performed. Steps S11 are repeated. If m = M (YES in S13), the processing operation unit 11 proceeds to step S17, and in all the tests TEST1 to TESTm, the processing operation unit 11 determines whether or not the high-speed ATE pin is an allocation candidate for the DUT pin DUT_p1. to decide.

  (E) When the high-speed ATE pin is selected as an allocation candidate in all the tests TEST1 to TESTm (YES in S17), the process proceeds to step S21, and the high-speed ATE pin is not selected as an allocation candidate in all the tests TEST1 to TESTm ( (NO in S17) Proceed to step S19.

  (F) In step S19, the processing operation unit 11 determines whether or not the number of tests TEST that use the high-speed ATE pin as an allocation candidate for the DUT pin DUT_p1 is larger than a predetermined threshold value. When the number of tests TEST is greater than the predetermined threshold (YES in S19), the process proceeds to step S21, and the pin assignment unit 18 determines to assign a high-speed ATE pin to the DUT pin DUT_p1. Thereafter, the process proceeds to step S25.

  (G) On the other hand, if the number of tests TEST is equal to or less than the predetermined threshold (NO in S19), the process proceeds to step S23, and the pin allocation unit 18 determines to allocate the low-speed ATE pin to the DUT pin DUT_p1. To do. Thereafter, the process proceeds to step S25.

  (H) In step S25, it is determined whether n = N. If n = N is not satisfied (NO in S25), the process proceeds to step S27, n is incremented by 1 and the process returns to step S03, and for all remaining DUT pins DUT_p2 to DUT_pN possessed by the specific DUT, step S03 Step S23 is repeatedly performed to determine whether to assign either a high-speed ATE pin or a low-speed ATE pin. If n = N (YES in S25), the flowchart of FIG. 4 ends.

  The above-described pin connection calculation method can be expressed as a series of processes or operations connected in time series, that is, a “procedure”. Therefore, this pin connection calculation method can be configured as a computer program (connection plan calculation program) for specifying a plurality of functions performed by a processor or the like in a computer system in order to execute the method using a computer system. The computer program can be stored in a computer-readable recording medium. It is possible to realize the above-described pin connection calculation method by reading this recording medium by a computer system and executing the program to control the computer. Here, the recording medium includes a memory device, a magnetic disk device, an optical disk device, and other devices capable of recording a program. The connection plan calculation program read into the computer system is stored in the program storage unit 13.

As described above, according to the first embodiment of the present invention, the high-speed ATE pin is connected to the DUT pins DUT_p1 to DUT_pN in which the waveform of the test signal is determined to change at a speed faster than a predetermined reference speed. By assigning the low-speed ATE pin to the DUT pins DUT_p1 to DUT_pN that are determined that the waveform of the test signal does not change at a speed faster than a predetermined reference speed, D
Since it is possible to accurately determine whether the connection destination of the UT pins DUT_p1 to DUT_pN is the high speed ATE pin or the low speed ATE pin, the pin connection calculation device can calculate an appropriate connection plan between the DUT pin and the ATE pin. .

  Further, based on the calculated connection plan between the DUT pin and the ATE pin, it is possible to calculate a proportional relationship between the change interval of the waveform changing at a low speed and the high-speed test rate from the simulation waveform to be tested. A test pattern for a semiconductor test apparatus in which low-speed ATE pins are mixed can be converted.

In the first embodiment, the case where the test signal is input from the ATE pin to the DUT pin has been described as an example, but the present invention is not limited to this. On the contrary, even when an output signal is output from the DUT pin to be tested to the ATE pin for this test signal, the same analysis processing is performed on the waveform of the output signal, and the type of ATE pin to be connected Can be judged.
(Second Embodiment)
When the number of ATE pins is smaller than the number of DUT pins, or when testing a plurality of test objects at the same time, the number of ATE pins is insufficient, and one ATE pin is provided for all DUT pins. Cannot connect one-on-one. Increasing the number of ATE pins provided in the semiconductor test apparatus increases the cost of the apparatus.

  The DUT pin includes a large number of bus pins such as an address bus pin. In many cases, the test signals input to these Bus pins satisfy common regularity. For example, the address Bus pin generally changes in ascending order of 0, 1, 2,. In particular, a test target composed of a system-on-chip (SoC) often has a plurality of bus pins that satisfy such a common regularity.

  Therefore, in the second embodiment, a pin connection calculation device that calculates a connection plan for connecting an ATE pin to a plurality of DUT pins satisfying a predetermined regularity via a predetermined external circuit will be described. To do.

  With reference to FIG. 5, the structure of the pin connection calculation apparatus concerning the 2nd Embodiment of this invention is demonstrated. The pin connection calculation apparatus according to the second embodiment of the present invention is a connection between a plurality of ATE pins included in a semiconductor test apparatus for determining pass / fail of an object to be tested such as an IC or LSI and a plurality of DUT pins included in the object to be tested. A device for calculating a relationship, which includes a processing operation unit 51 having functional means for executing a series of connection plan calculation work, and data for storing data necessary for the connection plan calculation work and calculated connection plan information It comprises at least a storage unit 52 and a program storage unit 53 that stores a connection plan calculation program.

  For each DUT pin, the processing calculation unit 51 includes a regularity determination unit 57 that determines whether the waveform change of the test signal input to the DUT pin satisfies a predetermined regularity, and the waveform change of the test signal is predetermined. A pin connection plan calculation unit 58 that calculates a connection plan for connecting the ATE pin via a predetermined external circuit to a plurality of DUT pins determined by the regularity determination unit 57 to satisfy the regularity of Is provided.

  The input / output control device 54, the output device 55, and the input device 56 are the same as the pin connection calculation device in FIG.

FIG. 6 shows a connection example between the ATE pin of the semiconductor test apparatus 31 and the DUT pin of the device under test (LSI) 32. The semiconductor test apparatus 31 includes a plurality of (here, L) ATE pins ATE_p1 to ATE_pL. The test object 32 includes a plurality (N in this case) of DUT pins DUT_p1 to DUT_.
with pN.

  In the second embodiment, wiring for connecting an ATE pin and a DUT pin and an external circuit 34 are mounted on an interface guard 33b such as a printed board or a circuit board.

The external circuit 34 includes a counter circuit and a shifter circuit formed of an FPGA (Field Programmable Gate Array), receives a control signal such as a clock signal and a reset signal from the ATE pin of the semiconductor test apparatus 31, and has a predetermined regularity to the DUT pin. Transmit a test signal that satisfies

  An example of the predetermined regularity determined by the regularity determination unit 57 of FIG. 5 will be described with reference to FIGS. The signal shown in FIG. 7 (a) is composed of a series (0, 1, 2,...) Of numerical data obtained by adding a constant numerical value (here, 1) to the test signal input to the DUT pin. 1 regularity is satisfied. The signal shown in FIG. 7 (b) consists of a series (5, 4, 3,...) Of numerical data obtained by subtracting a constant numerical value (here, 1) from the test signal input to the DUT pin. The regularity of 2 is satisfied.

  The signal shown in FIG. 7 (c) includes a series (1, 2, 4,...) Of numerical data obtained by multiplying a test signal input to the DUT pin by a constant numerical value (here, 2). 3 regularity is satisfied. The signal shown in FIG. 7 (d) consists of a series (16, 8, 4,...) Of numerical data obtained by dividing the test signal input to the DUT pin by a certain numerical value (here, 2). 4 regularity is satisfied.

  For each DUT pin, the regularity judgment unit 57 determines whether the waveform change of the test signal input to the DUT pin satisfies the first to fourth regularities shown in FIGS. 7 (a) to 7 (d). Determine whether.

  The pin connection plan calculation unit 58 determines that the change in the waveform of the test signal satisfies any of the first to fourth regularities shown in FIGS. 7A to 7D by the regularity determination unit 57. A connection plan for connecting the ATE pin to the plurality of DUT pins via the external circuit 34 shown in FIG. 6 is calculated.

  A test circuit comprising a list of numerical data obtained by adding or subtracting constant numerical values shown in FIGS. 7A and 7B is generated by a counter circuit provided in the external circuit 34. Further, a shifter circuit included in the external circuit 34 generates a test signal composed of a list of numerical data obtained by multiplication or division of constant numerical values shown in FIGS. 7C and 7D. The operation mode of the counter circuit and the shifter circuit can be controlled by a control signal input from the ATE pin.

  Next, an example of a pin connection calculation method using the pin connection calculation apparatus shown in FIG. 5 will be described with reference to FIG. The following description shows the processing operation of the processing calculation unit 51 of FIG.

  (A) First, in step S51, the Bus pin is detected from the DUT pins included in the DUT from the DUT simulation waveform or the test pattern file of the test signal. In step S53, it is determined whether there is an input bus pin among the detected bus pins. If there is no input Bus pin (NO in S53), it is determined that there is no DUT pin that satisfies the predetermined regularity, and the flowchart of FIG. 8 ends.

(B) On the other hand, if there is an input bus pin (YES in S53), the process proceeds to step S55, and r = 1 is initialized as a variable r for specifying the input bus pin. Here, input B
The case where the total number of us pins is R will be continued. Proceeding to step S57, it is determined whether or not the waveform change of the test signal input to the input bus pin Bus_p1 satisfies any of the first to fourth regularities shown in FIGS. 7 (a) to 7 (d). to decide.

  (C) If any of the first to fourth regularities is satisfied (YES in S57), the process proceeds to step S59, and the regularity satisfied by the input Bus pin Bus_p1 is stored in the data storage unit 52 of FIG. Thereafter, the process proceeds to step S61. On the other hand, if none of the first to fourth regularities is satisfied (NO in S57), the process proceeds directly to step S61.

  (D) Proceeding to step S61, it is determined whether r = R. If r = R is not satisfied (NO in S61), the process proceeds to step S63, r is incremented by 1 and the process returns to step S57, and all the remaining input bus pins Bus_p2 to Bus_pR of the specific test target are processed in step S57. Is repeatedly performed to determine whether or not the input Bus pins Bus_p2 to Bus_pR satisfy any of the first to fourth regularities. If r = R (YES in S61), the process proceeds to step S65, and data indicating the relationship between the input bus pin and the regularity satisfied by the input bus pin is output from the output device 55 from the data storage unit 52. Through the above procedure, the flowchart of FIG. 8 ends.

  As described above, according to the second embodiment of the present invention, a predetermined external circuit is provided for a plurality of DUT pins that are determined that the waveform change of the test signal satisfies the predetermined regularity. By calculating a connection plan for connecting the ATE pin via the ATE pin, even when the number of ATE pins is smaller than the number of DUT pins or when a plurality of test objects are simultaneously tested, the ATE pin Therefore, an appropriate connection plan between the DUT pin and the ATE pin can be calculated. As a result, the semiconductor test apparatus can measure a large number of characteristic DUT pins using a small number of ATE pins using the external circuit 34.

  As described above, the present invention has been described in terms of two embodiments and modifications thereof. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. That is, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

It is a block diagram which shows the structure of the pin connection calculation apparatus concerning the 1st Embodiment of this invention. 3 is a schematic diagram showing an example of connection between an ATE pin of a semiconductor test apparatus 31 and a DUT pin of a device under test (LSI) 32. FIG. FIG. 3A shows an example of a waveform of a test signal that changes at a low speed with respect to a predetermined reference speed, and FIG. 3B shows an example of a waveform of a test signal that changes at a high speed with respect to a predetermined reference speed. FIG. 3C shows the waveform of the clock signal. It is a flowchart which shows an example of the pin connection calculation method using the pin connection calculation apparatus shown in FIG. It is a block diagram which shows the structure of the pin connection calculation apparatus concerning the 2nd Embodiment of this invention. 3 is a schematic diagram showing an example of connection between an ATE pin of a semiconductor test apparatus 31 and a DUT pin of a device under test (LSI) 32. FIG. FIGS. 7A to 7D are schematic diagrams illustrating examples of predetermined regularity determined by the regularity determining unit 57 of FIG. It is a flowchart which shows an example of the pin connection calculation method using the pin connection calculation apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 51 ... Processing calculating part 12, 52 ... Data storage part 13, 53 ... Program storage part 14, 54 ... Input / output control part 15, 55 ... Output device 16, 56 ... Input device 17 ... Speed judgment part 18 ... Pin allocation Unit 19 Test rate calculation unit 20 Pin speed determination unit 31 Semiconductor test apparatus 32 Object to be tested (LSI)
33, 33b ... interface guard 34 ... external circuit 57 ... regularity judgment unit 58 ... pin connection plan calculation unit
ATE_p1 ~ ATE_pL ... ATE pin
Bus_p1 ～ Bus_pR… Bus pin
DUT_p1 to DUT_pN ... DUT pin
TEST1 ~ TESTM ... test

Claims (5)

A pin connection calculation device for calculating a connection relationship between a plurality of ATE pins included in a semiconductor test apparatus for determining pass / fail of a test target and a plurality of DUT pins included in the test target,
A speed determination unit that determines whether the waveform of the test signal input to the DUT pin or the output signal output from the DUT pin changes at a speed faster than a predetermined reference speed for each DUT pin;
A signal whose waveform changes at a speed higher than the predetermined reference speed with respect to the DUT pin determined by the speed determination unit when the waveform of the test signal or the output signal changes at a speed higher than a predetermined reference speed. A high-speed ATE pin capable of handling a predetermined reference speed is assigned to the DUT pin determined by the speed determination unit that the waveform of the test signal or the output signal does not change at a speed higher than a predetermined reference speed. And a pin assignment unit that assigns a low-speed ATE pin capable of handling only a signal whose waveform changes at a low speed equal to or lower than the speed. The speed determination unit
A test rate calculator for calculating a high-speed test rate;
When the change interval of the waveform of the test signal or the output signal is more than twice the high-speed test rate width, it is determined that it does not change at a speed faster than a predetermined reference speed, and the waveform of the test signal or the output signal 2. The pin connection according to claim 1, further comprising: a pin speed determination unit that determines that the change interval is less than twice the high-speed test rate width and changes at a speed faster than a predetermined reference speed. Calculation device. A pin connection calculation device for calculating a connection relationship between a plurality of ATE pins included in a semiconductor test apparatus for determining pass / fail of a test target and a plurality of DUT pins included in the test target,
For each DUT pin, a regularity judgment unit for judging whether or not the waveform change of the test signal input to the DUT pin satisfies a predetermined regularity;
A connection plan for connecting the ATE pin via a predetermined external circuit to the plurality of DUT pins determined by the regularity determination unit that the change in waveform of the test signal satisfies the predetermined regularity is calculated. A pin connection calculation device comprising: a pin connection plan calculation unit.   4. The pin connection calculation device according to claim 3, wherein the predetermined regularity includes regularity composed of a series of numerical data obtained by adding or subtracting a constant numerical value to the test signal.   4. The pin connection calculation apparatus according to claim 3, wherein the predetermined regularity includes regularity including a series of numerical data obtained by multiplying or dividing the test signal by a constant numerical value.

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