JP2004280426A - Internal signal tracing device for logic integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively use a trace memory for internal signal tracing, shorten internal signal tracing time and shorten time to analyze trouble by continuously tracing many internal signals in real time. <P>SOLUTION: An internal signal tracing device for a logic integrated circuit is arranged in a logic integrated circuit from which a plurality of internal signal groups and each clock signal corresponding to each group both obtained from a plurality of internal nodes grouped by clock frequency used can be fetched; and is configured to select one group of internal signals from the plurality of internal signal groups, and the clock signal corresponding to the group of internal signals, in response to an internal signal select signal given from without, and output the selected group of internal signals as well as the corresponding clock signal synchronously with the clock signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a logic integrated circuit internal signal trace device for tracing an internal signal of a logic integrated circuit mounted on a circuit board when designing an electric circuit.
[0002]
[Prior art]
When a developed large-scale integrated circuit (hereinafter, referred to as LSI) does not operate as expected at the beginning of design, it is necessary to analyze the operation of the LSI and debug it. If it is a black box, the task is extremely difficult. To cope with this, analysis and debugging have been conventionally performed by various methods.
[0003]
As a conventional technique, there is a method of embedding a logic analyzer for debugging in a programmable logic device as described with reference to FIGS. 5 to 7 (for example, see Patent Document 1). FIG. 5 is a block diagram showing a configuration of a programmable logic development system in which a conventional logic analyzer is embedded. This programmable logic development system is a computer system 153 and an electronic system 154 connected via a cable 152 or the like. It includes a component, a programmable logic device (PLD) 155, and shares one or more electronic connections 156 with other components and elements forming the electronic system 154. The PLD 155 includes a user logic design unit 157 and an embedded logic analyzer 158, and the logic connection 159 transmits a signal from the user logic design unit 157 to the embedded logic analyzer 158. The interface signals 160 from the embedded logic analyzer 158 are connected to corresponding connections 161 in the electronic system 154 using the pins of the PLD 155, and these interface signals are connected to the computer system 153 by cables 152.
[0004]
Computer system 153 transmits commands and other information to and receives information from embedded logic analyzer 158 without interrupting or affecting the functional operation of electronic system 154. Therefore, PLD 155 is configured to perform the functions of both user logic design unit 157 and embedded logic analyzer 158.
[0005]
FIG. 6 is a block diagram showing a configuration of a programmable logic device 155 in which a conventional logic analyzer is embedded. In the figure, the JTAG port 171 is used in association with the control logic 172 and the signal 173 to correspond to the interface signal 160 (see FIG. 5). The control logic 172 provides control signals to the embedded logic analyzer 158 and assists in retrieving data and status from the embedded logic analyzer 158. Note that JTAG is a standard method of a boundary scan test, which is one of the inspection methods of an IC chip, and is a standard proposed by the Joint European Test Action Group and standardized by IEEE. An IC compatible with JTAG has an interface including a circuit compatible with JTAG and a terminal called a TAP (Test Access Port), in addition to a circuit performing an original function, and is used for input / output and control of test data. .
[0006]
FIG. 7 is a block diagram showing a specific configuration of the conventional embedded logic analyzer 158. Logic analyzer 158 includes control state machine 181, trigger register 182, trigger comparator 184, registers 185 and 186, counters 187-189, comparators 190 and 191, and trace memory 192. When logic analyzer 158 is programmed into PLD 155, it receives various input signals from the signals in PLD 155. The user compares the trigger signal 183 with the trigger condition stored in the trigger register 182 and generates a breakpoint signal with the satisfied trigger comparator 184. The signal Run from the control state machine 181 is combined with the signal PDF at the gate 193 to enable the counter 189.
[0007]
Further, as a method of accessing a signal inside an integrated circuit, there is a method of providing a shadow PLD that can be programmed to emulate a PLD to be tested (for example, see Patent Document 2). Here, the shadow PLD has at least as many input / output terminals as are associated with the input / output terminals of the PLD to be tested. Also provided are terminals for connecting both input / output terminals of the PLD to be tested and the shadow PLD to an external circuit that is assumed to operate together with the PLD to be tested. Further, it has a probe connector for connecting each terminal of both PLDs to an external measuring instrument. Thus, by allowing access to the terminals of the shadow PLD, the analysis is greatly simplified, and the probability of finding faults associated with internal nodes is greatly increased.
[0008]
Further, as a conventional technique, a control memory and a logic block unit such as an SRAM, a programmable switch unit, an input / output block unit, and a memory control unit for controlling each unit are provided on a field programmable array (FPGA) chip. A mechanism for reading circuit information from the control memory and memory cells in the logic block to the outside of the FPGA chip and a read mechanism for executing the implemented digital circuit are provided, and both mechanisms are operated independently. (For example, see Patent Document 3). This makes it possible to verify the circuit information without stopping the operation of the device.
[0009]
[Patent Document 1]
JP-A-11-296403 (FIGS. 6, 7, and 9)
[Patent Document 2]
Japanese Patent Application Laid-Open No. 10-91472 [Patent Document 3]
JP-A-8-6809
[Problems to be solved by the invention]
The conventional logic integrated circuit monitor system has the following problems because it is configured as described above.
There is only one type of internal signal clock signal, and it is not possible to select a clock for each internal signal group. Therefore, when tracing internal signals having different clocks, it is necessary to match the clock signal with the fastest (higher frequency) clock signal. Therefore, when tracing an internal signal with a slow clock (low frequency), it is necessary to trace a large number of samples, which causes a shortage of trace memory, reading from trace memory, and display time on a computer system. was there. To avoid this problem, it is necessary to reselect a clock for each internal signal to be traced, recompile the logic integrated circuit, and write data to the device. As a result, timely debugging by tracing the internal signal becomes impossible.
[0011]
Further, in Patent Document 1, an internal signal is output to an external terminal using a JTAG port, but the interface of this JTAG is only a serial port of at most several hundred kHz according to an electrical standard, and at high speed. 1 MHz is the limit. This kind of serial communication has a problem that it is not suitable for an interface for analyzing a large number of internal signals of an FPGA operating at a clock of several tens of MHz in real time.
[0012]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to effectively utilize a trace memory for internal signal tracing and reduce internal signal tracing time, and to continuously chase many internal signals in real time. Accordingly, it is an object of the present invention to obtain an internal signal trace device of a logic integrated circuit which can reduce the time required for analyzing a failure.
[0013]
[Means for Solving the Problems]
The internal signal tracing device for a logic integrated circuit according to the present invention is capable of extracting a plurality of internal signal groups obtained from a plurality of internal nodes arranged in units of clock frequencies to be used and respective clock signals corresponding to each group. A group of internal signals and a clock signal corresponding to the group of internal signals are selected from a plurality of internal signals in response to an internal signal select signal provided from the outside and arranged in the logic integrated circuit. A group of internal signals are synchronized with a corresponding clock signal and output to the outside together with the corresponding clock signal.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a monitor system for a logic integrated circuit to which an internal signal trace device of the logic integrated circuit according to the first to third embodiments of the present invention is applied. Here, an example in which an ASIC (Application Specific Integrated Circuit) which is an application-specific integrated circuit, particularly an FPGA (Field Programmable Gate Array) which is a programmable integrated circuit, is used as a logic integrated circuit for monitoring an internal signal. Although shown, the invention is not necessarily limited thereto.
A target FPGA (logic integrated circuit) 9 to be monitored and other devices 11 are mounted on the circuit board 3. In the target FPGA 9, monitor pins for taking out internal signals are prepared on the circuit board 3 in advance, assuming a failure analysis at a stage prior to the design. Although it may be before an actual trouble occurs, usually after the occurrence of an unexpected trouble, a trace circuit 10 typically having a configuration shown in FIGS. 2 to 4 described later is inserted into the circuit of the target FPGA 9.
[0015]
The schematic operation of the monitor system of the logic integrated circuit is as follows.
Based on a command from the personal computer 1, the target FPGA 9 mounted on the circuit board 3 is controlled by a control signal arriving through the transmission line 4, the microcomputer 6 on the signal storage / control device 2, the control FPGA 8, and the transmission line 5. The internal trace circuit 10 is operated to trace the internal signal of the target FPGA 9. The traced internal signal passes through the transmission line 5 and is once written in the trace memory 7 by the control FPGA 8 on the signal storage / control device 2. Then, based on a command from the personal computer 1, the traced internal signal is read from the trace memory 7, sent to the personal computer 1 through the control FPGA 8, the microcomputer 6, and the transmission line 4 and displayed.
[0016]
Next, details of the trace circuit used on the monitor system of the logic integrated circuit shown in FIG. 1 will be described. FIG. 2 is a block diagram showing a configuration of the internal signal trace device of the logic integrated circuit according to the first embodiment of the present invention.
An internal signal group 17 in which several sets of internal signal groups n1 arranged in units of reference clock frequency are arranged is extracted from internal nodes of candidates to be monitored on the internal circuit 12 of the target FPGA 9. These internal signal groups 17 are applied to a multiplexer 23 in the trace circuit 10. The target FPGA internal circuit 12 is configured to extract a reference clock signal 18 in which several sets of one clock corresponding to the internal signal group n1 from the internal node are extracted. 24. When m1 internal signal select signals 13 are input to the trace circuit 10 from the signal storage / control device 2 of FIG. 1, n1 internal signal groups selected by the multiplexer 23 based on the values are selected by the multiplexer 24. The clock (eg, D-FlipFlop) 22 is output in synchronization with the corresponding clock signal. The clock signal at this time is output as a target FPGA reference clock 15 which is a reference for the operation of the target FPGA 9. Therefore, when the external signal storage / control device 2 receives the data, the data can be reliably transferred by the target FPGA reference clock 15. A monitor output enable signal 16 is provided to the target FPGA 9 to control the output enable of the target FPGA 9 to the tri-state output buffers 20 and 20 ′. When not necessary, the external monitor signal of the target FPGA and the target FPGA reference clock are output. Output is stopped. Note that a reference clock signal is used as the internal signal select signal 13 input from the outside, and the register (D-FlipFlop or the like) 21 uses the internal clock signal in synchronization.
[0017]
As described above, according to the first embodiment, a plurality of internal signal groups obtained from a plurality of internal nodes arranged in units of clock frequencies to be used and a target capable of extracting each clock signal corresponding to each group are obtained. A group of internal signals and a clock signal corresponding to the group of internal signals are selected from a plurality of internal signal groups in response to an internal signal select signal provided from outside and arranged in an FPGA (logic integrated circuit). Since the selected group of internal signals is output to the outside together with the corresponding clock signal in synchronization with the corresponding clock signal, the trace memory can be used even when there are logic integrated circuits operating with a plurality of different clocks. The effect of suppressing the amount and shortening the trace data display time can be obtained so that the internal signal can be sampled efficiently.
[0018]
Embodiment 2 FIG.
FIG. 3 is a block diagram showing a circuit configuration of an internal signal tracing device of a logic integrated circuit according to a second embodiment of the present invention. In the figure, portions corresponding to those in FIG. Omitted.
Here, a frequency multiplier (PLL) 25 is provided in the trace circuit 10 or in the target FPGA internal circuit 12 in front of the trace circuit 10 instead of the multiplexer 24 in FIG. In the second embodiment, the internal signal tracing device of the present invention has a configuration including a multiplying circuit 25 provided outside the trace circuit 10.
[0019]
From a candidate node to be monitored on the internal circuit 12 of the target FPGA 9, an internal signal group 17 in which several n1 sets are arranged is given to the multiplexer 23, and a clock signal corresponding to the internal node is a reference clock signal 18. Is multiplied by a multiplying circuit 25. When a clock signal having a frequency higher than the reference clock already exists in the target FPGA internal circuit 12, the clock signal may be directly used without passing through the multiplication circuit 25.
[0020]
In such a circuit arrangement, a clock signal obtained by multiplying the reference clock signal 18 by the multiplier circuit 25 or a clock signal having a higher frequency than the reference clock already existing in the target FPGA internal circuit 12 is used as the internal signal to be monitored. It is assumed that the operation is performed at a speed of an integer r times the reference clock. Then, the internal signal select signal 13 is not fixed while the reference clock signal advances by one, but is switched r times while the reference clock signal advances by one. Therefore, it is possible to trace the n1 internal signals of the number of r channels in a time division manner. Simultaneous traces of internal signals originally connected by n1 lines are immediately expanded to n1 × r lines without increasing the number of external monitor pins of the target FPGA 9. Internal signals can be monitored simultaneously beyond the number of pins limited by the number of pins of a device on which a logic integrated circuit is mounted.
[0021]
As described above, according to the second embodiment, a target FPGA (logic integration) capable of extracting a plurality of internal signal groups and a reference clock signal obtained from a plurality of internal nodes arranged in units of frequency of a clock to be used. Circuit), selects a group of internal signals from a plurality of internal signals in response to an internal signal select signal supplied from outside, and multiplies the reference clock signal to form a group of internal signals. And a group of selected internal signals are output in synchronization with the generated clock signal together with the generated clock signal. The effect that can be traced is obtained.
[0022]
Embodiment 3 FIG.
4 is a block diagram showing a circuit configuration of an internal signal tracing device of a logic integrated circuit according to a third embodiment of the present invention. In the drawing, portions corresponding to those in FIG. Omitted. Here, the multiplication circuit 25 is provided in the target FPGA internal circuit 12 before the trace circuit 10. In the second embodiment, the internal signal tracing device of the present invention has a configuration including a multiplying circuit 25 provided in the target FPGA internal circuit 12 in addition to the trace circuit 10.
[0023]
A clock signal 18 in which several sets of clocks corresponding to n1 internal nodes are arranged is supplied to a multiplexer 24. Among them, r clock signals are generated by multiplying a reference clock signal by a PLL circuit 25. Have been. As a result, n1 × r internal signals can be simultaneously traced. As for other internal signals, corresponding clock signals are directly supplied to the multiplexer 24, and sampling can be performed at the same resolution in units of n1 lines. As a result, the internal signal can be traced at high speed with a small trace memory capacity and a limited number of device pins.
[0024]
As described above, according to the third embodiment, the clock signal is generated by multiplying the reference clock signal, and the generated clock signal is selected as a part of the clock signal corresponding to the group of internal signals. Therefore, there can be obtained an effect that simultaneous tracing of n1 × r internal signals obtained by combining the first and second embodiments and sampling of internal signals of a logic integrated circuit operating with a plurality of clocks can be efficiently performed.
[0025]
【The invention's effect】
As described above, according to the present invention, a plurality of internal signal groups obtained from a plurality of internal nodes arranged in frequency units of clocks to be used and a logic integrated circuit capable of extracting clock signals corresponding to each group can be extracted. And selecting a group of internal signals and a clock signal corresponding to the group of internal signals from the plurality of internal signal groups in response to an internal signal select signal provided from the outside, and selecting the selected group of internal signals. Since the signal is synchronized with the corresponding clock signal and output to the outside together with the corresponding clock signal, all internal signals can be sampled with the same resolution, and the trace memory capacity is small and the internal speed is high. There is an effect that a signal can be traced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a monitor system for a logic integrated circuit according to Embodiments 1 to 3 of the present invention.
FIG. 2 is a block diagram showing a circuit configuration of an internal signal trace device of the logic integrated circuit according to the first embodiment of the present invention;
FIG. 3 is a block diagram showing a circuit configuration of an internal signal trace device of a logic integrated circuit according to a second embodiment of the present invention;
FIG. 4 is a block diagram showing a circuit configuration of an internal signal trace device of a logic integrated circuit according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a conventional programmable logic development system.
FIG. 6 is a block diagram showing a configuration of a programmable logic device in which a conventional logic analyzer is embedded.
FIG. 7 is a block diagram showing a configuration of a conventional embedded logic analyzer.
[Explanation of symbols]
Reference Signs List 1 personal computer, 2 signal accumulation / control device, 3 circuit board, 4, 5 transmission line, 6 microcomputer, 7 trace memory, 8 control FPGA, 9 target FPGA (logic integrated circuit), 10 trace circuit, 12 internal circuit, 13 internal signal select signal, 15 target FPGA reference clock, 16 monitor output enable signal, 17 internal signal group, 18 reference clock signal, 20, 20 'tri-state output buffer, 21, 22 register (D-FlipFlop), 23, 24 multiplexer, 25 multiplier (PLL).

Claims (3)

A plurality of internal signal groups obtained from a plurality of internal nodes grouped in frequency units of clocks to be used and arranged in a logic integrated circuit capable of extracting clock signals corresponding to each group,
Selecting a group of internal signals and a clock signal corresponding to the group of internal signals from the plurality of internal signal groups in response to an internal signal select signal given from the outside;
An internal signal tracing device for a logic integrated circuit, wherein a selected group of internal signals are output to the outside together with the corresponding clock signal in synchronization with the corresponding clock signal. A plurality of internal signal groups obtained from a plurality of internal nodes grouped in frequency units of a clock used and a reference clock signal are arranged in a logic integrated circuit capable of extracting the clock signal,
Selecting a group of internal signals from the plurality of internal signal groups in response to an internal signal select signal given from the outside,
Generating a clock signal corresponding to the group of internal signals by multiplying the reference clock;
An internal signal tracing device for a logic integrated circuit, wherein the selected group of internal signals is output together with the generated clock signal in synchronization with the generated clock signal. 2. The logic integration according to claim 1, wherein a clock signal is generated by multiplying the reference clock signal, and the generated clock signal is selected as a part of a clock signal corresponding to a group of internal signals. Internal signal trace device for the circuit.

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