JP2002196047A - Bist circuit built-in semiconductor integrated circuit device and testing method for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for examining each internal data output test result on a tested circuit having a plurality of internal data outputs by using a small number of external pins. SOLUTION: This device is provided with a BIST circuit 10 testing the tested circuit 20, a plurality of comparison circuits 30 arranged individually in correspondence with a plurality of internal output signals 21 outputted from the tested circuit, and a logic circuit 41 inputting a plurality of determination result signals 40 outputted from the comparison circuits 30 and outputting a single output signal as a result of predetermined logical computing on these signals to a result output terminal 50. When a determination enable signal 31 is active, the comparison circuit 30 compares the internal output signal 21 outputted from the tested circuit 20 with an expected value 11 outputted from the BIST circuit, and then, outputs the logical value determination result signal 40 matching agreement/disagreement. When the determination enable signal is inactive, the comparison circuit 30 outputs a predetermined logical value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit with a built-in BIST.

[0002]

2. Description of the Related Art With the progress of large-scale semiconductor integrated circuits, semiconductor integrated circuit chips have many external terminals.

An L for testing such a semiconductor integrated circuit is
The SI tester has a problem that it is very expensive because of the need to increase the speed and supply signals to many terminals.

Further, there is also a problem that an external terminal for testing a circuit built in the chip is required, and the chip size becomes large.

In order to solve such a problem, a BI
It is effective to incorporate an ST (Build In Self Test) circuit. As is well known, B
The IST circuit performs a self-diagnosis by incorporating a test circuit in the LSI. For example, the IST circuit includes a pattern generator and a test result analyzer. The test pattern generator automatically generates a test pattern and tests the test target circuit. A pattern is given, the response output of the circuit under test is taken into the data compressor, compressed, the code in the signature prepared in advance is compared with the output of the data compressor, and the comparison result is output.

In a semiconductor integrated circuit incorporating this type of BIST circuit, for example, as shown in FIG. 12, BIST circuits 211 and 212 are provided for a plurality of memory blocks 201 and 202 for each memory block. It is configured to output test results.

As another example of a conventional semiconductor integrated circuit having a built-in BIST circuit, as shown in FIG.
The two memory blocks 301 and 302 are tested by the two BIST circuits 311 and 312, two output data from the memory blocks 301 and 302 are input to the exclusive OR circuit 310, and the result is output as the output result 311. An output configuration is also known.

The conventional semiconductor integrated circuit having a built-in BIST circuit shown in FIG. 12 has a problem that the number of pins for outputting the BIST test results increases.

The conventional semiconductor integrated circuit having a built-in BIST circuit shown in FIG. 13 compresses output data of two memory blocks into one output result, so which memory block is defective. Cannot be determined.

Japanese Patent Application Laid-Open No. 2000-215693 discloses that a plurality of input / output circuit units are provided in an input / output circuit unit as a configuration of a synchronous semiconductor memory device in which the number of observation pins during a test can be reduced and output can be performed at a reduced output data rate. A configuration is disclosed in which a coincidence detection circuit for detecting coincidence of data output to a data terminal is provided, and the same result is written to two latches during a test and read alternately in response to a clock signal.

[0011]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing an increase in the number of pins for observing test results and specifying a block defect, and a test method therefor. It is to provide.

[0012]

SUMMARY OF THE INVENTION The present invention, which provides a means for solving the above-mentioned problems, comprises a BIST (Built In Self Test) circuit for testing a circuit under test.
In a semiconductor integrated circuit device with a built-in ST circuit, when an input judgment enable signal is in an active state, an internal output signal output from the circuit under test is compared with an expected value output from the BIST circuit, A comparison circuit that outputs a determination result signal of a logical value corresponding to the mismatch and outputs a predetermined logical value when the determination enable signal is in an inactive state, includes a plurality of comparators output from the circuit under test. A logic circuit including a plurality of internal output signals corresponding to each of the plurality of internal output signals, receiving a plurality of determination result signals output from the plurality of comparison circuits, and outputting one output signal which is a predetermined logical operation result of these signals And the output of the logic circuit is output from the result output terminal to the outside of the device.

According to the method of the present invention, a clock for executing a test is input to the BIST circuit from an automatic test device (ATE) such as an LSI tester, and a judgment result from the result output pin is passed to the non-defective product on the automatic test device. In comparison with the expected value, in the case of a failure, a failure log for the corresponding clock is generated, and only one of the determination enable signals is set to true, and the remaining determination enable signals are set to false, and a series of test sequences mounted on the BIST. , The next decision enable signal is set to true, and the remaining decision enable signals are set to false,
A failure log is generated while executing a series of test sequences mounted on the ST. The above problem is also solved by the invention of each claim as will be apparent from the following description.

[0014]

Embodiments of the present invention will be described. According to the present invention, referring to FIG. 1, when an input determination enable signal (31) is in an active state (indicating a determination permission state), an internal output signal (21) output from a circuit under test (20) and a BIST The circuit compares the expected value output from the circuit (10) with a logic value corresponding to a match or mismatch, and outputs a determination result signal (40). The determination enable signal is in an inactive state (indicating a determination impossible state). In some cases, a plurality of comparison circuits (30) that output a predetermined logic value as a determination result signal are provided corresponding to each of the plurality of internal output signals (21) output from the circuit under test. A plurality of judgment result signals (40) output from the comparison circuit (30), and a logic circuit (41) that outputs one output signal which is a predetermined logical operation result of these signals; For example, the output is output from the result output terminal (50) outside the apparatus logic circuit (41).

In the logic circuit (41), the judgment enable signal (31) input to the comparison circuit (30) is in an active state, and the internal output signal (21) input to the comparison circuit (30) is: If there is at least one comparison circuit that does not match the expected value (11), a failure (FAI
L), and outputs a logical value indicating normal (PASS) otherwise.

In the present invention, holding means for inputting and holding a judgment enable signal serially input from outside the device and outputting the signal in parallel (shift register 32 in FIG. 2)
And a plurality of signals output in parallel from the holding means (32) are a plurality of determination enable signals (31 _{1 in} FIG. 2).
To 31 ₄ ) are input in parallel to the comparison circuit (30A in FIG. 2).

In the present invention, a plurality of internal output signals output from the circuit under test are compared with expected values output from the BIST circuit, and when all of the plurality of internal output signals are normal, the normal value is output. and the failure value in the first result output pins case of failure in one, as a compressed signal, and outputs the first result output pins (50 ₁ in FIG. 3), corresponding to each internal output signal A comparison circuit (3 in FIG. 3) that outputs a determination result signal of a logical value corresponding to a match or mismatch with the expected value.
0B), and a plurality of holding means (42 in FIG. 3) for receiving and holding a plurality of determination result signals output from the comparison circuit.
If a failure occurs at least once in a series of BIST test sequence executions, the holding means (as shown in FIG. 3) which receives a determination result signal corresponding to a failure internal output signal output from the comparison circuit as an input. 42), a defective value is written to the result output pin (5) different from the first result output pin.
0 ₂ , 50 ₃ ).

The first result output pin (50 _{1 in} FIG. 3)
Is output, the result output pins (50 ₂ and 50 _{3 in} FIG. 3) different from the first result output pin (50 _{1 in} FIG. ₃ ).
Wherein by examining the value held in the plurality of holding means (42 ₁ to 42 ₄ of FIG. 3), it is made possible to determine which has become defective among the plurality of internal output signals from.

During the execution of a series of test sequences of the BIST, each time the comparison operation of the comparison circuit (30B) is performed, the comparison circuit (30B) updates the judgment holding value of the plurality of holding means (42).

The writing of the judgment result signal from the comparison circuit (30B) to the plurality of holding means (44 in FIG. 4) is performed by parallel input, and a shift register (FIG. 4) in which the plurality of holding means are cascaded. 44), the external terminal (50)
Output serially from

The plurality of holding means connected in cascade (FIG. 4)
Comprising the serial output from the shift register 44), the compressed signal (switching output to switched result output pins of the 40 ₅₎ in FIG. 4 circuit (45 in FIG. 4).

In the present invention, a high-speed clock generating circuit (70 in FIG. 5) for inputting an external clock from an external clock input pin and generating a frequency-multiplied clock (referred to as "high-speed clock") is driven by the high-speed clock. B
The IST circuit (10 in FIG. 5), the result output circuit (60 in FIG. 5) which receives the output of the circuit under test, the result output pins (50 ₁ and 50 _{2 in} FIG. 5), and the BIST circuit The circuit under test is tested, and a test result is serially output from the result output circuit to a shift register (61 in FIG. 5) in synchronization with the high-speed clock, and the shift register (61)
And a compression circuit (80) for compressing the test results output in parallel from each other and outputting the result to a result output terminal.

In the present invention, when a circuit to be tested is a memory array, and a test is performed using an automatic test apparatus (ATE) such as an LSI tester or a memory tester, a failure log is two-dimensionally corresponding to the address of the memory array. It is displayed (see FIG. 8).

The circuit under test includes a memory array, and the failure log recording means of the automatic test equipment (ATE) has an address (X, Y address) of a two-dimensional matrix, and corresponds to each clock for executing the test. And the BIST
Failure information is recorded at the address of the failure log recording means corresponding to the address of the memory array selected by the circuit (see FIG. 9).

In the present invention, a series of test sequences mounted on the BIST circuit are sequentially executed, and when a failure occurs, the test is stopped and the data held in the holding means is examined (see FIG. 10).

A series of test sequences mounted on the BIST are sequentially executed while judging a defect. When a defect occurs, the test is temporarily stopped, the data held in the judgment holding register is checked, and the data held in the judgment holding register is initialized. Then, in the series of test sequences mounted on the BIST, the test is executed again from the test following the stopped test (see FIG. 11).

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; In the following embodiment, a plurality of IPs (Intellectual
Property: Soft core, hard core, firm core, etc.)
, LSI with logic and memory, BIST
It is applied to a semiconductor integrated circuit such as a memory LSI with a function.

FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention. Internal data output 21 _{1 of} circuit under test 20
To 21 ₄ are inputted to the comparison circuit 30 ₁ to 30 _4.

The internal data output includes, for example, a data output bus from the circuit under test 20 to a CPU (not shown) incorporated in the same chip, data output from a plurality of circuits to be tested, and a plurality of circuits to be tested. This is a test-specific data output from each test area when the parallel test is performed by dividing the data into areas. Although _four internal data outputs 21 _{1 to} 21 ₄ are arranged in parallel, it goes without saying that the number of internal data outputs is not limited to four in the present invention.

Expected value 1 of test from BIST circuit 10
(11 _1), the expected value 2 (11 ₂₎ of the comparison circuit 30 ₁ to 30 ₄
Is input to In an example in which two internal data outputs have the same output value, the expected value signal lines for signal lines having the same output value are grouped into one, but the expected number of signal lines is the same as the number of internal data output signal lines. It may be. The comparator circuit 30 ₁ and 30 ₂ to the internal data output 1 (21 ₁₎ and the internal data output Input 2 (21 _2), BIST circuit 10
, The expected value 1 (11 ₁ ) of the test is input in common, and the internal data output 3 (21 ₃ ) and the internal data output 4 (21 ₄ )
The comparison circuit 30 ₃ and 30 ₄ which receives is expected second test (11 ₂₎ is commonly input, the expected value of the test from the BIST circuit 10 is input to the comparator circuit separately Needless to say, the configuration may be as follows.

In accordance with the number of internal data outputs (also referred to as "internal output signals"), judgment enable signals 31 _{1 to} 3 ₁
1 ₄ is inputted to the comparison circuit 30 ₁ to 30 _4. The signal values of the determination enable signals 31 _{1 to} 31 ₄ are, for example, true “1”.
(Inactive: enable the judgment),
False is “0” (active: determination is disabled).

In FIG. 1, other signals from the BIST circuit 10 to the circuit under test 20 required to operate the circuit under test 20 are omitted because they are not directly related to the subject of the present invention. .

[0033] In the comparison circuit 30 ₁ to 30 _4, when the value of the determination enable signal 31 _{1-31 4} input is true ( "1") when the expected value and the internal data output values are identical, comparison the output value 40 ₁ to 40 ₄ of the circuit 30 ₁ to 30 ₄ and a normal value, when the expected value and the internal data output values are different, the output value 40 ₁ to 40 ₄ of the comparator circuit and poor value. For example, the normal value of the output value 40 ₁ to 40 ₄ of the comparator circuit 30 ₁ to 30 ₄ is "1", the defective value is "0".

[0034] If the determination enable signal 31 _{1-31 4} is false ( "0"), the comparison circuit 30 ₁ to 30 _4, matching the expected value and the internal data output value, regardless of the discrepancy, the normal output value The value is “1”.

The output values 40 ₁ to ₄ of the comparison circuits 30 ₁ to 30 4
0 out of _4, in the case of all the normal value ( "1") outputs an output normal value to the result output pin 50, comparator circuits 30 ₁ ~
If there is a bad value in one of the output values of 30 _4,
The defective value is output to the result output pin 50. For example, the four comparator circuits 30 ₁ to 30 ₄ of the output 40 _{1-40 4} 4 inputs NA
The signal is input to the ND circuit 41, and the output of the NAND circuit 40 is output to the result output pin 50. In this case, the output normal value is “0”, and the output failure value is “1”.

The semiconductor integrated circuit of this embodiment has the advantage that all outputs of the circuit under test can be selectively examined even if the number of result output pins is reduced. A semiconductor integrated circuit (a semiconductor integrated circuit with a built-in BIST circuit) according to the present embodiment is replaced with a DUT (Device Under Test).
When a test is performed using an LSI tester, as described later, a failure log is generated while executing a series of test sequences in which one determination enable signal is set to true and the remaining determination enable signals are set to false, and the BIST is mounted. Subsequently, the next determination enable signal is set to true, and the remaining determination enable signals are set to false, and a failure log is generated while executing a series of test sequences mounted on the BIST.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, in the second embodiment of the present invention, internal data outputs 21 _{1 to} 21 of circuit under test 20 are shown.
₄ and the expected value signal 11 of the BIST circuit 10
Input to 0.

A signal serially input from an external pin 33 is applied to a shift register 32 having a four-stage flip-flop structure.
And holds four signal values (judgment enable signals).

The four signal values held in the shift register 32 are input to the comparison circuit 30A as _four determination enable signals 31 _{1 to} 31 ₄ . Comparison circuit 30A inputs respectively determination enable signal 31 _{1-31 4,} the four comparator circuits for comparing the internal signal 21 ₁ to 21 ₄ with the expected value (see FIG. 1), the output of the four comparator circuits And a NAND circuit (see FIG. 1) for outputting a result output signal based on the comparison result.

[0040] In the comparison circuit 30A, if each determination enable signal 12 ₁ to 12 ₄ corresponding to the four internal data output 21 ₁ to 21 ₄ of the circuit under test 20 is true (active state), the expected value signal And the output signal. If all the comparison results are normal, a normal value is output to the result output pin 50. If at least one of the comparison results is defective, a defective value is output to the result output pin.

In this embodiment, in addition to the advantages of the first embodiment, there is an advantage that only one input pin 33 for the judgment enable signal is required.

Next, a third embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the third exemplary embodiment of the present invention. Referring to FIG. 3, in the third embodiment of the present invention, the expected value signal 11 of the BIST circuit 10 and the four internal output signals 21 _{1 to} 21 _{4 of the} circuit under test 20 are compared with the comparison circuit 3.
0B.

[0043] The first result output pin 50 ₁ comparator circuit 3
From 0B, four comparison results are compressed and output. What compression method, if all is normal four internal output signal values result outputs normal value to the output pin 50 _1, in the case of failure in one is for outputting the result output pin 50 poor value ₁ and a comparison circuit 30B outputs the four comparator circuit for comparing the expected value of the internal signal 21 ₁ to 21 ₄ (see FIG. 1), the resulting output signal from the comparison result of the output of the four comparator circuits NA
It is configured with an ND circuit (see FIG. 1).

In FIG. 3, although the judgment enable signal is not explicitly shown, the judgment enable signal is input to the comparison circuit 30B in the configuration shown in FIG. 1 or FIG. 2 as in the first embodiment. Shall be.

The four judgment holding registers 42 _{1 to} 42 ₄ hold the judgment results 40 ₁ to 40 _{4 of the four} comparison circuits corresponding to the four internal output signals 21 _{1 to} 21 ₄ , respectively. .

If a failure occurs at least once in a series of BIST test sequence executions, a failure value is written to the determination holding register corresponding to the internal output signal.

The determination result holding register 42 _{1-42 4} holding value, the second through the determination holding result output circuit 43 can output a third result output pin 50 _2, 50 _3. In this embodiment, if the defect is output to the first result output pins 50 _1, second, third result output pin 50 ₂ or 50 ₃
From by examining the value held in the judgment holding register 41 _{1-41 4,} or which of the four internal output signal becomes defective, it can be examined using fewer pins.

As a fourth embodiment of the present invention, in FIG. 3, each time a comparison operation of the comparison circuit 30 is performed during the execution of a series of BIST test sequences, the judgment holding register 4
1 _{1-41 4} determination value may be configured to update.

The fourth embodiment of the present invention having such a configuration has an advantage that, in addition to the advantages of the third embodiment, good and bad can be checked for each test cycle.

Next, a fifth embodiment of the present invention will be described. FIG. 4 is a diagram showing the configuration of the fifth embodiment of the present invention. Referring to FIG. 4, in the fifth embodiment of the present invention, in the result output pin 50, compressing the comparison determination result between the four expected value of the internal data output 21 ₁ to 21 ₄ of the test circuit 20 an output 40 ₅ can be output separately via the four determination results 40 _{1-40 4} circuit 45 switches the in each comparison circuit.

The determination result how the output separately for four internal output of the test circuit 20, holding four determination results 40 _{1-40 4} parallel input to shift register 44 of the four-stage I do. The held data can be serially read from the shift register 44 to the external output pin 50. In switching circuit 45, the compressed output 40 ₅ individual output 40 _1-4
The number of external output pins can be reduced by selecting any one of O ₄ and switching the output. In this embodiment, since four determination results can be output to one external output pin, the chip size can be reduced.

FIG. 5 is a diagram showing the configuration of the sixth embodiment of the present invention. Referring to FIG. 5, in the sixth embodiment of the present invention, a low frequency clock is input from an external clock input pin 71. A high-frequency clock (“high-speed clock”) whose frequency has been multiplied by the high-speed clock generation circuit 70
). Examples of the high-speed clock generation circuit 70 include a circuit that generates an exclusive OR of two external clocks having different phases (in this case, the frequency is doubled).

The high-speed clock is input to the BIST circuit 10, and the BIST circuit 10 tests the circuit under test 20 with the high-speed clock (the operating frequency of the circuit under test 20 is defined by the high-speed clock).

The result output circuit 60 receives the test result of the circuit under test 20, and outputs the test result in synchronization with the high-speed clock. Test results are input to the shift register 61, the second result output pin 50 _2, each determination result is output serially.

The parallel output of the shift register 61 (when the high-speed clock frequency is a frequency obtained by doubling the external clock, the number of stages of the shift register 61 is, for example, two) is input to the compression circuit 80, and the compression circuit 80 In 80,
Compressing the test results of a plurality of high-speed clock, and outputs the first result output pin 50 ₁ at low frequencies. The high-speed test results output from the result output circuit 60 are sequentially held in the shift register 61. On the far end side from the input end (result output circuit 60) of the shift register 61, the test result of the past high-speed clock is held.

When the values held in the shift registers 61 are compressed by the compression circuit 80 that inputs the values in parallel, the compression values are updated every low-speed clock.

The present embodiment has an advantage that the circuit under test 20 can be tested at high speed using an inexpensive low-speed LSI tester.

FIG. 6 is a flow chart for explaining a seventh embodiment of the present invention. Referring to FIG.
A method for testing the semiconductor integrated circuit with a built-in BIST circuit having the configuration of the first embodiment shown in FIG.

The LSI tester inputs a clock for test execution to the BIST circuit 10, compares the judgment result from the result output pin 50 with an expected value of a non-defective product by a comparator of the LSI tester. A means for generating a failure log for the clock to be generated.

In a state where the failure log of the LSI tester is acquired, e of the judgment enable signal (31 _{1 to} 31 _{4 in} FIG. 1) is set.
When the test is executed (steps S3 and S4), and a series of test sequences mounted on the BIST are executed for each of e from 1 to the maximum value (steps S2 to S5, S6). ), End the bad log.

This embodiment has an advantage that all test results of internal data output can be acquired in a failure log by using a small number of external output pins.

FIG. 7 is a flowchart for explaining an eighth embodiment of the present invention. FIG. 7 shows a method of testing the BIST circuit-containing semiconductor integrated circuit having the configuration of the third embodiment. In the third embodiment described above, although the judgment enable signal is not explicitly shown, it is assumed that there is a judgment enable signal input to the comparison circuit 30 as in the first embodiment.

Assuming that all the judgment enable signals are true, B
Execute a series of tests mounted on the IST (step S
10, S11).

If at least one of the four internal data outputs has a failure, the test result is compressed and output to the result output pin 1 as a failure.

Next, when there is a defect (step S1)
2 of the YES branch), examining the determination result holding register 42 _{1-42 4.}

Only the internal data output corresponding to the number of the judgment holding register 42 holding the defective value is selectively set to true as a judgment enable signal, and a series of tests mounted on the BIST are executed.

In FIG. 7, the defective holding values are H (1) to H (4) corresponding to the internal data output numbers. The number corresponding to the number (subscript) of the determination holding registers 42 _{1 to} 42 ₄ is e. If e is between 1 and the maximum value, and H (e) is a normal value, e = e + 1.

If H (e) is a defective value (YES branch of step S15), only the e-th judgment enable signal is set to true, the other judgment enable signals are set to false, and a series of tests mounted on the BIST are executed. (Steps S16 and S1
7). This is repeated until e reaches the maximum value (step S18).

In the present embodiment, since only the portion corresponding to the internal data output having a defect can be selectively tested, there is an advantage that the test time can be reduced.

FIG. 8 is a diagram for explaining a ninth embodiment of the present invention. Referring to FIG. 8, when the circuit under test is a built-in memory array, the fault log in the seventh embodiment is converted into a two-dimensional array similar to the built-in memory array by the conversion unit 110, and Displayed at 120.

When a plurality of tests are performed on the same address on the array, if the test result of the same address has a defect even once, the defect is displayed on the corresponding address section of the defect display section 120. . This embodiment has an advantage that a two-dimensional defect display corresponding to the built-in memory array can be performed.

FIG. 9 is a diagram for explaining a tenth embodiment of the present invention. Referring to FIG. 9, the defect recording unit 13
It has an X register 103 and a Y register 104 for specifying the coordinates of 0 or a two-dimensional matrix of the defect display unit 120.

For each of the test clock numbers,
The values of the X register 103 and the Y register 104 are assigned. The value of the register may be given by a numerical value for each clock or by an arithmetic expression. When given by an arithmetic expression, fewer settings are required to specify the register value.

If the test result at a certain test clock is bad, the X register 103 and the Y register 10
The defect information is recorded in the defect recording unit 130 corresponding to the value of 4, and the defect is displayed on the defect display unit 131.

The present embodiment has the advantage that the size of the failure log does not depend on the test size, the size of the memory array can be used, and a two-dimensional failure display corresponding to the built-in memory array can be performed.

FIG. 10 is a flowchart for explaining an eleventh embodiment of the present invention. Referring to FIG. 10, in the method for testing a semiconductor integrated circuit with a built-in BIST circuit having the configuration of the fourth embodiment, when a series of test sequences mounted on the BIST are sequentially executed while judging a defect, and a defect occurs. Then, the test is stopped and the data held in the judgment holding register 42 is checked (step S2).
4).

In this embodiment, during the test execution, processing for outputting the result is not required, the test can be executed at the original speed to be tested, and when a failure occurs, which of the internal data outputs becomes defective. Can be checked.

FIG. 11 is a flowchart showing a twelfth embodiment of the present invention. Referring to FIG. 11, the test method of this embodiment is different from the test method of the semiconductor integrated circuit with a built-in BIST circuit of the fourth embodiment in that
A series of test sequences mounted on the ST are sequentially executed while determining a failure (steps S32 and S33). When a failure occurs, the test is temporarily stopped and the data held in the determination holding register 42 is examined (step S34).

Next, in the series of test sequences mounted on the BIST, the test is executed again from the test following the stopped test (steps S35, S36, S3).
2).

In this embodiment, each test can be executed at the original speed to be tested, and when a failure occurs, which of the internal data outputs has failed can be checked. Can be checked for defects.

[0081]

As described above, according to the present invention,
The following effects are obtained.

A first advantage of the present invention is that the number of output pins for outputting the determination result of the circuit under test having a plurality of internal output signals is reduced, and the internal circuit under test is implemented using a small number of external pins. Can be tested.

A second effect of the present invention is that the test target circuit having a plurality of internal output signals can be checked for good or defective individual internal output signals using a small number of external pins.

The third effect of the present invention is that the circuit under test and the BIST circuit are driven by a high-speed clock obtained by multiplying the low-speed clock, and the result output is output in a low-speed clock cycle. That is, the circuit under test can be tested at high speed.

A fourth effect of the present invention is that when the circuit under test is a memory device, a two-dimensional failure log corresponding to the memory array is generated and two-dimensionally displayed, thereby facilitating failure analysis. ,That's what it means.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of the seventh embodiment of the present invention.

FIG. 7 is a flowchart for explaining the operation of the eighth embodiment of the present invention.

FIG. 8 is a diagram for explaining a ninth embodiment of the present invention.

FIG. 9 is a diagram for explaining a tenth embodiment of the present invention.

FIG. 10 is a flowchart for explaining the operation of the eleventh embodiment of the present invention.

FIG. 11 is a flowchart for explaining the operation of the twelfth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a semiconductor memory device provided with a conventional BIST circuit.

FIG. 13 is a diagram showing a configuration of a conventional semiconductor memory device provided with a BIST circuit.

[Explanation of symbols]

Reference Signs List 10 BIST circuit 11, 11 ₁ , 11 ₂ Expected value 20 Tested circuit 21 _{1 to} 21 ₄ Internal data output 30, 30 ₁ to 30 ₄ Comparison circuit 31 _{1 to} 31 ₄ Judgment enable signal 32 Shift register 33 Pin 40 Judgment result output 40 ₁ to 40 ₄ Judgment result output 40 ₅ Compression output 41 NAND circuit 42 _{1 to} 42 ₄ Judgment holding register 43 Judgment holding result output 44 Shift register 45 Switching circuit 50 Result output pin 60 Result output circuit 70 High-speed clock generation circuit 80 Compression circuit 101 Test Clock Number 102 Failure Log (Test Result) 103 X Register 104 Y Register 110 Conversion Unit 120 Failure Display Unit 130 Failure Storage Unit

Claims (18)

[Claims] 1. A BIST (Build) for testing a circuit under test.
In a semiconductor integrated circuit device with a built-in BIST circuit having a (T In Self Test) circuit, an internal output signal output from the circuit under test and an expected output output from the BIST circuit when an input determination enable signal is in an active state. Compare with the value, and output the judgment result signal of the logical value corresponding to the match or mismatch,
When the determination enable signal is in the inactive state, a comparison circuit configured to output a predetermined logic value is provided in correspondence with each of the plurality of internal output signals output from the circuit under test. A plurality of logic circuits that input a plurality of determination result signals output from the plurality of comparison circuits and output one output signal that is a predetermined logical operation result of these signals; A BIST circuit-containing semiconductor integrated circuit device, which is output from an output terminal to the outside of the device. 2. The logic circuit according to claim 1, wherein at least one of the plurality of comparison circuits has an input determination enable signal in an active state and the input internal output signal does not match the expected value. 2. The semiconductor integrated circuit with a built-in BIST circuit according to claim 1, wherein a logical value indicating a failure (FAIL) is output when the signal exists, and a logical value indicating a normal (PASS) is output otherwise. Circuit device. 3. A means for inputting and holding a plurality of determination enable information serially input from the outside of the device and outputting the information in parallel, wherein the plurality of signals output in parallel are used as the plurality of determination enable signals. 2. The BIS according to claim 1, wherein the signals are input to the plurality of comparison circuits.
Semiconductor integrated circuit device with built-in T circuit. 4. A holding means for storing and holding a judgment result signal output from the comparison circuit, wherein the holding means detects a failure if at least one failure occurs before a series of test sequences is completed. 2. The semiconductor integrated circuit device with a built-in BIST circuit according to claim 1, wherein the semiconductor integrated circuit device holds a value and outputs the held data to the outside of the device. 5. A BIST (Build) for testing a circuit under test.
t In Self Test) circuit, comprising: a plurality of internal output signals output from the circuit under test and an expected value output from the BIST circuit; If all of the signals are normal, assume a normal value,
A comparison circuit that outputs a compressed signal indicating a defective value when at least one of the signals is defective, and outputs a logic value determination result signal corresponding to a match or mismatch between each internal output signal and a corresponding expected value; The compressed signal is output from a first result output terminal to the outside of the device, and includes a plurality of holding units that receive and hold a plurality of determination result signals output from the comparison circuit. If a failure occurs at least once, a failure value is written to the holding unit that receives the determination result signal corresponding to the failure internal output signal output from the comparison circuit, and the first result output terminal BIST, wherein a defective value held by the holding means is output from another result output terminal.
Semiconductor integrated circuit device with built-in circuit. 6. A logic circuit for comparing an internal output signal output from the circuit under test with an expected value output from the BIST circuit when the input determination enable signal is in an active state. A comparison circuit that outputs a predetermined logic value when the judgment enable signal is in an inactive state, and outputs a plurality of internal output signals output from the circuit under test. A plurality of comparison circuits, wherein, among the plurality of comparison circuits, the input determination enable signal is in an active state, and the input internal output signal does not match the expected value. If at least one circuit exists, a logical value indicating a failure (FAIL), otherwise, a logical value indicating a normal (PASS), 6. The semiconductor integrated circuit device having a built-in BIST circuit according to claim 5, wherein the semiconductor integrated circuit device outputs the compressed signal. 7. When a defective value is output to said first result output terminal, a plurality of holding values of said plurality of holding means are checked from a result output terminal different from said first result output terminal. 6. It is possible to check which one of the internal output signals has become defective.
Or a semiconductor integrated circuit device with a built-in BIST circuit according to 6. 8. During execution of a series of test sequences in a BIST, each time the comparison operation of the comparison circuit is performed, the comparison circuit updates the judgment holding values of the plurality of holding units.
7. The semiconductor integrated circuit device with a built-in BIST circuit according to claim 5, wherein: 9. The writing of the determination result signal from the comparison circuit to the plurality of holding units is performed in parallel, the plurality of holding units are cascade-connected, and the held data held by the plurality of holding units are written. 7. The semiconductor integrated circuit device with a built-in BIST circuit according to claim 5, wherein the signal is output serially from an external terminal. 10. A switching circuit for switching between a serial output from the output terminals of the plurality of holding means connected in cascade and a compression signal and outputting the compressed signal to a result output terminal. A semiconductor integrated circuit device having a built-in BIST circuit according to the above. 11. A BIST (Bu) for testing a circuit under test.
In a semiconductor integrated circuit device with a built-in BIST circuit provided with an ilt in self test) circuit, an external clock is input from an external clock input terminal, and a high-speed clock (hereinafter referred to as a “high-speed clock”) is generated by multiplying the frequency of the external clock. A clock output circuit, wherein the BIST circuit drives and tests the circuit under test with the high-speed clock output from the high-speed clock generation circuit, and a result output circuit that receives an output of the circuit under test as an input; A plurality of holding means connected in cascade, wherein the output from the result output circuit is synchronized with the high-speed clock, and the output of the plurality of holding means serially input to the plurality of holding means and connected in cascade. A test result held in the plurality of holding means is serially output from an output end from a first result output terminal, and the plurality of holding results are output. A BIST circuit-incorporated semiconductor integrated circuit device, comprising: a compression circuit that inputs and compresses test results output in parallel from the holding means and outputs the result to a second result output terminal. 12. The BIST circuit according to claim 1, wherein said BIST circuit supplies an expected value in common to a plurality of comparison circuits for comparing internal output signals outputting the same value. A semiconductor integrated circuit device with a built-in BIST circuit. 13. A BIST (Bu) for testing a circuit under test.
ilt In Self Test) circuit, and when an input decision enable signal is in an active state, compares an internal output signal output from the circuit under test with an expected value output from the BIST circuit, A comparison circuit configured to output a determination result signal of a logic value corresponding to the mismatch and to output a predetermined logic value when the determination enable signal is in an inactive state is output from the circuit under test. A plurality of judgment result signals output from the plurality of comparison circuits, and outputs one output signal which is a predetermined logical operation result of these signals. A method for testing a semiconductor integrated circuit device having an output logic circuit, wherein the output of the logic circuit is output from a result output terminal to the outside of the device using an automatic test device A clock for executing a test is input to the BIST circuit from the automatic test apparatus, and a determination result from the result output terminal is compared with an expected value of a non-defective product on the automatic test apparatus. In the case of the above, a failure log for the corresponding clock is generated. After that, the next decision enable signal is set to true, and the remaining decision enable signals are set to false, and the BI
A test method, wherein a failure log is generated while executing a series of test sequences mounted on an ST circuit. 14. A semiconductor integrated circuit device comprising: holding means for storing and holding a determination result signal output from the comparison circuit, wherein the holding means is provided at least once before a series of test sequences is completed. When a failure occurs, the failure value is held, the held data is output to the outside of the device, and one of the determination enable signals is enabled to enable the B
After executing a series of test sequences mounted on the IST circuit, if a failure value is output to the result output terminal,
A series of test sequences mounted on the BIST circuit are executed by sequentially setting only one of the determination enable signals corresponding to the internal output signals in which the data held by the holding unit has a defective value to true. Claim 1
3. The test method according to 3. 15. The test method according to claim 13, wherein said circuit under test includes a memory array, and said failure log is displayed two-dimensionally in correspondence with an address of said memory array. 16. The circuit under test includes a memory array, the failure log recording means of the automatic test apparatus has an address of a two-dimensional matrix, and the B corresponds to each clock for executing the test.
15. The test method according to claim 13, wherein failure information is recorded at an address of said failure log recording means corresponding to an address of said memory array selected by an IST circuit. 17. The semiconductor integrated circuit device includes a plurality of holding means for receiving and holding a plurality of determination result signals output from the comparison circuit, and the BIST circuit is defective even at least once in a series of test sequence executions. Occurs, a defective value is written to the holding unit that receives a determination result signal corresponding to a defective internal output signal output from the comparison circuit, and a result output different from the first result output terminal is output. In testing the semiconductor integrated circuit device output from the terminal, a series of test sequences mounted on the BIST circuit are sequentially executed, and when a failure occurs, the test is stopped and the data held in the holding unit is examined. 14. The test method according to claim 13, wherein: 18. A series of test sequences mounted on the BIST circuit are sequentially executed while judging a defect. When a defect occurs, the test is temporarily stopped, and after examining data held in the holding means, 14. The test method according to claim 13, wherein the data held in the holding means is initialized, and the test is executed again from the test following the stopped test in the test sequence.