JP2002343904A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002343904A
JP2002343904A JP2001150502A JP2001150502A JP2002343904A JP 2002343904 A JP2002343904 A JP 2002343904A JP 2001150502 A JP2001150502 A JP 2001150502A JP 2001150502 A JP2001150502 A JP 2001150502A JP 2002343904 A JP2002343904 A JP 2002343904A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
semiconductor
resin
posts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001150502A
Other languages
Japanese (ja)
Inventor
Yuji Yagi
優治 八木
Takafumi Kashiwagi
隆文 柏木
Masaaki Katsumata
雅昭 勝又
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001150502A priority Critical patent/JP2002343904A/en
Publication of JP2002343904A publication Critical patent/JP2002343904A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is easy to handle, even if being formed thin, while semiconductor elements are formed thin to mount them at high density in the prior art, but base materials used for the semiconductor elements are brittle enough to break, thus making difficult handling in the thinned condition. SOLUTION: A semiconductor element 1 is mounted in a face-down manner on a surface of a printed board 5 with electrode posts 3 formed thereon, the electrode posts 3 and the element 1 are molded with a resin 4, and only the molded surface of the resin 4 is polished until the posts 3 appear on the surface. Thus, the semiconductor element is mounted by face-down mounting less in increase in the thickness on a flexible printed board and the polishing follows to realize a semiconductor device easy to handle, even if being formed thin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子を高密度
実装してなる半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor elements are mounted at high density.

【0002】[0002]

【従来の技術】近年、小型携帯機器の急速な普及に伴っ
て、半導体装置の需要が急速に伸びてきている。特に、
機器の軽薄短小化にも関わらず、多機能化が望まれてい
るため、多数の半導体素子を高密度実装する必要があ
る。そのため、これまで、半導体素子は、パッケージ品
として取り扱われてきたが、最近は、ベアチップで取り
扱われることも稀ではなく、更には、半導体素子を厚み
方向に積載する三次元実装まで提案されている。現在、
提案されている三次元実装の主なものを図9に示す。図
9のように、三次元実装は、これまでの高密度実装化と
は違って、プリント基板の厚み方向にも実装エリアを確
保できるため、より機器の小型化に貢献できる。また、
図9のように、厚み方向に積層しても機器の厚み方向へ
の拡大に繋がらないようにするために、半導体素子を研
磨により、大幅に薄板化し、その問題の解決を図ってい
る。
2. Description of the Related Art In recent years, with the rapid spread of small portable devices, demand for semiconductor devices has been rapidly growing. In particular,
Despite the lightness, size, and size of devices, multifunctionality is demanded, so that a large number of semiconductor elements must be mounted at high density. For this reason, semiconductor devices have been handled as packaged products so far, but recently, they are not rarely handled as bare chips, and furthermore, three-dimensional mounting in which semiconductor devices are stacked in the thickness direction has been proposed. . Current,
The main three-dimensional implementation proposed is shown in FIG. As shown in FIG. 9, unlike the conventional high-density mounting, the three-dimensional mounting can secure a mounting area also in the thickness direction of the printed circuit board, and thus can contribute to further downsizing of the device. Also,
As shown in FIG. 9, in order that lamination in the thickness direction does not lead to expansion of the device in the thickness direction, the semiconductor element is greatly thinned by polishing to solve the problem.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、シリコ
ン等の半導体素子に使われる基材は、脆く割れやすいた
め、薄板化した状態での取り扱いが非常に難しかった。
However, the base material used for semiconductor elements such as silicon is brittle and easily broken, so that it is very difficult to handle the base material in a thinned state.

【0004】そこで本発明は、薄型化しても取り扱いの
し易く、高密度実装に適した半導体装置を提供するもの
である。
Accordingly, the present invention provides a semiconductor device which is easy to handle even if it is made thinner and is suitable for high-density mounting.

【0005】[0005]

【課題を解決するための手段】この課題を解決するため
に本発明の半導体装置は、電極ポストを形成してなるプ
リント基板の前記電極ポスト形成面側に、半導体素子を
フェイスダウン実装し、前記電極ポスト及び前記半導体
素子を樹脂モールドした後、前記樹脂モールド面側の
み、少なくとも前記電極ポストが表面化するまで研磨し
てなることを特徴としている。この発明によれば、柔軟
性のあるプリント基板上に半導体素子を、厚み増加の比
較的少ないフェイスダウン実装を用いて実装し、その
後、研磨するため、薄型化しても取り扱いのし易い半導
体装置を実現することができる。
In order to solve this problem, a semiconductor device according to the present invention comprises a semiconductor element mounted face down on a surface of a printed circuit board on which an electrode post is formed on the electrode post forming surface side. After the electrode posts and the semiconductor element are resin-molded, only the resin mold surface is polished at least until the electrode posts are surfaced. According to the present invention, a semiconductor device is mounted on a flexible printed board using face-down mounting with a relatively small increase in thickness, and then polished. Can be realized.

【0006】[0006]

【発明の実施の形態】本発明の請求項1に記載の発明
は、電極ポストを形成してなるプリント基板の前記電極
ポスト形成面側に、半導体素子をフェイスダウン実装
し、前記電極ポスト及び前記半導体素子を樹脂モールド
した後、前記樹脂モールド面側のみ、少なくとも前記電
極ポストが表面化するまで研磨してなることを特徴とし
ており、薄型化しても取り扱いのし易い半導体装置を実
現することができる。
According to the first aspect of the present invention, a semiconductor element is mounted face-down on the electrode post forming surface side of a printed circuit board on which an electrode post is formed, and the electrode post and the electrode post are mounted. After the semiconductor element is resin-molded, only the resin-molded surface is polished until at least the electrode posts are surfaced, so that a semiconductor device which is easy to handle even when thinned can be realized.

【0007】本発明の請求項2に記載の発明は、請求項
1記載の半導体装置であって、電極ポストを形成する箇
所の裏面側に接続電極を形成したプリント基板を用いる
ことを特徴としており、これにより、請求項1記載の半
導体装置を厚み方向にも積載することができる。
According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a printed circuit board on which connection electrodes are formed on a back surface side of a place where an electrode post is formed is used. Thus, the semiconductor device according to claim 1 can be stacked in the thickness direction.

【0008】本発明の請求項3に記載の発明は、複数個
の請求項2記載の半導体装置を積載し、熱プレスするこ
とにより、電極ポストと接続電極を接続してなることを
特徴としており、請求項2記載の半導体装置を厚み方向
に積載するための方法を示している。
A third aspect of the present invention is characterized in that a plurality of the semiconductor devices according to the second aspect are stacked and hot-pressed to connect the electrode posts and the connection electrodes. And a method for stacking the semiconductor device according to claim 2 in the thickness direction.

【0009】本発明の請求項4に記載の発明は、複数個
の請求項2記載の半導体装置間で、電極ポストと接続電
極間を半田接続してなることを特徴としており、請求項
2記載の半導体装置を厚み方向に積載するための請求項
3とは別の方法を示している。
According to a fourth aspect of the present invention, an electrode post and a connection electrode are connected by soldering between a plurality of the semiconductor devices according to the second aspect. Another method for loading semiconductor devices in the thickness direction is shown.

【0010】本発明の請求項5に記載の発明は、ウエハ
状態で、半導体素子の入出力端子部に電極ポストを形成
し、前記電極ポストの周囲に樹脂形成し、前記ウエハを
両面研磨により、少なくとも前記電極ポストが表面化す
るまで薄板化した後、前記半導体素子を個片化し、前記
個片化した半導体素子をプリント基板上に熱プレスする
ことにより、前記電極ポストと前記プリント基板の接続
電極を接続してなることを特徴としており、プリント基
板への接続を果たす電極ポストと封止樹脂層の形成をウ
エハ状態で行え、さらに、薄型化しても取り扱いのし易
い構造を実現することができる。
According to a fifth aspect of the present invention, in a wafer state, an electrode post is formed on an input / output terminal portion of a semiconductor element, a resin is formed around the electrode post, and the wafer is polished on both sides. After thinning at least until the electrode posts are surfaced, the semiconductor elements are singulated, and the diced semiconductor elements are hot-pressed on a printed circuit board to connect the electrode posts and the connection electrodes of the printed circuit board. The connection is characterized in that the electrode posts and the sealing resin layer for connecting to the printed circuit board can be formed in a wafer state, and furthermore, a structure which is easy to handle even when thinned can be realized.

【0011】以下、本発明の実施の形態について図1,
2を用いて説明する。
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
2 will be described.

【0012】(実施の形態1)図1は、本実施の形態1
での半導体装置の形成方法を示す模式図である。図1に
おいて、1は半導体素子、2はバンプ、3は電極ポス
ト、4は樹脂、5はプリント基板を示す。
(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
FIG. 4 is a schematic view showing a method for forming a semiconductor device in FIG. In FIG. 1, reference numeral 1 denotes a semiconductor element, 2 denotes a bump, 3 denotes an electrode post, 4 denotes a resin, and 5 denotes a printed board.

【0013】図1に示す通り、本実施の形態での半導体
装置の形成は、(a)電極ポスト3を実装面側に形成し
たプリント基板5に半導体素子1をフェイスダウン実装
し、(b)半導体素子1と電極ポスト3を覆うように樹
脂4でモールドし、(c)樹脂4面を少なくとも電極ポ
スト3が表面化するまで研磨することにより行う。電極
ポストは、銅または半田等をメッキにより形成する。フ
ェイスダウン実装には、熱硬化性樹脂11による方法
(図2)または半田バンプ2aによる方法(図3)また
は金バンプ2bと導電ペースト12による方法(図4)
等を用いる。熱硬化性樹脂による実装の場合、フェイス
ダウン実装後、新たに樹脂でモールドする必要がある
が、半田バンプまたは金バンプと導電ペーストによる実
装の場合、半導体素子とプリント基板の間の封止に用い
る樹脂を、半導体素子と電極ポストをモールドするため
にも用いる。
As shown in FIG. 1, the semiconductor device according to the present embodiment is formed by (a) mounting the semiconductor element 1 face down on a printed board 5 having an electrode post 3 formed on a mounting surface side, and (b) This is performed by molding with a resin 4 so as to cover the semiconductor element 1 and the electrode posts 3 and (c) polishing the surface of the resin 4 at least until the electrode posts 3 are surfaced. The electrode posts are formed by plating copper or solder. For face-down mounting, a method using a thermosetting resin 11 (FIG. 2), a method using a solder bump 2a (FIG. 3), or a method using a gold bump 2b and a conductive paste 12 (FIG. 4).
And so on. In the case of mounting with thermosetting resin, it is necessary to newly mold with resin after face-down mounting, but in the case of mounting with solder bumps or gold bumps and conductive paste, it is used for sealing between the semiconductor element and the printed board Resin is also used to mold the semiconductor element and the electrode posts.

【0014】これまで、シリコン等の半導体素子に使わ
れる基材は脆く割れ易いため、150μm以下になる
と、ハンドリングが難しかった。一方、本実施の形態で
は、柔軟性のあるプリント基板上に半導体素子をフェイ
スダウン実装後、研磨するため、10μm程度まで薄型
化可能であり、更にフェイスダウン実装での厚み増加と
して30μmと、プリント基板の厚み80μm程度を合
計しても、150μm以下の半導体装置を、薄型化して
も取り扱いのし易い構造で実現することができる。
Heretofore, a substrate used for a semiconductor element such as silicon has been fragile and easily broken. On the other hand, in the present embodiment, since the semiconductor element is mounted face-down on a flexible printed board and then polished, the thickness can be reduced to about 10 μm, and the thickness in face-down mounting is increased to 30 μm. Even if the total thickness of the substrate is about 80 μm, a semiconductor device having a thickness of 150 μm or less can be realized with a structure that is easy to handle even if the thickness is reduced.

【0015】(実施の形態2)図5は、本実施の形態2
での半導体装置の断面図である。図5において、5aは
プリント基板、6は接続電極を示す。
(Embodiment 2) FIG. 5 shows Embodiment 2 of the present invention.
FIG. 4 is a cross-sectional view of the semiconductor device at FIG. In FIG. 5, 5a indicates a printed circuit board, and 6 indicates a connection electrode.

【0016】図5に示す通り、本実施の形態での半導体
装置は、実施の形態1とほぼ同様の形態をなす。
As shown in FIG. 5, the semiconductor device according to the present embodiment has substantially the same form as that of the first embodiment.

【0017】特徴としては、電極ポスト3を形成する箇
所の裏面側に接続電極6を形成したプリント基板5aを
用いることである。この形態にすることにより、より高
密度実装化を実現するための厚み方向への積載も可能に
できる。
A feature is that a printed circuit board 5a having connection electrodes 6 formed on the back surface side of the places where the electrode posts 3 are formed is used. With this configuration, stacking in the thickness direction for realizing higher-density mounting can be performed.

【0018】図6,7は、その厚み方向に積載する2つ
の方法を示している。まず、1つの方法は、図6に示す
通り、本実施の形態で示す半導体装置7を複数個積載
し、熱プレスすることにより、電極ポスト3と接続電極
6を接続してなる。熱プレスの際、樹脂4はプリント基
板5aに接着され、十分な接続信頼性が得られる構造を
なす。次に、もう1つの方法は、図7に示す通り、本実
施の形態で示す半導体装置7間で、電極ポスト3と接続
電極6間を半田8で接続してなる。
FIGS. 6 and 7 show two methods of stacking in the thickness direction. First, in one method, as shown in FIG. 6, a plurality of semiconductor devices 7 described in the present embodiment are stacked and hot-pressed to connect the electrode posts 3 and the connection electrodes 6. At the time of hot pressing, the resin 4 is adhered to the printed circuit board 5a, and has a structure with sufficient connection reliability. Next, as shown in FIG. 7, another method is to connect the electrode posts 3 and the connection electrodes 6 with the solder 8 between the semiconductor devices 7 shown in this embodiment.

【0019】(実施の形態3)図8は、本実施の形態3
での半導体装置の形成方法を示す模式図である。図8に
おいて、3aは電極ポスト、4aは樹脂、5cはプリン
ト基板、9はウエハ、10は入出力端子、13は加圧加
熱ツール、14はダイシングソーを示す。
(Embodiment 3) FIG. 8 shows Embodiment 3 of the present invention.
FIG. 4 is a schematic view showing a method for forming a semiconductor device in FIG. In FIG. 8, 3a denotes an electrode post, 4a denotes a resin, 5c denotes a printed board, 9 denotes a wafer, 10 denotes an input / output terminal, 13 denotes a pressure heating tool, and 14 denotes a dicing saw.

【0020】図8に示す通り、本実施の形態での半導体
装置は、(a)ウエハ9の状態で、半導体素子1の入出
力端子10に電極ポスト3aを形成し、(b)電極ポス
ト3aの周囲に樹脂4aを形成し、(c)ウエハ9を両
面研磨により、少なくとも電極ポスト3aが表面化する
まで薄板化した後、(d)各半導体素子1に個片化し、
(e)個片化した半導体素子1をプリント基板5c上に
熱プレスすることにより形成する。熱プレスの際、樹脂
はプリント基板に接着され、十分な接続信頼性が得られ
る構造をなす。また、電極ポストは、銅または半田等を
メッキにより形成する。
As shown in FIG. 8, the semiconductor device according to the present embodiment includes (a) an electrode post 3a formed on an input / output terminal 10 of a semiconductor element 1 in a state of a wafer 9, and (b) an electrode post 3a. (C) After the wafer 9 is thinned by double-side polishing until at least the electrode posts 3a are surfaced, (d) the wafer 9 is separated into individual semiconductor elements 1,
(E) The individualized semiconductor elements 1 are formed by hot pressing on the printed circuit board 5c. At the time of hot pressing, the resin is adhered to the printed circuit board to form a structure capable of obtaining sufficient connection reliability. The electrode posts are formed by plating copper or solder.

【0021】このように、本実施の形態では、プリント
基板への接続を果たす電極ポストと封止樹脂層の形成を
多数個一括処理のできるウエハ状態で行え、さらに柔軟
性のある樹脂層を有した状態で研磨するため、薄型化し
ても取り扱いのし易い構造を実現することができる。
As described above, in the present embodiment, the formation of the electrode posts for connecting to the printed circuit board and the sealing resin layer can be performed in a wafer state in which a large number of electrode posts can be collectively processed. Since the polishing is performed in a state in which it is made thin, it is possible to realize a structure that is easy to handle even if the thickness is reduced.

【0022】[0022]

【発明の効果】以上のように本発明での半導体装置は、
柔軟性のあるプリント基板上に半導体素子を、厚み増加
の比較的少ないフェイスダウン実装を用いて実装し、そ
の後、研磨するため、薄型化しても取り扱いのし易い形
態を実現することができる。
As described above, the semiconductor device according to the present invention is:
Since the semiconductor element is mounted on a flexible printed circuit board using face-down mounting with a relatively small increase in thickness, and then polished, it is possible to realize a form that is easy to handle even if the thickness is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施の形態1での半導体装置の形成方法を示す
模式工程断面図
FIG. 1 is a schematic process cross-sectional view illustrating a method for forming a semiconductor device in Embodiment 1.

【図2】熱硬化性樹脂による実装方法を示す模式工程断
面図
FIG. 2 is a schematic process sectional view showing a mounting method using a thermosetting resin.

【図3】半田バンプによる実装方法を示す模式工程断面
FIG. 3 is a schematic process sectional view showing a mounting method using solder bumps.

【図4】金バンプと導電ペーストによる実装方法を示す
模式工程断面図
FIG. 4 is a schematic process sectional view showing a mounting method using a gold bump and a conductive paste.

【図5】実施の形態2での半導体装置の模式断面図FIG. 5 is a schematic cross-sectional view of a semiconductor device in Embodiment 2.

【図6】実施の形態2での半導体装置を熱プレスにより
積載する方法を示す模式工程断面図
FIG. 6 is a schematic process cross-sectional view illustrating a method of mounting the semiconductor device according to the second embodiment by hot pressing;

【図7】実施の形態2での半導体装置を半田により積載
する方法を示す模式断面図
FIG. 7 is a schematic cross-sectional view showing a method for mounting the semiconductor device according to the second embodiment by soldering;

【図8】実施の形態3での半導体装置の形成方法を示す
模式工程図
FIG. 8 is a schematic process diagram illustrating a method for forming a semiconductor device in Embodiment 3.

【図9】従来の3次元実装での形態を示す摸式断面図FIG. 9 is a schematic cross-sectional view showing a form in a conventional three-dimensional mounting.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 バンプ 3 電極ポスト 4 樹脂 5 プリント基板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bump 3 Electrode post 4 Resin 5 Printed circuit board

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 25/11 25/18 (72)発明者 勝又 雅昭 大阪府門真市大字門真1006番地 松下電器 産業株式会社内──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/11 25/18 (72) Inventor Masaaki Katsumata 1006 Kadoma, Oji, Kadoma, Osaka Matsushita Electric Industrial Co., Ltd. Inside

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 電極ポストを形成してなるプリント基板
の前記電極ポスト形成面側に、半導体素子をフェイスダ
ウン実装し、前記電極ポスト及び前記半導体素子を樹脂
モールドした後、前記樹脂モールド面側のみ、少なくと
も前記電極ポストが表面化するまで研磨してなることを
特徴とする半導体装置。
1. A semiconductor device is mounted face-down on a side of the electrode post forming surface of a printed circuit board on which an electrode post is formed, and the electrode post and the semiconductor element are resin-molded. A semiconductor device which is polished until at least the electrode posts are surfaced.
【請求項2】 電極ポストを形成する箇所の裏面側に接
続電極を形成したプリント基板を用いることを特徴とす
る請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a printed circuit board on which connection electrodes are formed on the rear surface side of the place where the electrode posts are formed is used.
【請求項3】 複数個の請求項2記載の半導体装置を積
載し、熱プレスすることにより、電極ポストと接続電極
を接続してなることを特徴とする半導体装置。
3. A semiconductor device comprising a plurality of the semiconductor devices according to claim 2 mounted thereon and hot-pressed to connect the electrode posts and the connection electrodes.
【請求項4】 複数個の請求項2記載の半導体装置間
で、電極ポストと接続電極間を半田接続してなることを
特徴とする半導体装置。
4. A semiconductor device comprising a plurality of semiconductor devices according to claim 2, wherein electrode posts and connection electrodes are connected by soldering.
【請求項5】 ウエハ状態で、半導体素子の入出力端子
部に電極ポストを形成し、前記電極ポストの周囲に樹脂
形成し、前記ウエハを両面研磨により、少なくとも前記
電極ポストが表面化するまで薄板化した後、前記半導体
素子を個片化し、前記個片化した半導体素子をプリント
基板上に熱プレスすることにより、前記電極ポストと前
記プリント基板の接続電極を接続してなることを特徴と
する半導体装置。
5. In a wafer state, an electrode post is formed at an input / output terminal portion of a semiconductor element, a resin is formed around the electrode post, and the wafer is thinned by double-side polishing until at least the electrode post is surfaced. After that, the semiconductor element is singulated, and the diced semiconductor element is hot-pressed on a printed circuit board, thereby connecting the electrode posts and connection electrodes of the printed circuit board. apparatus.
JP2001150502A 2001-05-21 2001-05-21 Semiconductor device Pending JP2002343904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001150502A JP2002343904A (en) 2001-05-21 2001-05-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001150502A JP2002343904A (en) 2001-05-21 2001-05-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2002343904A true JP2002343904A (en) 2002-11-29

Family

ID=18995503

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002343904A (en)

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JP2007158331A (en) * 2005-11-30 2007-06-21 Freescale Semiconductor Inc Packaging method of semiconductor device
JP2007287762A (en) * 2006-04-13 2007-11-01 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit element, its manufacturing method and semiconductor device
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US8395269B2 (en) 2005-12-02 2013-03-12 Renesas Electronics Corporation Method of stacking semiconductor chips including forming an interconnect member and a through electrode
US9293446B2 (en) 2012-07-26 2016-03-22 Murata Manufacturing Co., Ltd. Low profile semiconductor module with metal film support
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JP2001135662A (en) * 1999-11-04 2001-05-18 Matsushita Electric Ind Co Ltd Semiconductor element and method for manufacturing semiconductor device
JP2002026244A (en) * 2000-07-12 2002-01-25 Matsushita Electric Ind Co Ltd Multilayer module and its manufacturing method

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