JP2002342295A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of the difficulty in high-speed communication between processors, when a multiprocessor system, especially an on-chip multiprocessor system for performing packet transfer processing in a network node device is increased in scaled up. SOLUTION: This multiprocessor system is provided with a plurality of processors 1-1 to 1-4 which are respectively equipped with at least one arithmetic unit and buses 1-8 to 1-10 for connecting those arithmetic units. In this case, not all the processor are connected to a single bus, but a small number of processors are connected to a plurality of buses, so that the processors connected to one and the same bus for rapid perform data exchange between the arithmetic units can be made, without using registers or memories. The processors connected to the different buses can perform the data exchange via a plurality of buses and a plurality of bridges 1-5 and 1-6, so that, the inter-process communication can be quickly performed, even in the large-scaled multiprocessor system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to an interprocessor communication system in an on-chip multiprocessor system for performing packet transfer processing in a network node device.

[0002]

2. Description of the Related Art Advances in semiconductor technology have made it possible to integrate many processors on one semiconductor. One advantage of integrating many processors on a single semiconductor is that a large bandwidth can be used for communication between processors, and a delay time required for communication between processors can be reduced. The following three methods are mainly considered as methods for performing communication between processors.

The first inter-processor communication method is a method using a shared storage area such as a shared register, a shared cache memory, and a main memory. When a certain processor writes data to the shared storage area, another processor sharing the storage area reads the data to perform communication. This method is generally and widely used in a multiprocessor system. For example, Japanese Patent Application Laid-Open Nos. 2-244252 and 6-35
840 and JP-A-7-152647. As an example of using a shared register, there is a method disclosed in Japanese Patent Application Laid-Open No. H10-78880.

The second inter-processor communication system is a system for directly transmitting and receiving data between processors. For example, Japanese Patent Application No. 11-348545 describes a method in which register files of respective processors are connected to each other using a bus, and register data is copied between register files.

[0005] The third inter-processor communication system is a system in which arithmetic units of the respective processors are directly connected. Generally, this method is not a communication method between processors,
Super scalar processor and VLIW (Very Long In
In a struction word) type processor, a plurality of computing units exchange data in the middle of computation. In this method, data can be exchanged between arithmetic units at high speed by directly connecting a plurality of arithmetic units in a processor or arithmetic units of different processors to a mesh.

When communication is performed between processors by using a shared storage area as in the first method, arbitration of accesses from a plurality of processors to the storage area is performed. In the case where the processor or the computing unit is directly connected as in the third method, it is assumed that the bus used for the connection can be accessed from a plurality of processors. Selects one of the processors requesting access, permits access to this processor, and denies access to other processors.

The second access arbitration method is a method in which a processor is operated at a fixed timing and a program is provided in advance so as not to cause contention. In this method, program code is rearranged in advance using a compiler, etc., so that program code that does not cause contention is given to the processor, and the processor executes the given program code at the timing assumed at the time of code rearrangement. By doing so, no access conflict occurs during execution. However, in this method, it is necessary to exactly match the operation timing assumed at the time of program rearrangement with the actual operation timing at the time of execution. And the processor hardware must be configured so that unpredictable execution disturbances do not occur. A technique disclosed in Japanese Patent Application No. 11-348545 is an example of a processor using this method.

[0008]

The first problem is that communication delays in the first and second inter-processor communication systems, particularly, the operation performed by a certain processor and the results are used. That is, the communication delay between the processors when the operation is performed by another processor is large. In the first method, it is necessary to temporarily write data in a storage area that can be accessed by both the transmitting processor and the receiving processor, so that the data calculated in the arithmetic unit of the transmitting processor is stored in the arithmetic unit of the receiving processor. Large delays occur until they arrive.

Also, in the second method, the transmitting processor must once write the operation result to the register file and transfer the result to the register file of the receiving processor. Occurs.

A second problem is that the number of processors and the number of arithmetic units cannot be increased in the third inter-processor communication system. In this method, it is necessary to connect the outputs of all the arithmetic units to the inputs of all the arithmetic units, so wiring of the number of processors and the square of the number of arithmetic units is required, and the number of connectable processors and arithmetic units Less is.

A third problem is that in the first and second communication systems between processors, it takes time to take over processing between processors. In the above-described method, data on a memory, data on a register, and data on an operation unit can be transferred between processors, but the contents of a status register and a program counter cannot be transferred between processors. Therefore, when processing is taken over between processors, the information in the status register is temporarily reflected in a memory or a normal register to carry out the processing, and the succeeding processor checks the contents of the memory or the normal register and renews the status register. Must be set.

The same applies to the program counter. When a certain processor branches a plurality of processes and takes over the process from each branch destination, the takeover source processor determines which branch is being processed. The information is temporarily reflected in a memory or a normal register to perform the takeover, and the processor that has taken over needs to check the contents of the memory or the normal register and branch the process again.

A fourth problem is that the first access arbitration method is not suitable for large-scale multiprocessing.
In this method, to grant access to one processor from access requests from all processors,
As the number of processors increases, the delay in determining access arbitration increases, and the physical distance from the processor to the access arbitration circuit increases, so the delay time between when a processor issues an access request and when communication starts is longer. Become. Therefore, there is a problem that as the number of processors increases, the communication speed between the processors decreases.

[0015] A fifth problem is that the first access arbitration method is not suitable for real-time processing. In this method, access arbitration is performed dynamically during execution, so that the processing time for each process cannot be guaranteed. Therefore, it is difficult to realize a process that requires very strict real-time performance, such as a packet scheduling process in the packet transfer process.

A sixth problem is that when the second access arbitration system is used, the execution efficiency of the program is reduced depending on the processing content. If the same processing is simply repeated, the execution efficiency of the program does not decrease even if the access time to the shared resource is fixed. However, when there are many branches in a program and various processes are performed according to the time, it is necessary to create a program code so that access to a shared resource does not conflict in all branch paths. As the number increases, the useless access waiting time increases.

Taking the packet transfer process as an example, the packet scheduling process is a repetitive process of the same process, so that even if this method is used, the processing efficiency does not decrease, but various types of packets are processed in the packet header process. In this case, the processing to be executed differs depending on the type of the packet, and the execution efficiency of the program may be reduced.

The present invention has been made in view of the above problems, and has been proposed in a multiprocessor system, particularly, an on-chip multiprocessor system for performing packet transfer processing in a network node device, which has a very large number of processors. It is another object of the present invention to speed up communication between processors and perform access arbitration that satisfies both program execution efficiency and real-time processing.

[0018]

In order to solve the first problem, in a multiprocessor system according to the present invention, in addition to the conventional interprocessor communication system, direct communication is performed between arithmetic units of respective processors. Communication path for
High-speed data exchange between arithmetic units.

In order to solve the second problem, a bus connection using one or a plurality of buses is used instead of connecting all the arithmetic units to a mesh. When one bus is used, when the number of processors increases, communication efficiency decreases due to bus congestion and an increase in the physical distance of the bus.
Therefore, when the number of processors increases, not all processors are connected to one bus, but a plurality of short buses are prepared and each processor is connected only to the nearest bus. Since communication is performed between processors connected to different buses, communication between a plurality of buses is enabled by connecting the buses using a bridge.

In order to solve the third problem, a communication path for directly communicating between the status register and the program counter of each processor is provided.

In order to solve the fourth problem, access arbitration is not performed by all processors for all shared resources, but only by processors sharing the same bus. The multiprocessor system has a plurality of buses, and the processor is connected only to the nearest bus. Therefore, processors sharing one bus are close to each other, and the number of processors is limited, so that access arbitration can be performed between these processors at high speed.

When the number of processors is increased, the number of buses is increased rather than the number of processors connected to one bus, so that access arbitration can be performed at high speed even in the case of performing large-scale multiprocessing. Can be. In the case of communication passing through a plurality of buses, data output from the processor is received by a bridge that passes once, and the bridge arbitrates access to the next bus and outputs data.

[0023] In order to solve the fifth and sixth problems, each processor is provided with an asynchronous operation corresponding to the first access arbitration scheme and an unpredictable execution disorder corresponding to the second access arbitration scheme. It is configured such that a synchronous operation in which the processing to be performed is prohibited can be selected. As an access control method for shared resources, dynamic arbitration is performed for a processor using the first access arbitration method, and the access request is always permitted for a processor using the second access arbitration method. I do.

That is, a program code is created so that accesses to the processor using the second access arbitration method do not conflict with each other, and the processor using the second access arbitration method is not accessed at the time of execution. For resources only, dynamically arbitrate access requests from processors using the first access arbitration scheme.

When implementing the packet transfer process on the multiprocessor system, the packet transfer process is divided into a plurality of small processes, and each process is fixedly assigned to the processor. Then, by selecting the operation of the processor according to the characteristics of each processing, that is, the processor in charge of packet header processing that performs various operations uses the first access arbitration method, and simple repetition with strong real-time characteristics is mainly used. By using the second access arbitration scheme, the processor in charge of the packet scheduling process satisfies both the processing efficiency and the real-time performance.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of a multiprocessor system according to the present invention. Referring to FIG. 1, the multiprocessor system according to the present embodiment includes a plurality of processors 1-1 to 1-4,
Data buses 1-8 to 1-10 for exchanging data between arithmetic units of a plurality of processors; bridges 1-5 to 1-6 for exchanging data between data buses; shared memory 1-7; Memory bus 1-1 connecting 1-7
1. Coprocessors 1-12-1-13.

The processor 1-1 includes a register file 1-1-1 for holding data, and one or more arithmetic units 1-1-1.
1-2-1-3, one or more memory units 1
-1-4, and the processors 1-2 to 1-3 have the same configuration. Although each processor has a mechanism required by a general processor such as a program counter and a status register, it is omitted from the configuration diagram because it has no direct relation to the inter-processor communication operation according to the present embodiment.

The data buses 1-8 to 1-10 are constituted by a plurality of channels so that a plurality of data can be simultaneously communicated in the bus, and each channel is a communication path for transferring data and its destination. Be composed. Memory bus 1-1
Reference numeral 1 denotes a communication path for transferring addresses and data. The co (child) processors 1-12 and 1-13 are (parent) processors 1-1 such as a floating-point arithmetic unit and a character string copy.
1-2 and 1-3-1-4, which perform processing by communicating with a processor or a memory using a data bus or a memory bus.

FIG. 2 shows an arithmetic unit 1-1-2 according to this embodiment.
FIG. 2 is a block diagram showing the structure of FIG. The arithmetic unit 1-1-2 controls an input circuit 1-1-9 for controlling data input from the data bus to the input register, an input register 1-1-5 for temporarily holding data fetched from the data bus, and supplies the arithmetic circuit. Selection circuits 1-1-6 to 1-1-7 for selecting data from an input register or a register file, an arithmetic circuit 1-1-8, and an output circuit 1-1 for controlling data output from the arithmetic circuit to the data bus. It consists of ten. All other arithmetic units have the same configuration.

Next, the operation of this embodiment will be described with reference to FIGS. The memory access operation of each processor in this embodiment is described in, for example, JP-A-2-244252, JP-A-6-35840, and JP-A-7-1526.
This is the same as the memory access operation in a general multiprocessor system as shown in JP-A-47-47 and the like.
Therefore, when communication is performed between the processors via the memory, the multiprocessor system according to the present embodiment performs communication in the same manner as a general multiprocessor system.

The multiprocessor system according to the present embodiment has a data bus for directly connecting arithmetic units. Therefore, an inter-processor communication system using a data bus will be described next. When a processor executes a normal operation instruction, the operation result output from the operation circuit is sent to the register file, but when an operation instruction accompanied by data output is executed, the operation result output is sent to the register file. At the same time, the data is output to the data bus through the output circuit. The output circuit selects a channel on the data bus to be output according to an instruction from the program, and outputs the data to the data bus together with the destination processor number or coprocessor number of the data specified by the program.

In the bridge, the destination of the data flowing on the data bus is checked, and if it is determined that the data bus through which the data flows and the data bus to which the destination is connected are the same, the data transfer processing is performed. Absent. Otherwise, transfer the data to the data bus which is the route to the destination.

The input circuit of each arithmetic unit monitors each channel in the connected data bus, and when it is determined that the destination of data flowing on the channel is its own processor, the data is taken in and input. After the data is stored in the register, the input register is set to a valid state. When a normal operation is performed in an arithmetic unit, data is obtained from a register file. When an operation involving data input is performed, data is obtained from an input register and the operation is performed. When the data in the input register is used, if the input register is in an invalid state, the operation is stopped and the operation waits until the input register changes to a valid state. When the input register changes to a valid state, the operation is restarted, and when the operation is completed, the input register is set to an invalid state.

Such an input register mechanism is necessary for synchronizing processing between processors, and prevents a processor receiving data from starting an operation before data arrives. As described in Japanese Patent Application No. 11-348545, when each processor operates at a fixed timing, such a mechanism for synchronization is unnecessary.

When the processor sends data to the coprocessor to outsource processing, the processor outputs data on the data bus in the same manner as the above-described operation, and the coprocessor receives data from the data bus and performs predetermined processing. Is performed. Then, the processing result is transmitted again to the processor which has requested the processing using the data bus. In a process in which the coprocessor needs to perform direct memory access, such as a character string transfer process on a memory, the coprocessor performs direct memory access using a memory bus.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the multiprocessor system according to the present invention. Referring to FIG. 3, the multiprocessor system according to the present embodiment includes a plurality of processors 2-1 to 2-4, data buses 2-8 to 2--4 for exchanging data among arithmetic units of the plurality of processors and between register files. 10. Bridges 2-5 to 2-6 for exchanging data between data buses, shared memory 2-7, and coprocessors 2-11 to 2-12.

The processor 2-1 has a register file 2-1-1 for holding data and one or more arithmetic units 2-1-1.
1-2 to 2-1-3, and processors 2-2 to 2-2.
-3 has the same configuration. Data bus 2-8 to 2-10
Is composed of a plurality of channels so that a plurality of data can be simultaneously communicated in a data bus, and each channel is composed of a communication path for transferring data and its destination. Further, this embodiment does not have a memory bus, and the shared memory 2-7 is connected using two channels in the data bus.

Since the configuration of each arithmetic unit is the same as that of the arithmetic unit in the first embodiment, the configuration diagram is omitted here.

Next, the operation of this embodiment will be described with reference to FIG. In the present embodiment, since the shared memory is connected using the data bus, the memory access operation is different from that of the first embodiment. When writing to a memory, an address to be written is set in one register on the register file, and data to be written is set in another register. Then, the destination is set to the address input of the shared memory, the register contents are output from the register where the address is set to one channel of the data bus, and the destination is set to the data input / output of the shared memory and the data is set from the register where the data is set. Output the register contents to another channel of the data bus.

When the shared memory receives these addresses and data from the data bus, it writes to the memory. When reading from the shared memory, the address to be read is set in one register in the register file, the destination is set to the address input of the shared memory,
The register contents are output from the register to one channel of the data bus. The shared memory receives the read address, reads the data, sets the destination as the requesting processor, and outputs the read data to one channel of the data bus. When the processor receives this data, it stores it in a predetermined register.

Next, an interprocessor communication system using a data bus will be described. Also in this embodiment, since the arithmetic units are connected using the data bus, it is possible to directly communicate between the arithmetic units as in the first embodiment,
The operation of the arithmetic unit and the bridge in this case is the same as in the first embodiment. Further, in this embodiment, since the register file is also connected to the data bus, the register data is output from the register file of one processor to the data bus, and the data is directly transferred to the register on the register file of another processor. It is possible to In this case, data of a plurality of registers can be transmitted and received simultaneously using a plurality of channels.

In this embodiment, it is also possible to receive the data output from the arithmetic unit by the register file, or to receive the data output from the register file by the arithmetic unit. Further, at the time of memory access, it is also possible to use not the register file but the input / output of the arithmetic unit at the time of address transmission or data transmission / reception. For example, when writing data to a memory, it is possible to directly output a write address calculated using an arithmetic unit to a data bus and output write data from a register file.

In this embodiment, when communication is performed using a register file, each register in the register file is provided with a valid state / invalid state by using the same configuration as the input register in the first embodiment. , It is possible to synchronize between processors. When each processor performs a synchronous operation at a fixed timing, such a mechanism for synchronization is unnecessary.

Register files, arithmetic units, shared memory,
The coprocessor need not be connected to all the channels on the data bus, but may be connected to a specific channel as shown in FIG. In this case, the degree of freedom of communication is reduced, but there is an effect of reducing the amount of hardware. This is the same in the following embodiments.

The communication between the processor and the coprocessor in this embodiment is the same as that in the first embodiment, but the communication between the coprocessor and the memory is performed using the data bus as described above.

FIG. 4 is a block diagram showing the configuration of a third embodiment of the multiprocessor system according to the present invention. Referring to FIG. 4, the multiprocessor system according to the present embodiment includes a plurality of processors 3-1 to 3-4, an arithmetic unit of the plurality of processors, and a data bus for exchanging data among register files, program counters, and status registers. 3-8 to 3-10, bridges 3-5 to 3-6 for exchanging data between data buses, and a shared memory 3-7.

The processor 3-1 has a register file 3-1-1 for holding data and one or more arithmetic units 3-1-1.
1-2, 3-1-3, program counter 3-1-4,
The processor 3-2 comprises a status register 3-1-5.
3-3 have the same configuration.

The data buses 1-8 to 1-10 are constituted by a plurality of channels so that a plurality of data can be simultaneously communicated in the bus, and each channel is a communication path for transferring data and its destination. Be composed. Further, this embodiment does not have a memory bus, and the shared memory 2-7 is connected using two or more channels in the data bus. Also in the present embodiment, the configuration of each arithmetic unit is the same as the configuration of the arithmetic unit in the first embodiment, and the configuration diagram is omitted. The feature of this embodiment is that the program counter 3-1-4 and the status register 3-1-5 are directly connected to the data bus.

Next, the operation of this embodiment will be described with reference to FIG. Since the memory access operation and the inter-processor communication operation in the present embodiment are the same as those in the second embodiment, they will not be described here. In this embodiment, the contents of the program counter and the status register can be transmitted and received between the processors, and the processing can be efficiently taken over between the processors. That is, when taking over processing between processors, the takeover source processor can send the contents of the program counter and status register as well as the contents of the registers on the register file to the takeover destination processor using the data bus, The takeover processor can resume the takeover process in exactly the same state as the final state of the takeover source processor.

When the processors have different contents of the program memory to perform different processes, the program counter is simply transferred because there is no address consistency between the takeover source and the processor and the takeover destination processor. Can not. In such a case, the takeover source processor calculates the execution start address of the takeover destination processor, stores it in a register in the register file, and transfers the contents of this register to the program counter of the takeover destination processor when the process is taken over. And send it.

FIG. 5 is a block diagram showing the configuration of a fourth embodiment of the multiprocessor system according to the present invention. Referring to FIG. 5, the multiprocessor system according to the present embodiment differs from the multiprocessor system according to the second embodiment in that coprocessors 4-15 to 4-16, processors 4-1 to 4-2, and a coprocessor 4-15. Arbiter 4-11 for arbitrating data bus access, processor 4-
1-4, coprocessor 4-16 and shared memory 4
Arbiter 4-1 that arbitrates -7 data bus access
2, a time table 4-13 describing the data transfer operation of the bridge 4-5 and a time table 4-14 describing the data transfer operation of the bridge 4-6 are added.

The processor 4-1 has an operation selection register 4-1-4, and the same applies to the processors 4-2 to 4-4. Since the configuration of each arithmetic unit is the same as the configuration of the arithmetic unit in the first embodiment, the configuration diagram is omitted here.

In this embodiment, each processor selects the dynamic scheduling operation or the static scheduling operation by using the operation selection register. The static scheduling operation means that the processor operates at a fixed timing, prohibits a process that causes unpredictable execution disturbance to the processor, and causes each processor to repeatedly execute a process according to a preset fixed-length cycle. That is. Therefore, it is possible to predict what data bus access will be performed by the processor at what time, and it is possible to adjust the program code so that the access from each processor does not conflict by rearranging the program code optimally. .

On the other hand, in the dynamic scheduling operation, each processor does not have a fixed-length operation cycle, and processing that causes unpredictable execution disturbance is not prohibited. For this reason, it is impossible to predict the data bus access operation of the processor in advance, and access arbitration must be performed dynamically at the time of program execution.

FIG. 6 shows an example of the configuration of the time table 4-13. The time table defines whether transfer of data received from each channel of each data bus connected to the bridge is possible or not, and defines whether transfer is possible for each time according to the destination of the received data. In the example of FIG. 6, at time 0, the data input from the channel 1 of the data bus 4-8 is permitted to be output to the processor 1, and at time 1
Allows the data input from the channel n of the data bus 4-8 to be output to the shared memory, and outputs the data input from the channel 1 of the data bus 4-9 to the shared memory at time 2. This indicates that all transfer processing in other bridges is not permitted.

The bridge and the processor performing the static scheduling operation operate in synchronization with each other, and the bridge periodically performs the transfer process by repeatedly referring to the time table.

Next, the operation of this embodiment will be described with reference to FIGS. The inter-processor communication operation in this embodiment is the same as that in the second embodiment, and the operation of arbitrating access to the data bus will be described in detail below. First, an access arbitration operation in communication within the same data bus will be described. When outputting data to the data bus, the processor notifies the arbiter of the destination and the channel to be used, requests permission to use the channel, and outputs the data after obtaining the permission. If the use permission is not given, the data output is stopped, and the request is repeated until the use permission is given. The arbiter receives a use permission request from each processor, determines a processor to permit data output for each channel, and transmits the result to each processor.

In the processor of the static scheduling operation, the contention of the access of the data bus is avoided by appropriately rearranging the program code before execution. In the processor of the dynamic scheduling operation, the access arbitration is dynamically performed during the execution of the program. Need to do. Therefore, in the arbiter, when a plurality of processors request the use permission of the same channel, first, the use permission is given to the processor of the static scheduling operation, and if there is no request from the processor of the static scheduling operation, One processor is selected from the processors and the use permission is given.

The same applies to the data output operation from the coprocessor and the shared memory. However, at Arbiter,
When outputting data from the coprocessor or the shared memory to the processor performing the dynamic scheduling operation, make sure that the data output does not interfere with the data output from the processor performing the static scheduling operation. Priority is given to the channel use request from the processor performing the static scheduling operation over the channel use request from the processor.

On the other hand, when data is output from the coprocessor or the shared memory to the processor performing the static scheduling operation, the data output is made smaller than the channel use request from the processor performing the dynamic static scheduling operation. Prioritize.

Next, an access arbitration operation in communication over a bridge will be described. Also in this case, the operation of the processor is the same as described above, and the operation of the arbiter is different. If the arbiter has a channel use permission request for another data bus, the arbiter queries the bridge for a transferable destination at the current time, and the bridge refers to the time table for the corresponding channel of the bus to which the arbiter is connected. Answer the forwarding destination. Then, the arbiter grants the request for a channel use permission request having the same destination as the answered destination, and otherwise, all communication over the bridge is disallowed and communication on the data bus is prohibited. Grant channel use permission.

However, the communication of the processors performing the static scheduling operation always has priority, and if there is a channel use permission request from these processors, the channel use request of the processor performing the dynamic scheduling operation passes through the bridge. Regardless of whether or not to do so, all are disallowed.

When the bridge receives data for communication over the bridge, it outputs the data to the data bus which is a route to the destination of the data. Therefore, the arbiter that controls this data bus is permitted to use the channel. And outputs the data to this data bus. The arbiter always permits a channel use request from the bridge so that data does not stay in the bridge. Therefore, in the time table of each bridge, it is necessary to set so that the data bus does not compete between the bridges. In the processor performing the static scheduling operation, the program must be set so that the communication between the bridges is not hindered. You need to write code.

As described above, when the processor obtains the channel use permission from the nearest arbiter, the channel is always reserved in the subsequent communication path by setting the time table, so that the destination of the data transfer is not interrupted. Arrive up to. Therefore, in a processor that performs static scheduling, it is necessary to create a program so that data does not conflict on all data buses in communication, not only on the connected data bus, and set a time table according to the result.

On the other hand, with regard to the processor performing the dynamic scheduling operation, the access control is performed by the arbiter, so that the program code can be freely created. However, in order to perform communication beyond the bridge, a communication path is set at an appropriate time in the time table so as not to interrupt communication of the processor performing the static scheduling operation. It is necessary to wait for communication until the set time comes. However, if there is enough time table time, it is possible to reduce communication waiting time by setting communication paths at a plurality of times.

An arbiter is not required for a data bus connected only to a bridge, such as the data bus 4-9, since no conflict occurs.

FIG. 7 is a block diagram showing the configuration of a fifth embodiment of the multiprocessor system according to the present invention. Referring to FIG. 5, the multiprocessor system according to the present embodiment has substantially the same configuration as the multiprocessor system according to the fourth embodiment, except that temporary buffers 5-13 to 5-14 are provided instead of the time tables. different.

Next, the operation of this embodiment will be described with reference to FIG. In the present embodiment, the access arbitration operation in the same data bus is the same as that of the fourth embodiment, and the data is temporarily stored in the bridge, so that the control by the time table is not required. Different from the example. That is, in the fourth embodiment, since the access control for all the routes is performed using the time table in the communication beyond the bridge, the data permitted to be transmitted by the first-stage arbiter does not stay in the middle bridge. In this embodiment, if even the first-stage data bus is available, data transmission is started. If the data bus is unavailable in the middle of the communication path, the data bus can be used in the immediately preceding bridge. Let the data wait until it becomes. Therefore, this embodiment has an advantage that the time required for the processor performing the dynamic scheduling operation to wait for the start of communication is reduced, but has a disadvantage that the bridge becomes complicated.

Since the data of the processor performing the static scheduling operation is not allowed to stay in the bridge, the priority is set for the data to be transferred, and the data from the processor performing the static scheduling operation and the data addressed to this processor are determined. Is
The arbiter is controlled so that no queuing occurs as priority data, and data from a processor performing a dynamic scheduling operation and data addressed to this processor are given non-priority.

Next, the operation of the arbiter and the bridge regarding the access arbitration operation in communication via the bridge will be described. The arbiter always grants a channel use permission request for priority data, if any. If there is no priority data, all bridges connected to the arbiter are inquired about the free space of the temporary buffer, and one non-priority data is selected from non-priority data passing through a bridge having a free capacity to use a channel. Give permission. If the channel use permission is not given to the non-priority data passing through the bridge, the channel use permission is given to the non-priority communication in the data bus.

When the bridge receives the data of the communication over the bridge, it requests the arbiter that controls the data bus to which the data is output, to grant the channel use permission. If the received data is the priority data, the arbiter always grants the use permission, so that the bridge performs the transfer processing without arriving the arriving data. If the arriving data is non-priority data and the arbiter grants use permission, and there is no priority data to be output to the same data bus or non-priority data in the temporary buffer, the non-priority data is transferred. If not, this data is stored in a temporary buffer.

When a plurality of non-priority data are output to the same data bus, a transfer process is performed on one of the non-priority data, and all the remaining non-priority data are stored in a temporary buffer. The non-priority data stored in the temporary buffer is extracted from the temporary buffer and the transfer processing is performed if there is no priority data with the same data bus as the output destination and permission is obtained from the arbiter that controls the data bus. Done.

FIG. 8 is a block diagram showing the configuration of a sixth embodiment of the multiprocessor system according to the present invention. Referring to FIG. 8, the multiprocessor system according to the present embodiment includes a plurality of processors 6-1 to 6-4, a shared memory 6-8 shared by all processors, and a shared memory 6 from processors 6-1 and 6-2. Memory bus 6-3 for accessing -8, processors 6-1 and 6-2
A memory control circuit 6-6 for arbitrating access to the shared memory 6-8 between the processor 6-3 and the processor 6-3, and exchanging data between arithmetic units of the processors 6-3 and 6-4 and between register files. Data bus 6-7, processor 6
It is composed of a shared memory 6-9 shared by 3 and 6-4.

The processor 6-1 includes a register file 6-1-1 for holding data and one or more arithmetic units 6-1-1.
1-2 to 6-1-3, one or a plurality of memory units 6-1-4, and the processor 1-2 has the same configuration. The processor 6-3 includes a register file 6-3-1 for holding data and one or more arithmetic units 6-3-.
2 to 6-3-3, and the processor 6-4 has the same configuration.

Next, the operation of this embodiment will be described with reference to FIG. The processors 6-1 and 6-2 perform a dynamic scheduling operation, and dynamically control access to the shared memory 6-8. These processors communicate only via the shared memory 6-8, which is similar to the operation of a general multiprocessor system sharing the memory.

On the other hand, the processors 6-3 and 6-4 perform the same operation as the inter-processor communication in the second embodiment. That is, these processors communicate with each other using the data bus between arithmetic units and register files, and also communicate with the shared memory 6-8 and the shared memory 6-9. Further, since these processors perform a static scheduling operation, they do not perform access control such as for the data bus 6-7.

Communication between the processors 6-1 and 6-2 and the processors 6-3 and 6-4 is performed using the shared memory 6-8. The memory accesses from the processors 6-1 and 6-2 and the empty memory accesses from the processors 6-3 and 6-3 are arbitrated by the memory control circuit 6-6, and the processors 6-3 and 6-6 performing the dynamic scheduling operation. 4 is controlled so that the access from 4 is always given priority.

This embodiment combines the first embodiment and the second embodiment, and has a configuration particularly specialized in packet transfer processing. That is, in the packet header processing, since there is relatively little communication between the processors and various processing is performed in each processor, the processors 6-1 and 6-2 are processed with the same configuration as a general multiprocessor system. In the packet scheduling process and the like, communication between the processors is frequent and strict real-time processing is required. Therefore, the processors 6-3 and 6-4 have the same configuration as in the second embodiment to perform the static scheduling operation. .

[0079]

The first effect of the present invention is that, in a multiprocessor system, particularly in an on-chip multiprocessor system for performing packet transfer processing in a network node device, direct communication is performed between arithmetic units of respective processors. Communication with a very short delay time between processors can be realized by providing a communication path for communication.

The second effect of the present invention is that all processors
Instead of connecting to buses, prepare multiple short buses and connect each processor only to the nearest bus, and connect the buses using bridges to communicate via multiple buses. By making it possible, a high communication speed can be realized even when a large number of processors and arithmetic units are used.

A third effect of the present invention is that, by directly communicating between a register file, a status register, and a program counter of each processor, processing between processors can be efficiently taken over. .

A fourth advantage of the present invention is that dynamic access arbitration is performed only between processors sharing the same bus, and communication across a bridge is statically scheduled according to a time table, or a communication within a bridge is performed. By queuing in a temporary buffer, access arbitration can be performed at high speed in large-scale multiprocessing.

A fifth effect of the present invention is that, by configuring each processor so that a dynamic scheduling operation or a static scheduling operation can be selected, the operation of the processor is selected according to the characteristics of the processing, and the efficiency of the processing is improved. And real-time performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a computing unit in FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is a chart showing a configuration example of a time table in the embodiment of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a sixth embodiment of the present invention.

[Explanation of symbols]

1-1 to 1-4, 2-1 to 2-4, 3-1 to 3-4, 4
-1 to 4-4, 5-1 to 5-4, 6-1 to 6-4
Processor 1-5, 1-6, 2-5, 2-6, 3-5, 3-6, 4
-5,4-6 bridge 1-7,2-7,3-7,4-7,5-7,6-8,6
-9 Shared memory 1-8 to 1-10, 2-8 to 2-10, 3-8 to 3-1
0,4-8 to 4-10,5-8 to 5-10,6,5,6
-7 data bus 1-11 memory bus 1-12, 1-13, 2-11, 12-12, 4-15,
4-16 Coprocessor 4-11, 4-12, 5-11, 5-12 Arbiter 4-13, 4-14 Time Table

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/16 640 G06F 15/16 640B 15/177 682 15/177 682G F-term (Reference) 5B033 AA03 AA14 DD09 5B045 BB12 BB14 BB32 BB34 BB47 CC06 DD01 EE03 EE07 EE12 EE22 GG01 GG09 5B061 BB01 BC01 FF07 GG01 GG11 RR05 5B077 BA02 BA06

Claims (11)

[Claims] 1. A multiprocessor system having a large number of processors, comprising a plurality of processors having one or a plurality of arithmetic units, and a plurality of buses connecting the plurality of arithmetic units. A multiprocessor system characterized by performing direct communication between computing units and simultaneously performing a plurality of communications between computing units using the bus. 2. The multiprocessor system according to claim 1, further comprising: a bridge connecting the plurality of buses to each other, wherein a part of the plurality of arithmetic units is connected to each of the plurality of buses. The operation units connected to the same bus perform direct communication via the bus, and the operation units connected to different buses perform communication via the plurality of buses and the plurality of bridges. And a multiprocessor system. 3. The multiprocessor system according to claim 1, wherein the multiprocessor system has one or more buses for connecting register files of each of the processors.
A multiprocessor system, wherein communication is performed between the register files of different processors or between the register file and the arithmetic unit. 4. The multiprocessor system according to claim 1, further comprising one or a plurality of coprocessors for assisting the processor, and one or a plurality of memories, and By connecting a coprocessor and a memory, communication is performed between the arithmetic unit and the coprocessor or the memory, between the register file and the coprocessor or the memory, or between the coprocessor and the memory. Multiprocessor system. 5. The multiprocessor system according to claim 1, further comprising a status register indicating data arrival corresponding to said operation unit, wherein data arrives at said operation unit from said bus. In this case, the status register of the operation unit is set to true, and after the operation unit performs an operation using the data arriving from the bus, the status register of the operation unit is set to false, and the operation unit When performing an operation using data arriving from the bus, if data from the bus has not arrived, that is, if the status register is false, wait for the operation until the status register becomes true. Characteristic multiprocessor system. 6. The multiprocessor system according to claim 1, wherein a state register such as a flag register and a program counter of each of said processors are connected to said bus, so that arithmetic operations of different processors are performed. A multiprocessor system for performing communication between a device, a register file, a status register, and a program counter. 7. The multiprocessor system according to claim 1, wherein the register files of each of the processors are connected using a bus, and the contents of the registers are directly copied between the register files. Communication between processors, and by connecting a status register such as a flag register and a program counter of each of the processors to the bus, an arithmetic unit, a register file, a status register, and a program counter of different processors can be connected. A multiprocessor system for performing communication. 8. The multiprocessor system according to claim 2, wherein an arbiter for arbitrating a bus use request from an arithmetic unit, a register file, a coprocessor, or a memory connected to the bus is provided. Each bus has a time table for instructing a data transfer operation at each time, and a time table for instructing a data transfer operation at each time.In communication not exceeding the bridge, arbitration of a bus use request is performed by the arbiter in each bus. In a multiprocessor system, the arbiter permits only communication on a route permitted by the time table at the time of communication exceeding the bridge. 9. The multiprocessor system according to claim 2, wherein an arbiter for arbitrating a bus use request from an arithmetic unit, a register file, a coprocessor, or a memory connected to the bus is provided. Each bus has a temporary buffer for temporarily holding data that cannot be output from the bridge, and arbitration of a bus use request is performed by the arbiter in each bus in communication that does not exceed the bridge. In the communication exceeding the bridge, if the next bus on the path is available, the data is transmitted to the next bridge, and if the next bus on the path is unavailable, the bus is usable. A multiprocessor system characterized in that data is held in a bridge until the data is stored. 10. The multiprocessor system according to claim 8, wherein the processor is a processor that operates at a fixed timing and a processor that operates at a dynamic timing, and the arbiter is a fixed processor. A multiprocessor system characterized in that a bus use permission is always given to a communication performed by a processor operating at a timing, prior to a communication of another processor. 11. The multiprocessor system according to claim 9, wherein the processor is a processor that operates at a fixed timing and a processor that operates at a dynamic timing, and the arbiter is a fixed processor. The communication to the processor operating at the timing is always given a bus use permission in preference to the communication of the other processor, and the bridge gives priority to the data to the processor over the data held in the bridge. A multiprocessor system characterized by outputting to a bus.