WO2007049543A1

WO2007049543A1 - Calculating apparatus

Info

Publication number: WO2007049543A1
Application number: PCT/JP2006/321033
Authority: WO
Inventors: Yasunori Sakakibara; Shinichi Iwamoto; Takayuki Sugawara
Original assignee: Sonac Incorporated
Priority date: 2005-10-27
Filing date: 2006-10-23
Publication date: 2007-05-03
Also published as: JP4017005B2; JP2007122337A

Abstract

A calculating apparatus wherein processing parts, which executes application programs, do not need to execute any processings other than the application programs, such as a task management, and further can flexibly cope with any changes in the contents of various processings after a designing. The calculating apparatus comprises a control means that reads and executes a program, thereby assigning, based on the statuses of a plurality of processing means held by a status notifying means, tasks constituting the application programs to the respective processing means; the plurality of processing means that execute the respective tasks assigned by the control means and output the statuses related to the executions of the tasks; and the status notifying means that holds the statuses outputted by the processing means.

Description

Specification

Arithmetic unit

Technical field

[0001] The present invention relates to an arithmetic device including a plurality of processing units that execute a program.

Background art

[0002] Various methods have been proposed and implemented in order to execute processing according to the purpose of data at high speed. For example, Non-Patent Document 1 describes a multiprocessor system equipped with a plurality of processors. FIG. 8 is a configuration diagram of the multiprocessor system described in Non-Patent Document 1, in which a plurality of processors and memories are connected via a bus. According to Non-Patent Document 1, a plurality of processors share memory with one operating system, and a program (hereinafter referred to as an application program) according to the operating system capability processing purpose (Non-Patent Document 1). , It is broken down into threads or processes) and assigned to each processor.

That is, each processor executes both the operating system and each task of the application program, and the entire execution time of the processor cannot be allocated to the execution of the application program, and memory is not allocated. In order to share, the operation of the operating system may be affected by the execution of the application program.

[0004] For this reason, Patent Document 1 describes a configuration that reduces overhead such as task management and scheduling in each processor. FIG. ₉ is a configuration diagram of the multiprocessor system described in Patent Document IV. In addition to the configuration of FIG. 8, the state management unit is connected to a plurality of processors. According to Patent Document 1, the state management unit manages the free state of each processor and notifies each processor, and a processor in which a new task has occurred causes the other free state processor to execute the task. A new task is started immediately. According to Patent Document 1, the state management unit is realized by a combinational circuit.

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-86921

Non-Patent Document 1: "Interface Extra Number Microprocessor 'Introduction to Architecture", CQ Publishing , August 2004, p. 231 -p. 233

Disclosure of the invention

[0006] As described above, in the configuration in which the operating system performs task assignment processing to a plurality of processors, the execution time of the application program decreases, and the operation of the application program affects the operation of the operating system. There is a problem that can be given. For example, if the operating system is destroyed, the system will stop completely.

[0007] On the other hand, in the configuration described in Patent Document 1, the state management unit is a hardware block, and not all the management functions of the multiple processors can be realized! This part needs to be executed by the processor, leading to a reduction in the execution time of the application program. For example, in Patent Document 1, it is the processor itself in which a new task has occurred that causes a free processor to execute a new task. In addition, it is difficult to cope with changes in the processing contents of the state management unit after designing hardware blocks.

[0008] Therefore, the present invention solves the above-described problem, and the processing unit that executes the application program does not need to execute processing other than the application program such as task management. The purpose is to provide a computing device that can flexibly cope with changes in content.

[0009] According to the arithmetic device of the present invention,

By reading and executing the program for the control means, the control means for assigning the tasks constituting the application program to each processing means based on the status of each processing means held by the status notification means, and the control means It is characterized by having a plurality of processing means for executing the assigned task and outputting a state relating to the execution of the task, and a state notifying means for maintaining the state output by the processing means.

[0010] According to another embodiment of the arithmetic device of the present invention,

It is also preferable to have a first storage means used only by the control means and a second storage means used by the control means and the processing means.

[0011] Further, according to another embodiment of the arithmetic device of the present invention, The control means allocates the area of the second storage means and the hardware resource for input / output to the requested processing means based on the request from the processing means, and the processing means is the first assigned the control means power. It is also preferable to access only the storage area of 2 and Z or the hard resource for I / O.

Furthermore, according to another embodiment of the arithmetic device of the present invention,

The control means and the first storage means are connected to the first bus, the plurality of processing means and the second storage means are connected to the second bus, the first bus and the second bus It is also preferable to have bus conversion means for connecting the bus and preventing access from the processing means to the first storage means.

The control means and the first storage means are connected to the first bus, the plurality of processing means are connected to the second bus, and the second storage means is connected to the first node and the second bus. It is also preferable that they are connected.

[0014] By realizing the operation of the control means by a program, the operation of the control means can be easily changed, and it is possible to easily cope with a change in the processing contents. In addition, it is difficult for a hardware block by a program, and even a complicated control operation can be realized. Furthermore, the processing means does not need to perform tasks other than task management and execution of the application program, thereby improving the execution speed.

[0015] In addition, the control means manages access to the storage means and hardware resources for input / output by the processing means, thereby preventing problems caused by a plurality of processing means accessing the same resource. Can do. Furthermore, by separating the first storage means used by the control means from the second storage means that can be accessed by the processing means etc., the operation of the processing means is prevented from affecting the operation of the control means. Can do.

Brief Description of Drawings

FIG. 1 is a block diagram of a first embodiment of an arithmetic device according to the present invention.

FIG. 2 is a block diagram of a second embodiment of the arithmetic device according to the present invention.

FIG. 3 is a block diagram of a third embodiment of the arithmetic device according to the present invention.

FIG. 4 is a diagram illustrating a relationship between an application program executed by a processing unit and a task.

FIG. 5 is a process flow diagram of task management in the control unit.

FIG. 6 is a process flow diagram of task switching by the control unit. FIG. 7 is a processing flowchart of memory management in a control unit.

FIG. 8 is a configuration diagram of a conventional multiprocessor system.

FIG. 9 is another configuration diagram of a multiprocessor system according to the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiment.

FIG. 1 is a block diagram of a first embodiment of an arithmetic device according to the present invention. According to FIG. 1, the arithmetic device includes a control unit 1, a nonvolatile memory 2, a memory 3, a plurality of processing units 4, a shared memory 5, and a status notification unit 6. The control unit 1, the nonvolatile memory 2, the memory 3, each processing unit 4, and the shared memory 5 are connected to each other via a bus 8. Each processing unit 4 and the status notification unit 6 are connected by a line 71, and the status notification unit 6 and the control unit 1 are connected by a line 72.

The control unit 1 is, for example, a processor having a RISC (Reduced Instruction Set Computer) core and executing a control unit program stored in the non-volatile memory 2 and managing tasks of application programs. To determine the processing unit 4 to execute each task based on the status of each processing unit 4 held by the status notification unit 6, and execute the task to the determined processing unit 4 via the bus 8. Controls the loading of application programs. It also manages shared memory and hardware resources for external input / output (not shown).

The processing unit 4 is a processor that executes an application program. Here, the application program is a program for executing a desired purpose such as image data processing and communication data processing, as described above. The application program is executed by the control unit 1 and the application by the processing unit 4. It is clearly distinguished from the control unit program, which is a program that implements various control processes for executing the Chillon program. The type of processor used in the processing unit 4 is an array in which RISC cores or a plurality of processor elements are arranged in a matrix, and the processing contents in the processor elements and the connection configuration between the processor elements are changed according to the program to be executed. The type, such as the type, is arbitrary. For example, the processing unit 4 notifies the status of the task execution status in the processing unit 4 such as a free state, a processing state, and a suspended state through a line 71. Notify Part 6. A detailed identifier is assigned to each state as necessary, and the processing unit 4 notifies the state notification unit 6 of the detailed identifier together with the state. The detailed identifier will be described later.

The non-volatile memory 2 is a non-volatile memory storing a control unit program, and the processing unit 4 does not access it. Non-volatile memory includes ROM, EEPROM, flash memory, etc. If a rewritable memory such as flash memory is used, the control program can be changed easily.

The memory 3 is a readable / writable memory used as an area for storing various data when the control unit 1 executes the control unit program, and the processing unit 4 does not access it.

The shared memory 5 is a readable / writable memory that stores an application program executed by the processing unit 4 and is also used as an area for storing various data when the application program is executed. Can also be used.

[0024] The status notification unit 6 holds the status of the processing unit 4 output to the line 71 by the processing unit 4 together with the detailed identifier. The control unit 1 can access the status notification unit 6 through the line 72, and recognizes the status and detailed identifier of the processing unit 4 by accessing the status notification unit 6. It is also possible to adopt a configuration in which the status notification unit 6 issues an interrupt to the control unit 1 when the status of the processing unit 4 changes. In addition, the status notification unit 6 is also connected to the bus 8, and the signal transmission / reception between the control unit 1 and the status notification unit 6 is performed by the bus 8, or only the interrupt notification to the processing unit 4 is performed on the line 72. It is also possible to adopt a configuration in which 1 checks the status of the processing unit 4 to the status notification unit 6 through the bus 8 when an interrupt occurs.

FIG. 4 is a diagram showing the relationship between application programs executed by the processing unit 4 and tasks. Part of the processing of the application program is called a task, and the application program consists of multiple tasks. In Fig. 4, task A is executed first, and task B or task C is selectively executed according to the end result of task A. Task D is executed after task B or C ends, and tasks E, F, and G are executed after task D ends. Tasks E, F and G can be executed simultaneously or one by one. In any case, task H will be executed after all tasks E, F, and G are finished.

[0026] As described above, only one task constituting the application program is executed. In some cases, multiple tasks are executed at the same time, and the amount of processing for each task is different.

[0027] How to set a task is a design matter by a coniler or control means, but one or more basic blocks can be set as one task. A basic block is a unit of a control flow graph. There is only one instruction to be executed first and one instruction to be executed last, and it is possible to branch to another basic block without going through the instruction to be executed last. The instruction power to be executed first without stopping can be executed in a straight line up to the instruction to be executed last, and is normally recognized by the compiler in the process.

[0028] The control unit 1 recognizes the tasks constituting the application program and adds the recognized tasks to the task queue. As a method for adding tasks to the task queue in the control unit 1, for example, a task table is provided in the application program, and the control unit 1 reads the task table included in the application program, and all the tasks constituting the application program are read. There is a way to add to the task queue in advance. In this case, since all tasks can be recognized in advance, task scheduling described later can be performed effectively. Also, it reads the application program entry task, that is, the task to be executed first, recognizes the task that may be executed next to the entry task, adds it to the task queue, and executes it when the task ends. When a task is finalized, there is a method of repeatedly adding a task that may be executed next to the finalized task to the task queue and deleting a task that no longer needs to be executed from the task queue. In this case, the application program has a structure capable of recognizing each task as if it contains information indicating the position of each task in the shared memory.

[0029] In parallel with the addition of the task to the task queue, the control unit 1 performs task management and input / output management with respect to the shared memory and the outside so that the plurality of processing units 4 execute the application program. Task management is classified into task assignment and task switching. Each of these controls is realized by a control unit program.

[0030] Task assignment means control processing for grasping the processing amount of a task in the task queue, determining the processing unit 4 to execute the task, and causing the determined processing unit 4 to execute the task. At this time, in addition to assigning one task to one processing unit 4, the processing amount of the task is large. In such a case, one task can be divided and assigned to a plurality of processing units 4. For example, when a task is composed of a plurality of basic blocks, by including information indicating the basic block in the task, the control unit 1 can easily divide the task into a plurality of processing units 4. Can be executed. The control unit 1 notifies the processing unit 4 determined by the bus 8 of the task to be processed in order to cause the determined processing unit 4 to execute the assigned task.

Next, task management processing in the control unit 1 will be described using the application program of FIG. 4 as an example. The control unit 1 first assigns and executes task A to an arbitrary processing unit 4. The control unit 1 can execute the task A by writing the task A to be executed in the processing unit 4, or the processing unit 4 can specify the address of the shared memory 5 in which the part corresponding to the task A of the application program is stored. This can be done by notifying the processing unit 4 and acquiring the necessary application program from the shared memory 5.

[0032] When the processing unit 4 executing the task A finishes the execution of the task A, the processing unit 4 changes the state from the processing state to the empty state, and sets the detailed identifier # 1 or # 2 in the processing result. Outputs accordingly. The control unit 1 recognizes the end of processing in the processing unit 4 executing the task A through the status notification unit 6, and the force task C whose task to be executed next is the task B by the value of the detailed identifier. Recognize whether or not there is a task to be executed by assigning it to the processing unit 4 that is in a free state. Note that task B or C, which is the next task after task A, has already been added to the task queue by any of the methods described above. Therefore, when task A is executed, When 4 exists, it is possible to assign tasks B and C in advance to the processing unit 4 that is free, and load the assigned processing unit 4 in advance to the corresponding part of the application program. When it is loaded in advance, the control unit 1 loads the next task to be executed when the execution of the task A is finished, and gives the execution start trigger to the processing unit 4.

[0033] In addition, when task D is executed and the state power of processing unit 4 is changed from the processing state to the free state, and there are three or more processing units 4 that are free at that time Assigns tasks E, F, and G to each of the three processing units 4 and executes them. If there are two or less, only a part of the tasks, for example, only task E is assigned and executed, and the processing unit being processed Each time 4 changes to a free state, the remaining tasks are executed. Finally, task H is executed when execution of tasks E, F, and G is completed.

FIG. 5 is a process flow diagram of task management in the control unit 1. The control unit 1 grasps the necessary resources for the tasks existing in the task queue (S51), reads the status of each processing unit 4 held by the status notification unit 6 (S52), and exists in the task queue according to the scheduling rule. Among the tasks, the task that can be assigned to the processing unit 4 and the processing unit 4 that is the assignment destination, that is, the task execution schedule is determined (S53). Subsequently, when the execution-target processing unit 4 is ready to be executed by the execution-target processing unit 4, the task assigned to the processing unit 1 is executed. (S54)

[0035] As described above, the control unit 1 performs task execution control on the processing unit 4 by writing the task portion of the application program to be executed in the processing unit 4, as described above. It is also possible to notify the processing unit 4 of the address of the shared memory 5 in which the necessary application program is stored, and the processing unit 4 acquires the necessary application program from the shared memory 5. The control unit 1 can also divide a task and cause a plurality of processing units 4 to execute it.

FIG. 6 is a process flow diagram of task switching by the control unit 1. For simplicity, the state notification unit 6 that holds various states output by the processing unit 4 is omitted from FIG. When the high-priority task needs to be executed and the processing unit 4 is not available, the control unit 1 issues a suspension request to the processing unit 4 executing the low-priority task. (S61). Upon receiving the suspension request, the processing unit 4 saves the content, which is information necessary for restarting the task currently being executed, in the shared memory 5, interrupts the processing, and interrupts the status notification unit 6 via the line 71. State is output (S62).

[0037] The control unit 1 confirms the interruption of the process via the status notification unit 6, and then the processing unit that has issued the interruption request.

4 is instructed to execute the high priority task that has occurred. The processing unit 4 instructed to start starts processing the high priority task, and outputs an empty state to the state notification unit 6 through the line 71 when the execution is completed (S63). After confirming the end of processing via the status notification unit 6, the control unit 1 issues a task restart instruction to the processing unit 4, and the processing unit 4 that has received the task restart instruction reads the shared memory 5 force context, Is resumed (S64). [0038] It should be noted that the interruption request made by the control unit 1 includes information specifying the storage location of the context, or the processing unit 4 that interrupted the processing of the low-priority task, the status location stored by the processing unit 4 6 is notified to the control unit 1 and the control unit 1 notifies the processing unit 4 of the location of the context that is saved in response to the restart instruction. The processing unit 4 for restarting the task can be different.

[0039] There are various methods for how the control unit 1 determines the priority of each task. The task that has read the power application program and found it first is given a higher priority. There is a way. For example, in the application program shown in FIG. 4, when tasks E, F, and G are read in this order, priorities are assigned in the order of tasks E, F, and G. In this case, when compiling the application program, the compiler can recognize the number of operation data, the number of loops, etc., and can prioritize at the compilation stage.

There is also a method of increasing the priority as the processing amount of the task increases. For example, in the application program shown in Fig. 4, when task F has twice the processing amount of tasks E and G and there are two processing units 4, task F and task E are first assigned to processing unit 4. Instead of allocating task F and task G to processing unit 4 and then executing them, first divide task F into two processing units 4 and then execute tasks E and G.

[0041] Further, in the arithmetic device according to the present invention, by using a plurality of processing units 4, the ability to execute a plurality of application programs at the same time, the priority can be determined in units of application programs. Of course it is possible.

FIG. 7 is a process flow diagram of shared memory management in the control unit 1. Note that I / O management is the same by simply replacing the memory with hardware resources for I / O. Memory and I / O management manages access to hardware resources (not shown) for input / output to / from shared memory 5 and external devices (not shown). This is necessary in order to prevent harmful effects caused by accessing the data, for example, the loss of data caused by one processing unit 4 writing other data at the same position as the data written by another processing unit 4.

[0043] The control unit 1 manages the allocation area of the shared memory 5 to each processing unit 4, and from the processing unit 4 When there is a memory request via the status notification unit 6, the allocation status of the shared memory 5 is confirmed (S71), and the area requested from the unallocated area is allocated to the processing unit 4 that made the memory request. Hit (S72). The processing unit 4 that has received the allocation of the area of the shared memory 5 and the allocation of the hardware resource for Z or I / O accesses only the area or the hardware resource, and accesses the other area or the hardware resource. do not do. When the processing unit 4 finishes using the allocated memory area, the processing unit 4 notifies the control unit 1 of a memory release request via the status notification unit 6.

FIG. 2 is a block diagram of a second embodiment of the arithmetic device according to the present invention. In the following description, the same components as those described in the first embodiment are assigned the same reference numerals, and description thereof is omitted. According to FIG. 2, the processing unit 4 and the shared memory 5 are connected to the bus 81, the control unit 1, the nonvolatile memory 2 and the memory 3 are connected to the nose 82, and the bus 81 and the bus 82 are connected to the nose connection unit 9. ing.

The node connection unit 9 has a function of restricting the processing unit 4 from accessing the memory 3 and the nonvolatile memory 2. The processing unit 4 destroys the control program or is stored in the memory 3. Yes Control unit 1 is prevented from overwriting control data saved. In addition, it is possible to use different nose protocols by providing bus 81 and bus 82 functions.

FIG. 3 is a block diagram of a third embodiment of the arithmetic device according to the present invention. According to FIG. 3, the processing unit 4 is connected to the bus 81, the control unit 1, the nonvolatile memory 2 and the memory 3 are connected to the bus 82, and the shared memory 5 is connected to the bus 81 and the bus 82. The control unit 1 is connected to each processing unit 4 through a line 73.

In the present embodiment, the control unit 1 notifies the processing unit 4 of various controls for the processing unit 4 using the line 73. In addition, the shared memory 5 is a 2-port memory, for example, and both the bus 81 and the bus 82 can be accessed, so that the bus connected to the processing unit 4 can be connected to the nonvolatile memory 2 and the memory 3 etc. It is completely separated and access from the processing unit 4 to the nonvolatile memory 2 and the memory 3 is completely prevented.

Claims

The scope of the claims

[1] By reading and executing the program for the control means, the control means for assigning the tasks constituting the application program to each processing means based on the status of each processing means held by the status notification means;

A plurality of processing means for executing a task assigned to the control means and outputting a status relating to the execution of the task;

State notification means for holding the state output by the processing means;

An arithmetic device comprising:

[2] first storage means used only by the control means;

Second storage means used by the control means and the processing means;

The arithmetic device according to claim 1, comprising:

[3] Based on the request from the processing means, the control means allocates the area of the second storage means and hardware resources for Z or I / O to the requested processing means,

The processing means accesses only the area of the second storage means allocated by the control means and the hardware resources for Z or I / O,

The arithmetic unit according to claim 2, wherein:

[4] The control means and the first storage means are connected to the first bus,

The plurality of processing means and the second storage means are connected to the second bus,

Having bus conversion means for connecting the first bus and the second node and preventing access from the processing means to the first storage means;

The arithmetic unit according to claim 2, wherein:

[5] The control means and the first storage means are connected to the first bus,

The plurality of processing means are connected to the second bus,

The second storage means is connected to the first bus and the second bus;

The arithmetic unit according to claim 2, wherein: