JP2002314504A - Communication unit and sample clock adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication unit that can realize enhanced demodulation accuracy. SOLUTION: The communication unit (master unit) of this invention is provided with a control circuit 10 that uses a training frame sent from a slave unit at training to calculate transmission line characteristics and an equalizer coefficient, estimates a sample synchronization position of a pilot tone in the training frame on the basis of the equalizer coefficient and instructs adjustment of the sample synchronization position so that a mean value of group delays being one of the transmission line characteristics, and with a sample synchronization circuit 31a that adjusts a current sample clock according to the adjustment instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus employing a multi-carrier modulation / demodulation system, and more particularly to a DMT (Discrete Multi Tone) modulation / demodulation system and OF.
The present invention relates to a communication device that performs data communication using an existing communication line by a DM (Orthogonal Frequency Division Multiplex) modulation / demodulation method or the like, and to a sample clock adjustment method in the communication device.

[0002]

2. Description of the Related Art A conventional communication device will be described below. In recent years, "power line modems" that perform communication using existing power lines (light lines) without adding new communication lines for cost reduction and effective use of existing facilities have attracted attention. The power line modem performs various processes such as control of the product and data communication by networking electrical products such as inside and outside the home, buildings, factories, and stores connected by the power line.

At present, such power line modems include:
An apparatus using the SS (Spread Spectrum) method has been considered. For example, when the SS method is used as a power line modem, the transmitting side modulates predetermined information and further performs spread modulation using a “spreading code” to increase the signal band by several tens to several thousand times. Spread and send. On the other hand, the receiving side performs spread demodulation (despreading) using the same spreading code as the transmitting side, and then demodulates the despread signal into the predetermined information.

In this case, a spreading code desirable for the SS system generally has a sharp peak in the autocorrelation characteristic,
M-sequence (Maximum-length lin
earshift-register sequence) is used.

On the other hand, as a communication device employing a modulation / demodulation method different from the communication device employing the SS method, for example, there is a communication device employing a multicarrier modulation / demodulation method. Here, the operation of a conventional communication device employing the multi-carrier modulation / demodulation method will be described.

First, as a multi-carrier modulation / demodulation method,
The operation of the transmission system of a conventional communication device employing the OFDM modulation / demodulation method will be briefly described. For example, when performing data communication using the OFDM modulation / demodulation method, the transmission system performs tone ordering processing, that is, processing for allocating transmission data of a transmittable number of bits to a plurality of tones (multicarriers) in a predetermined frequency band. Do. More specifically, for example, tone0 to toneX (X
Is an integer indicating the number of tones), transmission data of a predetermined number of bits is allocated. The transmission data is multiplexed for each frame by performing the tone ordering process and the encoding process.

Further, the transmission system performs an inverse fast Fourier transform (IFFT) on the multiplexed transmission data,
The parallel data after the inverse fast Fourier transform is converted into serial data, then the digital waveform is converted into an analog waveform through a D / A converter, and finally the data is transmitted through a transmission path through a low-pass filter.

Next, a conventional communication apparatus employing an OFDM modulation / demodulation method as a multicarrier modulation / demodulation method is described below.
The operation of the receiving system will be briefly described. As above, OFD
When performing data communication using the M modulation / demodulation method, the reception system applies a low-pass filter to the reception data (the transmission data described above), and then converts an analog waveform into a digital waveform through an A / D converter, and sends the data to a time domain equalizer. To perform adaptive equalization processing in the time domain.

Further, the receiving system converts the data after the adaptive equalization processing in the time domain from serial data to parallel data, performs a fast Fourier transform on the parallel data, and then performs frequency domain equalization by a frequency domain equalizer. Is performed.

[0010] The data after the adaptive equalization processing in the frequency domain is converted into serial data by a composite processing (maximum likelihood composite method) and a tone ordering processing, and thereafter, rate conversion processing and FEC (forward error correction) are performed.
on: forward error correction), descrambling, CRC (cy
Processing such as clic redundancy check is performed, and finally the transmission data is reproduced.

As described above, in the conventional communication apparatus employing the OFDM modulation / demodulation method, high-rate communication is performed by utilizing, for example, good transmission efficiency and function flexibility which cannot be obtained by the CDMA or single carrier modulation / demodulation method. It is possible.

[0012]

SUMMARY OF THE INVENTION However,
In a conventional power line modem using the SS system, for example, a spectrum that fills a given band is transmitted, that is, a spectrum that fills a frequency band that can be used under legal regulations: 10 KHz to 450 KHz is transmitted. Therefore, there is a problem that it is difficult to coexist with other communication schemes, and that a transfer rate for a used band is low (extensibility is low).

Further, in the conventional communication apparatus adopting the above-mentioned OFDM modulation / demodulation method, for example, from the viewpoint of "further improvement in demodulation accuracy", a configuration for generating a sample clock for A / D and D / A. There is a problem that there is room for improvement.

The present invention has been made in view of the above, and an object of the present invention is to provide a communication device capable of improving the demodulation accuracy by establishing sample synchronization with high accuracy, and a method of adjusting the sample clock thereof. And

[0015]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, a communication device according to the present invention receives a pilot tone transmitted from a slave device, and operates as a master device that performs data communication with the slave device in synchronization with the pilot tone. And
Further, at the time of training, an equalizer coefficient is calculated using a training frame sent from the slave device, and based on the equalizer coefficient, a transmission path characteristic and a sample synchronization position of a pilot tone in the training frame are estimated. A control unit (corresponding to a control circuit 10 of an embodiment described later) for instructing adjustment of the sample synchronization position so that an average value of a group delay representing one of the transmission path characteristics is 0; And a sample clock adjusting means (corresponding to the sample synchronization circuit 31a) for adjusting the current sample clock in accordance with the adjustment instruction.

In the communication apparatus according to the next invention, the control means sets a target phase angle closest to the estimated sample synchronization position as a first synchronization position candidate, and sets a target phase angle delayed by one cycle from the first synchronization position candidate. A phase angle is set as a second synchronization position candidate, a target phase angle one cycle ahead of the first point is set as a third synchronization position candidate, and a synchronization position candidate whose group delay average value is closest to 0 is determined as an optimal sample. The synchronization position is selected.

In the sample clock adjusting method according to the next invention, an equalizer coefficient calculating step (corresponding to step S14) of calculating an equalizer coefficient using a training frame sent from a slave device during training. ), A transmission path characteristic / synchronization position estimation step (corresponding to step S15) for estimating a transmission path characteristic and a sample synchronization position of a pilot tone in the training frame based on the equalizer coefficient, and A synchronous position adjustment instruction step (corresponding to step S16) for instructing the adjustment of the sample synchronous position so that the average value of the group delay representing one becomes zero, and the current sample clock is adjusted according to the adjustment instruction. A sample clock adjusting step (corresponding to step S17). .

In the sample clock adjusting method according to the next invention, in the synchronous position adjusting instruction step, a target phase angle closest to the estimated sample synchronous position is set as a first synchronous position candidate, and A target phase angle delayed by one cycle is set as a second synchronization position candidate, a target phase angle advanced by one cycle from the first point is set as a third synchronization position candidate, and a synchronization position candidate whose average value of group delay is closest to 0 Is selected as the optimal sample synchronization position.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a communication method and a sample clock generation method according to the present invention will be described in detail with reference to the drawings. The present invention is not limited by the embodiment.

Embodiment 1 In the present embodiment, as a communication device using an existing power line, for example, a power line modem employing a multi-carrier modulation / demodulation method will be described. In a power line modem, for example, an OFDM (Orthogonal Frequency Division Multip
lexing) When transmitting and receiving signals, 256 complex IFFs
Using T, 128 DQPSK data or MQ
Convert AM data to time axis data. Therefore, when the carrier interval is set to Δf = 4.3125 KHz, a band from 0 to 552 KHz is used.

In this embodiment, when transmitting and receiving OFDM signals of 128 tones, for example, tones 24, 40, 56, 72, and 88 are used as pilot tones, and the remaining tones are used as tones for data communication. Used.

FIG. 1 is a diagram showing a configuration example of a communication device operating as a master device on a network. In FIG. 1, 1 is a framing circuit, 2 is a mapper, and 4 is an inverse fast Fourier transform circuit (IFFT: Inverse).
Fast Fourier Transform), 5 is a parallel / serial conversion circuit (P / S), 6 is a digital / analog conversion circuit (D / A), and 7 is a transmission line (power line).
8 is a coupling circuit, 10 is a control circuit,
11 is a deframing circuit, 12 is a demapper, 13 is a correlation detection circuit, 14 is a fast Fourier transform circuit (FFT: Fast Fourier Transform), and 1
Reference numeral 5 denotes a serial / parallel conversion circuit (S / P),
6 is an analog / digital conversion circuit (A / D),
17 is a carrier detector and 31a is a sample synchronization circuit.

The framing circuit 1, the mapper 2,
A transmission system is configured by IFFT4, P / S5, and D / A6.
/ D16, S / P15, FFT14, correlation detection circuit 1
3, a demapper 12, a deframing circuit 11, and a sample synchronization circuit 31a constitute a receiving system.

FIG. 2 is a diagram showing a configuration example of a communication device operating as a slave. In FIG. 2, reference numeral 21 denotes a symbol boundary determination value calculator, 22 denotes a symbol boundary determination unit, 23 denotes a synchronous tone selector, and 31b denotes a sample synchronization circuit. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

Then, the framing circuit 1, the mapper 2,
A transmission system is configured by IFFT4, P / S5, and D / A6.
/ D16, S / P15, FFT14, correlation detection circuit 1
3, a demapper 12, a deframing circuit 11, a symbol boundary determination value calculator 21, a symbol boundary determiner 22, a synchronization tone selector 23, and a sample synchronization circuit 31b constitute a reception system.

Here, the basic operation of the transmission system and the reception system in the communication device will be described with reference to the drawings.
First, the operation of the transmission system will be described. For example, when transmission data is input from a data processing device (not shown) connected to the communication device (power line modem), the framing circuit 1 performs a framing process shown in FIG. Output to 2. Then, the mapper 2 uses the received frame as “tone ordering selection information”, “turbo code length selection information”, “bitmap selection information”, and “power distribution selection information” from the control circuit 10.
(Including DQPSK modulation, M-QAM modulation, turbo coding, power distribution control, etc.), and outputs the result to IFFT4.

In IFFT4, all received tones (tones 48, 64, and
(Other than 80) is subjected to inverse Fourier transform to convert frequency axis data into time axis data and output it to P / S5.

In P / S5, the parallel data output from IFFT4 is converted into serial data, and the serial data is output to D / A6.
At 6, the digital / analog conversion is performed on the serial data, and the analog signal is transmitted to another communication device (not shown) connected to the power line 7 via the coupling circuit 8 and the power line 7.

Next, the operation of the receiving system will be described.
Here, for convenience of explanation, since only one communication device is connected to the transmission path 7, the description will be made using the configuration of the receiving system in FIG. In the receiving system described below,
It is confirmed that symbol synchronization is established using a pilot tone constantly transmitted from a communication device serving as a clock master (actually, using a pilot frame transmitted intermittently when communication is not being performed). It is assumed.

First, when multicarrier data is transmitted from the transmission system as described above, the reception system of another communication device performs an operation reverse to the operation of the transmission system and demodulates the data. More specifically, all the multi-carrier data sent from the communication device on the transmission side is fetched via the coupling circuit 8, and the A / D 16 performs analog / digital conversion. Subsequently, the carrier detector 17 detects a carrier detection field by carrier sense and tone test.

Thereafter, at S / P 15, the serial data converted to digital data is converted to parallel data based on the symbol timing at which synchronization has been established.
The data is output to FFT14.

The FFT 14 performs a Fourier transform on the parallel data, thereby converting the multicarrier signal on the time axis into data on the frequency axis, and outputs the frequency axis data to the demapper 12. Note that the correlation detection circuit 13 determines whether or not the frame being received is for its own device from “ID (see FIG. 3)” which is a code for identifying the transmission path in the received frame. Thereafter, in the demapper 12, if the frame being received is for the own device, the “FEQ coefficient information” and the “information on turbo decoding” specified by the control circuit 10
"Bitmap information""Tone ordering selection information"
And the like, and demodulates the received frequency data.

Finally, the deframing circuit 11 performs a deframing process of cutting out only the data in the transmission frame (see FIG. 2) from the demodulated data.
It generates reception data and outputs the reception data to a device (not shown) connected to the communication device. Note that the deframing process is a process opposite to the framing process by the framing circuit 1, and separates a preamble and a physical layer header to be described later from a frame of the primary demodulated data, and synthesizes only the physical layer payload. processing,
That is, it refers to a process of reconstructing received data into original transmission data.

FIG. 3 is a diagram showing a configuration example of a frame generated by the framing process by the framing circuit 1. The frame shown in FIG. 3 is a physical layer including a preamble field (AGC) which is an area of a signal for carrier detection, a code (ID) indicating a transmission path, a sample clock / symbol clock synchronization signal (PT1, PT2), and the like. The framing circuit 1 includes a header field, a logical data boundary identification code, a bitmap match / mismatch detection code, a command field, control information such as a group code, and a physical layer payload field including transmission data. , And after being modulated in the above-described processing, is output to the transmission path 7.

The frame on the transmission path 7 is received by all communication devices connected to the transmission path, and the control circuit 1
In the case of "0", only when the received signal is identified and the code matches its own code, it is determined that the data transmitted on the transmission path is addressed to itself, and the contents of the subsequent payload portion are understood. . If it is determined that it is not addressed to itself, no operation is performed.

FIG. 4 is a diagram showing pilot tones and tones used by the communication device for data communication. For example, 128 lines at 4.3125 kHz intervals (# 0 to # 12
Assuming the tone of 7), a tone of M times the symbol frequency (M = 24, 40, 56, 72, 88) is used as a pilot tone, and data communication is performed using other tones.

FIG. 5 is a diagram showing a state of the frame on the transmission path and a unit of a symbol inputted to the FFT. For example, in the present embodiment, as shown in FIG. 5, symbols constituting the frame include a cyclic prefix (CP) of 16 samples,
It consists of a data portion of 6 samples and one symbol is 27
There are two samples. Therefore, the receiving side demodulates data in a state where the CP inserted at a known timing is deleted (corresponding to “to demodulation FFT” in FIG. 5). The data portion is a minimum unit of communication, and represents a composite wave of all tones to be transmitted in a 256-point sample. The CP is inserted between symbols in order to prevent inter-symbol interference, and is obtained by duplicating and pasting the last 16 samples of the data portion. It becomes a waveform.

In the above description, the basic operation of the communication device has been described. In the following description, a method of establishing symbol synchronization and a method of adjusting a sample clock will be described from the viewpoint of “further improvement in demodulation accuracy”.

First, a method of establishing symbol synchronization in a slave device when performing data communication between the above communication devices will be described. In this embodiment, the symbol frequency F is set to F = 4.3125 kHz, and D / A6 and A /
The sampling frequency S of D16 is S = 1.104 MHz.
And In this case, the signal for one symbol time is S / F
(256 samples) + CP (16 samples) = 272 samples. Further, the symbol here is the minimum unit of communication, for example, a symbol expressing a synthesized wave of a plurality of tones used for communication with 272 sample data. IFFT4 and FF
When T14 corresponds to 256 samples, the tone frequency that can be generated is Fxx (x = 1 to 128), and 12
Eight tones become available.

In such a state, the receiving system of the slave device first establishes symbol synchronization using the pilot tone transmitted by the master device (clock master) at the time of startup and when data communication is not performed. Be prepared to start data communication at any time. Specifically, first, the A / D 16 converts the signal on the transmission
Captured by performing two-point sampling. And
The symbol boundary determination value calculation unit 21 performs an operation for establishing symbol synchronization with another communication device using the sampling data of the pilot tone after the A / D conversion.

The symbol boundary determination value calculator 21 calculates a determination value required for determining a symbol boundary using the sampling data of the pilot tone. The synchronous tone selector 23 selects at least one pilot tone from a plurality of tones according to an instruction from the control circuit 10. If the frequency of the selected pilot tone is, for example, M times the symbol frequency (M = 2
4, 40, 56, 72, 88), the symbol boundary determination value calculator 21 calculates the past S / F + CP = 272.
The sample data is buffered, and a symbol boundary determination value described later is calculated. However, here, the first content of the buffer is D ₀ , and the last content is D _{0.
(S / F + CP) -1} . Each time new sample data is obtained, the latest S / F + CP = 27
It is calculated using two sample data.

Next, the symbol boundary determiner 22 searches for the timing at which the maximum value of the symbol boundary determination values for the past S / F + CP = 272 has occurred, and uses the searched timing to determine the symbol. Establish synchronization.

FIG. 6 is a diagram showing a specific example of a method of establishing symbol synchronization in the slave device. Here, a case will be described where, for example, a 24 × tone (tone 24) is selected as the pilot tone (M = 24). Note that, as described above, the pilot tone is a signal having the same phase in a symbol cycle unit.

FIG. 6A shows a composite wave of a plurality of tones.
It expresses only the pilot tone. FIG.
In (a), the pilot tone includes a sine wave signal for 25.5 cycles (including CP) in one symbol period. Therefore, when one symbol is sampled at S / F + CP = 272 points, 16 samples are used. 1.5 cycles, 1
It has a value whose sign is inverted every six samples.

First, in the symbol boundary judgment value calculator 21, every time new sample data is obtained, the latest S / S
F + CP = using 272 sample data, and 16
Inverts the value in sample units and performs synchronous addition. That is, as shown in the figure, the sample value is inverted every 16 samples, and synchronous addition is performed within a range of one symbol length.

FIG. 6B is a diagram showing an example of the calculation range of the symbol boundary judgment value, FIG. 6C is a diagram showing an example of the synchronous addition result, and FIG. FIG. 14 is a diagram illustrating a result of addition of absolute values of sample data in a result of synchronous addition, that is, a symbol boundary determination value. As illustrated, when the calculation range of the symbol boundary determination value is A (FIG. 6).
(See (b)), the pilot tone signal is enhanced,
It is possible to obtain a synchronous addition result for 1.5 cycles in which the amplitude becomes 17 times (see A ′ in FIG. 6C). In this case, the symbol boundary determination value becomes maximum (see FIG. 6D). Then, as the calculation range of the symbol boundary determination value deviates from A, the symbol boundary determination value gradually decreases.
Note that signal components of tones other than the selected pilot tone (M = 24) are canceled by the above-described synchronous addition, and the value becomes 0.

On the other hand, when the calculation range of the symbol boundary determination value is B
If (see FIG. 6 (b)), the first half of the 272 points of the signal (D ₀ to D ₁₃₅₎ and the second half (D ₁₃₆ to D ₂₇₂₎ and because the in-phase signal, the synchronization addition (16 sample units of , The pilot tone signal is canceled, and a synchronous addition result for 1.5 cycles in which the amplitude becomes 0 can be obtained (see B ′ in FIG. 6C). Further, in this case, the symbol boundary determination value becomes minimum (see FIG. 6D).

Then, the symbol boundary judgment unit 22 that has received the output from the symbol boundary judgment value calculator 21
The timing at which the symbol boundary determination value over the symbol period is maximum is detected, and this is used as the symbol timing between the communication devices.

As described above, when the symbol synchronization is established in the slave device, the pilot tones (tones 24, 40, 56, 72, pilot tone) satisfying 16n (n is a natural number) +8 are used.
88) to perform the symbol synchronization processing. More specifically, the value of the pilot tone is inverted in units of 1/17 symbol length (16 samples), and synchronous addition of sampling data is performed within one symbol length range. The timing at which the sum of the absolute values of the sampling points in, that is, the symbol boundary determination value, becomes maximum is defined as the symbol timing between the communication devices (the output timing of a symbol synchronization signal described later).

Next, a method of adjusting the sample clock in the slave device will be described. FIG. 7 is a diagram showing a configuration of the sample synchronization circuit 31b in the slave device.
7, reference numeral 41 denotes an FFT module, reference numeral 42 denotes a phase calculation circuit, reference numeral 43 denotes a phase adjustment circuit, and reference numeral 44 denotes a phase adjustment circuit.
Is a sample clock generation unit, 45 is a counter, and 46 is a sample clock generation control circuit.

Here, the sample clock synchronization circuit 3
1b will be described. 8 and 9 are diagrams illustrating a sample clock generation process in the slave device. First, after the received symbol is determined (step S1), the A / D 16 samples the analog signal on the transmission path using the current sample clock (step S1).

Next, in the memory in the FFT module 41, the reception timing of the symbol synchronization signal (see FIG. 9)
That is, based on the write control signal generated by the sample clock generation control circuit 46 with reference to the output value of the counter 45, the writing of each A / D sample data is started (step S2). Then, when the A / D sample data of one symbol (272 samples) is written (reception timing of the next symbol synchronization signal), the FFT in the FFT module 41 starts the FFT processing (step S3). . Each A / D sample data is continuously written even after the above processing,
The FFT processing is performed for each symbol.

Next, the phase calculation circuit 42 executes the level measurement processing and the phase calculation processing of all the pilot tones at the timing of the control signal generated by the sample clock generation control circuit 46 (step S4). For example, in the level measurement process, for each pilot tone,
The levels of the real part and the imaginary part of the FFT processing result are measured. In the phase calculation processing, an angle value (0 to 360 °) is calculated for each pilot tone from the FFT result.

Next, the phase adjustment circuit 43 receives the individual level measurement results, and, at the timing of the control signal generated by the sample clock generation control circuit 46, sets the pilot tone having the highest reception level (highest reliability). Is selected (step S5). Then, the predetermined target phase of the selected pilot tone is compared with the actual reception phase (the above angle value) (step S6), and the phase adjustment amount of the sample clock is calculated according to the phase difference (step S6). S7). For example, at the time of the first phase adjustment after the start of pilot tone reception, it is necessary to quickly establish sample synchronization. Therefore, the phase difference is directly used as the phase adjustment amount. Is weighted (for example, “× 50%” or the like) is performed on the phase difference in consideration of the influence of the phase difference, and the result is used as the phase adjustment amount.

Finally, in the sample clock generation circuit 44, at the next symbol synchronization signal reception timing (see FIG. 9), ie, the sample clock generation control circuit 4
At the timing of the load signal generated by 6, the above-described phase adjustment amount is fetched, and the current phase of the sample clock is corrected (step S 8).

Here, each time the A / D sample data for one symbol is written to the memory in the FFT module 41, the processing of the above-described steps S3 to S8 is repeatedly executed.

In FIG. 8, one of a plurality of pilot tones is selected. However, the present invention is not limited to this, and a predetermined specific pilot tone (for example, tone 56) may be used. Is also good. In this case, the phase adjustment circuit 43 compares the received level measurement result with a predetermined threshold value at the timing of the control signal generated by the sample clock generation control circuit 46. Then, when the level measurement result is higher than the threshold value, the phase adjustment amount of the sample clock is calculated. However, if the level measurement is lower than the threshold,
The phase adjustment amount calculation processing is not performed.

Next, a method of adjusting the sample clock in the master device will be described. The master device adjusts the sample clock by using a training frame (sent from the slave device) used for training between the master device and the slave device, for example, at power-on.

FIG. 10 is a diagram showing a frame format of a training frame. In FIG. 10, a training frame includes an AGC that is an area for performing gain adjustment and carrier sense, a PT that is an area for establishing clock synchronization, an LID that is an area for specifying a communication partner, and an equalizer. It includes TRNS, which is a region for calculating coefficients and SNR (signal-to-noise ratio), and EOF, which is a region indicating the end of a frame.

Here, the sample clock adjustment processing by the master device will be described. FIG. 11 is a diagram illustrating a sample clock adjustment process in the master device. First, the A / D 16 samples an analog signal on the transmission path using the current sample clock (step S1).
1). Then, in S / P 15, the A / D sample data (serial data) is converted into parallel data, and the data is output to FFT 14 (step S1).
2).

Next, in the FFT 14, when the parallel data of one symbol (272 samples) is accumulated, the received parallel data is subjected to fast Fourier transform, and the frequency axis data is output to the control circuit 10. (Step S13). The FFT processing is performed on the parallel data in units of symbols. Here, the frame currently being received by the correlation detection circuit 13 is
The following description will be made on the assumption that it is determined that “the training frame is addressed to the own device”.

Next, the control circuit 10 demodulates the received frequency axis data, and uses the TRNS in the demodulated training frame in a known manner to obtain the equalizer coefficient EQ _i.
Is calculated (step S14). The equalizer coefficient EQ _i obtained here can be expressed as in equation (1). EQ _i = (R _i , I _i ) (1) where R _i represents a coefficient of a real part and I _i represents a coefficient of an imaginary part.

Next, the control circuit 10 uses the equalizer coefficient, that is, utilizes the fact that the equalizer coefficient shows the inverse characteristic of the transmission path characteristic to transmit data between the master device and the slave device. The road characteristics _Ti are estimated (step S15). Also, using the above equalizer coefficients, the synchronization position (phase angle) of the pilot tone at the head of the received frame
Is estimated (step S15). Note that the transmission line characteristics T _i
Can be expressed as in equation (2). _{T i = 1 / EQ i =} (R i / (R i 2 + I i 2), I i / (R i 2 + I i 2)) = (TR i, TI i) (2)

That is, the amplitude characteristic, phase characteristic and group delay characteristic between the master device and the slave device are as follows:
Expressions (3), (4) and (5) can be used. Amplitude = √ (TR _i ² + TI _i ² ) (3) Phase (θ) = tan ⁻¹ (TI _i / TR _i ) (4) Group delay = Δθ / 2πΔf (5) Note that FIG. FIG. 9 is a diagram illustrating an example of a determined transmission path characteristic.

Next, in the control circuit 10, the phase angle (for example, 60 °) of the pilot tone at the head of the acquired received frame is set to a predetermined synchronization position (for example, 135) so that the average value of the group delay becomes 0. (°) is instructed to adjust the sample synchronization position (step S16). Then, the sample synchronization circuit 31a adjusts the current sample clock based on the adjustment instruction (step S17).

[0066] In the control circuit 10 again calculates the equalizer coefficients EQ _i using TRNS in the training frame, confirms synchronization position of the pilot tone (phase angle), then in the training frame The SNR is calculated using the TRNS (step S18).

As described above, in the present embodiment, the master device uses the fact that the equalizer coefficient obtained by training with the slave device shows the inverse characteristic of the transmission channel characteristic to make use of the transmission channel characteristic. It is configured to estimate and adjust the sample synchronization position based on the estimated transmission path characteristics. That is, the above configuration is used to establish sample synchronization with high accuracy. Thereby, the demodulation accuracy in the master device can be greatly improved.

Embodiment 2 In the first embodiment described above,
The master device sets the average value of the group delay to 0,
Adjusted the sample synchronization position. On the other hand, in the present embodiment, the master device creates a plurality of sample synchronization position candidates based on the acquired synchronization position (phase angle) of the pilot tone at the beginning of the received frame, and among the candidates, To select the optimal sample synchronization position.
The basic operation of the communication device (see FIGS. 1 to 5), the method of establishing symbol synchronization (see FIG. 6), and the method of establishing sample synchronization in the slave device (see FIGS. 7 to 9) are described above. This is the same as in the first embodiment.

Here, the sample clock adjustment processing according to the second embodiment will be described. In the present embodiment,
Only operations different from those of the first embodiment will be described. As shown in FIG. 11, after estimating the transmission path characteristics and the synchronization position (phase angle) of the pilot tone, the control circuit 10 sets the following three points as candidates for the optimal sample synchronization position based on the phase angle. I do. Point A: Point corresponding to the reference phase angle closest to the acquired phase angle (target phase angle) Point B: Point corresponding to the reference phase angle delayed by one cycle from A Point C: Reference phase angle advanced by one cycle from A Points corresponding to

Next, the control circuit 10 selects a point at which the average value of the group delay is closest to 0 as an optimum sample synchronization position. FIG. 13 is a diagram illustrating an example of a case where an optimal sample synchronization position is selected from candidates. In this example, the point C where the average value of the group delay is closest to 0 is selected.

Finally, the sample synchronization circuit 31a adjusts the current sample clock so that the selected point is at the sample synchronization position of the pilot tone.

FIG. 14 is a diagram showing an example of sample sync position candidates obtained from the current pilot tone sync position. More specifically, FIG. 14A is a diagram showing candidates when the synchronization position (phase angle) of the pilot tone at the beginning of the acquired received frame is 220 °, for example, and FIG. FIG. 14C is a diagram showing candidates when the synchronization position (phase angle) of the pilot tone at the head of the acquired received frame is 75 °, for example. FIG. Tone synchronization position (phase angle)
FIG. 14 is a diagram showing candidates when is is 330 °. In addition,
Here, the reference phase angle is set to 135 °.

As described above, in the present embodiment, the master device estimates the synchronization position of the pilot tone at the head of the received frame from the equalizer coefficients obtained by training with the slave device, and based on the synchronization position. A plurality of sample synchronization position candidates are created, and an optimal sample synchronization position is selected from the candidates.
Thereby, the demodulation accuracy in the master device can be greatly improved.

[0074]

As described above, according to the present invention, the master device transmits data using the fact that the equalizer coefficient obtained by training with the slave device shows the inverse characteristic of the transmission line characteristic. The channel characteristics are estimated, and the sample synchronization position is adjusted based on the estimated transmission channel characteristics. As a result, since the sample clock can be adjusted with high accuracy, there is an effect that a communication device (master device) capable of greatly improving demodulation accuracy can be obtained.

According to the next invention, the master device estimates the synchronization position of the pilot tone at the head of the received frame from the equalizer coefficient obtained by training with the slave device, and based on the synchronization position, calculates a plurality of sample synchronizations. Position candidates are created, and an optimal sample synchronization position is selected from the candidates. As a result, since the sample clock can be adjusted with high accuracy, there is an effect that a communication device (master device) capable of greatly improving demodulation accuracy can be obtained.

According to the next invention, the master device estimates the transmission channel characteristics by utilizing that the equalizer coefficient obtained by training with the slave device shows the inverse characteristic of the transmission channel characteristics. The sample synchronization position is adjusted based on the estimated transmission path characteristics. Thereby, there is an effect that the sample clock can be adjusted with high accuracy.

According to the next invention, the master device estimates the synchronization position of the pilot tone at the head of the received frame from the equalizer coefficient obtained by training with the slave device, and based on the synchronization position, a plurality of sample synchronizations are performed. Position candidates were created, and an optimum sample synchronization position was selected from the candidates. Thereby, there is an effect that the sample clock can be adjusted with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a communication device that operates as a master device.

FIG. 2 is a diagram illustrating a configuration of a communication device that operates as a slave device.

FIG. 3 is a diagram showing a configuration of a frame generated by a framing process.

FIG. 4 is a diagram showing pilot tones and tones used by the communication device for data communication.

FIG. 5 is a diagram illustrating a state of a frame on a transmission path and a unit of a symbol input to an FFT.

FIG. 6 is a diagram illustrating a specific example of a method for establishing symbol synchronization.

FIG. 7 is a diagram illustrating a configuration of a sample synchronization circuit 31b.

FIG. 8 is a flowchart illustrating a sample clock adjustment process in the slave device.

FIG. 9 is a diagram showing a sample clock adjustment process in a slave device.

FIG. 10 is a diagram showing a frame format of a training frame.

FIG. 11 is a diagram showing a sample clock adjustment process in the master device.

FIG. 12 is a diagram illustrating an example of transmission path characteristics.

FIG. 13 is a diagram illustrating a process of selecting an optimum sample synchronization position.

FIG. 14 is a diagram illustrating an example of a candidate for a sample synchronization position obtained from a synchronization position of a current pilot tone.

[Explanation of symbols]

1 framing circuit, 2 mapper, 4 inverse fast Fourier transform circuit (IFFT), 5 parallel / serial converter circuit (P / S), 6 digital / analog converter circuit (D / A), 7 transmission line (power line), 8 coupling Circuit, 1
0 control circuit, 11 deframing circuit, 12 demapper, 13 correlation detection circuit, 14 fast Fourier transform circuit (FFT), 15 serial / parallel transform circuit (S
/ P), 16 analog / digital conversion circuit (A /
D), 17 carrier detector, 21 symbol boundary determination value calculator, 22 symbol boundary determination unit, 23 synchronous tone selector, 31a, 31b sample synchronous circuit, 41F
FT module, 42 phase calculation circuit, 43 phase adjustment circuit, 44 sample clock generation unit, 45 counter, 46 sample clock generation control circuit.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Masataka Kato 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5K022 DD01 DD21 DD34 DD42 5K046 AA03 BA05 BA06 PS02 PS42 PS55 5K047 AA01 BB05 CC01 HH15 LL06 MM03 MM13 MM44 MM45

Claims (4)

[Claims] 1. A communication device that receives a pilot tone sent from a slave device and performs data communication with the slave device in synchronization with the pilot tone and operates as a master device. Calculating an equalizer coefficient using the obtained training frame; estimating a transmission path characteristic and a sample synchronization position of a pilot tone in the training frame based on the equalizer coefficient; And control means for instructing the adjustment of the sample synchronization position so that the average value of the group delay representing zero becomes zero, and sample clock adjusting means for adjusting a current sample clock in accordance with the adjustment instruction. Communication device. 2. The control unit according to claim 1, wherein a target phase angle closest to the estimated sample synchronization position is determined as a first synchronization position candidate, and
The target phase angle delayed in period is set as a second synchronization position candidate,
3. A target phase angle one cycle ahead of the point (1) is set as a third synchronization position candidate, and a synchronization position candidate whose average value of group delay is closest to 0 is selected as an optimum sample synchronization position. The communication device according to claim 1. 3. A method for adjusting a sample clock of a master device, which receives a pilot tone sent from a slave device and performs data communication with the slave device in synchronization with the pilot tone, comprising the steps of: An equalizer coefficient calculating step of calculating an equalizer coefficient using the training frame that comes in, and a transmission path for estimating transmission path characteristics and a sample synchronization position of a pilot tone in the training frame based on the equalizer coefficient. A characteristic / synchronous position estimating step; a synchronous position adjusting instruction step for instructing adjustment of the sample synchronous position so that an average value of a group delay representing one of the transmission path characteristics becomes 0; A sample clock adjustment step for adjusting the current sample clock; Sample clock adjustment method, which comprises. 4. The synchronizing position adjustment instruction step sets a target phase angle closest to the estimated sample synchronizing position as a first synchronizing position candidate, and
The target phase angle delayed by the period is set as the second synchronization position candidate,
4. A target phase angle advanced by one cycle from the point (1) is set as a third synchronization position candidate, and a synchronization position candidate having an average value of group delay closest to 0 is selected as an optimum sample synchronization position. The sample clock adjustment method described in 1.