JP2002300133A - Communication unit and sample clock generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication unit that can realize improved demodulation accuracy. SOLUTION: The communication unit is provided with an FFT module 41 that stores A/D sample data and applies Fourier transform to the A/D sample data, a phase calculation circuit 42 that measures a reception level of each pilot tone from the real part and the imaginary part of the Fourier transform result and calculates a received phase of each pilot tone from the result of Fourier transform, a phase adjustment circuit 43 that selects the pilot tone with a highest level, compares a target phase of the selected pilot tone with the received phase and calculates the phase adjustment amount of a sample clock depending on the phase difference, and a sample clock generating circuit 44 that captures the phase adjustment amount in a succeeding symbol synchronization timing and adjusts the phase of a current sample clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus employing a multi-carrier modulation / demodulation system, and more particularly to a DMT (Discrete Multi Tone) modulation / demodulation system and OF.
The present invention relates to a communication device that performs data communication using an existing communication line by using a DM (Orthogonal Frequency Division Multiplex) modulation / demodulation method or the like, and a method of generating a sample clock in the communication device.

[0002]

2. Description of the Related Art A conventional communication device will be described below. In recent years, "power line modems" that perform communication using existing power lines (light lines) without adding new communication lines for cost reduction and effective use of existing facilities have attracted attention. The power line modem performs various processes such as control of the product and data communication by networking electrical products such as inside and outside the home, buildings, factories, and stores connected by the power line.

At present, such power line modems include:
An apparatus using the SS (Spread Spectrum) method has been considered. For example, when the SS method is used as a power line modem, the transmitting side modulates predetermined information and further performs spread modulation using a “spreading code” to increase the signal band by several tens to several thousand times. Spread and send. On the other hand, the receiving side performs spread demodulation (despreading) using the same spreading code as the transmitting side, and then demodulates the despread signal into the predetermined information.

In this case, a spreading code desirable for the SS system generally has a sharp peak in the autocorrelation characteristic,
M-sequence (Maximum-length lin
earshift-register sequence) is used.

On the other hand, as a communication device employing a modulation / demodulation method different from the communication device employing the SS method, for example, there is a communication device employing a multicarrier modulation / demodulation method. Here, the operation of a conventional communication device employing the multi-carrier modulation / demodulation method will be described.

First, as a multi-carrier modulation / demodulation method,
The operation of the transmission system of a conventional communication device employing the OFDM modulation / demodulation method will be briefly described. For example, when performing data communication using the OFDM modulation / demodulation method, the transmission system performs tone ordering processing, that is, processing for allocating transmission data of a transmittable number of bits to a plurality of tones (multicarriers) in a predetermined frequency band. Do. More specifically, for example, tone0 to toneX (X
Is an integer indicating the number of tones), transmission data of a predetermined number of bits is allocated. The transmission data is multiplexed for each frame by performing the tone ordering process and the encoding process.

Further, the transmission system performs an inverse fast Fourier transform (IFFT) on the multiplexed transmission data,
The parallel data after the inverse fast Fourier transform is converted into serial data, then the digital waveform is converted into an analog waveform through a D / A converter, and finally the data is transmitted through a transmission path through a low-pass filter.

Next, a conventional communication apparatus employing an OFDM modulation / demodulation method as a multicarrier modulation / demodulation method is described below.
The operation of the receiving system will be briefly described. As above, OFD
When performing data communication using the M modulation / demodulation method, the reception system applies a low-pass filter to the reception data (the transmission data described above), and then converts an analog waveform into a digital waveform through an A / D converter, and sends the data to a time domain equalizer. To perform adaptive equalization processing in the time domain.

Further, the receiving system converts the data after the adaptive equalization processing in the time domain from serial data to parallel data, performs a fast Fourier transform on the parallel data, and then performs frequency domain equalization by a frequency domain equalizer. Is performed.

[0010] The data after the adaptive equalization processing in the frequency domain is converted into serial data by a composite processing (maximum likelihood composite method) and a tone ordering processing, and thereafter, rate conversion processing and FEC (forward error correction) are performed.
on: forward error correction), descrambling, CRC (cy
Processing such as clic redundancy check is performed, and finally the transmission data is reproduced.

As described above, in the conventional communication apparatus employing the OFDM modulation / demodulation method, high-rate communication is performed by utilizing, for example, good transmission efficiency and function flexibility which cannot be obtained by the CDMA or single carrier modulation / demodulation method. It is possible.

[0012]

SUMMARY OF THE INVENTION However,
In a conventional power line modem using the SS system, for example, a spectrum that fills a given band is transmitted, that is, a spectrum that fills a frequency band that can be used under legal regulations: 10 KHz to 450 KHz is transmitted. Therefore, there is a problem that it is difficult to coexist with other communication schemes, and that a transfer rate for a used band is low (extensibility is low).

In the conventional communication apparatus employing the OFDM modulation / demodulation method, for example, from the viewpoint of “further improvement in transmission rate and demodulation accuracy”, A / D
There is a problem that there is room for improvement in the configuration for generating the sample clocks for D and D / A.

The present invention has been made in view of the above, and an object of the present invention is to provide a communication device capable of realizing improvement in demodulation accuracy by establishing sample synchronization with high accuracy, and a sample clock generation method thereof. And

[0015]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, the communication device according to the present invention is configured to receive a plurality of intermittently transmitted pilot tones and perform data communication with another device in a state synchronized with the pilot tones. A / D conversion means (corresponding to an A / D 16 in an embodiment described later) for A / D converting an analog signal on a transmission path, and memory means for storing the A / D sample data (memory in the FFT module 41) And Fourier transform means (corresponding to the FFT core in the FFT module 41) for performing a Fourier transform on the A / D sample data at the stage when the A / D sample data for one symbol is written. Level measuring means (corresponding to a phase calculation circuit 42) for measuring a reception level of each pilot tone from a real part and an imaginary part of the Fourier transform result; Phase calculating means for calculating the received phase of each pilot tone from Fourier transform result (phase calculating circuit 4
2), the highest level pilot tone is selected, the target phase of the selected pilot tone is compared with the reception phase, and the phase adjustment amount of the sample clock is calculated according to the phase difference. A phase adjustment amount calculating means (corresponding to the phase adjusting circuit 43) and a sample clock phase adjusting means (to the sample clock generating circuit 44) for taking in the phase adjusting amount at the next symbol synchronization timing and adjusting the phase of the current sample clock ).

In the communication device according to the next invention,
A configuration in which a predetermined single pilot tone intermittently transmitted is received and data communication is performed with another device in synchronization with the pilot tone, and A / D conversion of an analog signal on a transmission path is performed. / D conversion means;
Memory means for storing D sample data (corresponding to the memory in the FFT module 41), and A / D for one symbol
Fourier transform means (corresponding to the FFT core in the FFT module 41) for performing a Fourier transform on the A / D sample data when the sample data is written;
Level measuring means (corresponding to the phase calculating circuit 42) for measuring the reception level of the pilot tone from the real part and the imaginary part of the Fourier transform result; and phase calculating means (phase) for calculating the pilot tone receiving phase from the Fourier transform result. If the level is higher than a predetermined threshold, the target phase of the pilot tone is compared with the reception phase, and the phase adjustment amount of the sample clock is calculated according to the phase difference. A phase adjustment amount calculating means (corresponding to the phase adjusting circuit 43), and a sample clock phase adjusting means (sample clock generating circuit 44) which fetches the phase adjustment amount at the next symbol synchronization timing and adjusts the phase of the current sample clock. ) Is provided.

In the communication apparatus according to the next invention, the phase adjustment amount calculating means changes the first phase after the pilot tone transitions from the transmission stop period to the transmission period on the transmission path and starts receiving the pilot tone. At the time of adjustment, the phase difference is used as a phase adjustment amount. On the other hand, at the second and subsequent phase adjustments, a predetermined weighting process is performed on the phase difference, and the result is used as the phase adjustment amount.

In the sample clock generation method according to the next invention, an A / D conversion step (corresponding to step S2) for A / D converting an analog signal on a transmission line, and storing the A / D sample data. A storage step (corresponding to step S2), a Fourier transform step (corresponding to step S3) of performing a Fourier transform on the A / D sample data when one symbol of A / D sample data is written, A level measuring step (corresponding to step S4) of measuring a reception level of each pilot tone from a real part and an imaginary part of the Fourier transform result;
A phase calculating step of calculating a reception phase of each pilot tone from the Fourier transform result (corresponding to step S4)
And a selection step (corresponding to step S5) of selecting a pilot tone having the highest level, comparing the target phase of the selected pilot tone with the reception phase, and adjusting the phase of the sample clock in accordance with the phase difference. And a sample clock phase adjustment step (step S8) of taking in the phase adjustment amount at the next symbol synchronization timing and adjusting the phase of the current sample clock.
).

In the sample clock generating method according to the next invention, an A / D conversion step (corresponding to step S2) for A / D converting an analog signal on a transmission line, and storing the A / D sample data. A storage step (corresponding to step S2), a Fourier transform step (corresponding to step S3) of performing a Fourier transform on the A / D sample data when one symbol of A / D sample data is written, A level measuring step (corresponding to step S4) of measuring a reception level of a pilot tone from a real part and an imaginary part of the Fourier transform result, and a phase calculating step of calculating a pilot tone reception phase from the Fourier transform result (step S4). Equivalent),
When the level is higher than a predetermined threshold value, a target phase of the pilot tone is compared with the reception phase, and a phase adjustment amount of the sample clock is calculated according to the phase difference. S11, S6
(Corresponding to S7) and a sample clock phase adjusting step (corresponding to step S8) of acquiring the phase adjustment amount at the next symbol synchronization timing and adjusting the phase of the current sample clock.

In the sample clock generating method according to the next invention, in the phase adjustment amount calculating step, the pilot tone transitions from the transmission stop period to the transmission period on the transmission line, and the first time after receiving the pilot tone, In the phase adjustment, the phase difference is used as a phase adjustment amount. On the other hand, in the second and subsequent phase adjustments, a predetermined weighting process is performed on the phase difference, and the result is used as the phase adjustment amount. .

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a communication device and a sample clock generation method according to the present invention will be described in detail with reference to the drawings. The present invention is not limited by the embodiment.

Embodiment 1 In the present embodiment, as a communication device using an existing power line, for example, a power line modem employing a multi-carrier modulation / demodulation method will be described. In a power line modem, for example, an OFDM (Orthogonal Frequency Division Multip
lexing) When transmitting and receiving signals, 256 complex IFFs
Using T, 128 DQPSK data or MQ
Convert AM data to time axis data. Therefore, when the carrier interval is set to Δf = 4.3125 KHz, a band from 0 to 552 KHz is used.

In this embodiment, when transmitting and receiving an OFDM signal of 128 tones, for example, tones 56, 72, and 88 are used as pilot tones, and the remaining tones are used as tones for data communication.

FIG. 1 is a diagram showing a configuration example of a communication device according to the present invention. In FIG. 1, 1 is a framing circuit, 2 is a mapper, 4 is an inverse fast Fourier transform (IFFT) circuit, 5 is a parallel / serial transform circuit (P / S), Reference numeral 6 denotes a digital / analog conversion circuit (D / A), 7 denotes a transmission line (power line), 8 denotes a coupling circuit, 10 denotes a control circuit, 11 denotes a deframing circuit, and 12 denotes a demapper. And 14 is a fast Fourier transform circuit (FFT: Fast Fourier Transform).
Reference numeral 5 denotes a serial / parallel conversion circuit (S / P),
6 is an analog / digital conversion circuit (A / D),
17 is a carrier detector, 21 is a symbol boundary judgment value calculator, 22 is a symbol boundary judgment unit, and 2
Reference numeral 3 denotes a synchronization tone selector, and reference numeral 31 denotes a sample synchronization circuit.

Then, the framing circuit 1, the mapper 2,
A transmission system is configured by IFFT4, P / S5, and D / A6.
/ D16, S / P15, FFT 14, demapper 12, deframing circuit 11, symbol boundary determination value calculator 2
1, symbol boundary determiner 22, synchronous tone selector 23,
The sample synchronizing circuit 31 forms a receiving system.

Here, basic operations of the transmission system and the reception system will be described with reference to the drawings. First, the operation of the transmission system will be described. For example, when transmission data is input from a data processing device (not shown) connected to the communication device (power line modem), the framing circuit 1 performs a framing process shown in FIG. Output to 2. Then, the mapper 2 maps the received frame using “tone ordering selection information”, “turbo code length selection information”, “bitmap selection information”, “power distribution selection information” from the control circuit 10 (DQPSK modulation, M-QAM modulation, turbo coding, power distribution control, etc.) and output the result to IFFT4.

In IFFT4, all received tones (tones 48, 64, and
(Other than 80) is subjected to inverse Fourier transform to convert frequency axis data into time axis data and output it to P / S5.

In P / S5, the parallel data output from IFFT4 is converted into serial data, and the serial data is output to D / A6.
At 6, the digital / analog conversion is performed on the serial data, and the analog signal is transmitted to another communication device (not shown) connected to the power line 7 via the coupling circuit 8 and the power line 7.

Next, the operation of the receiving system will be described.
Here, for convenience of explanation, since only one communication device is connected to the transmission path 7, the description will be made using the configuration of the receiving system in FIG. In the receiving system described below,
It is confirmed that symbol synchronization is established using a pilot tone constantly transmitted from a communication device serving as a clock master (actually, using a pilot frame transmitted intermittently when communication is not being performed). It is assumed.

First, when multicarrier data is transmitted from the transmission system as described above, the reception system of another communication device performs an operation reverse to the operation of the transmission system and demodulates the data. More specifically, all the multi-carrier data sent from the communication device on the transmission side is fetched via the coupling circuit 8, and the A / D 16 performs analog / digital conversion. Subsequently, the carrier detector 17 detects a carrier detection field by carrier sense and tone test.

Thereafter, at S / P 15, the serial data converted to digital data is converted to parallel data based on the symbol timing at which synchronization has been established.
The data is output to FFT14.

The FFT 14 performs a Fourier transform on the parallel data, thereby converting the multicarrier signal on the time axis into data on the frequency axis, and outputs the frequency axis data to the demapper 12. After that, the demapper 12 demodulates the received frequency data by using “FEQ coefficient information”, “information on turbo decoding”, “bitmap information”, and “tone ordering selection information” specified by the control circuit 10.

Finally, the deframing circuit 11 performs a deframing process of cutting out only the data in the transmission frame (see FIG. 2) from the demodulated data.
It generates reception data and outputs the reception data to a device (not shown) connected to the communication device. Note that the deframing process is a process opposite to the framing process by the framing circuit 1, and separates a preamble and a physical layer header to be described later from a frame of the primary demodulated data, and synthesizes only the physical layer payload. processing,
That is, it refers to a process of reconstructing received data into original transmission data.

FIG. 2 is a diagram showing the structure of a frame generated by the framing processing by the framing circuit 1. As shown in FIG. The frame shown in FIG. 2 includes a preamble field (AGC) which is an area of a signal for carrier detection, a code (ID) indicating a transmission path, a sample clock / symbol clock synchronization signal (PT1, PT2), and the like. The framing circuit 1 includes a header field, a logical data boundary identification code, a bitmap match / mismatch detection code, a command field, control information such as a group code, and a physical layer payload field including transmission data. , And after being modulated in the above-described processing, is output to the transmission path 7.

The frame on the transmission line is received by all communication devices connected to the transmission line, and the control circuit 10
Then, only when the received signal is identified and the code matches the own code, it is determined that the data transmitted on the transmission path is addressed to itself, and the contents of the subsequent payload portion are understood. If it is determined that it is not addressed to itself, no operation is performed.

FIG. 3 is a diagram showing pilot tones and tones used by the communication device for data communication. For example, 128 lines at 4.3125 kHz intervals (# 0 to # 12
Assuming the tone of 7), a tone of M times the symbol frequency (M = 24, 40, 56, 72, 88) is used as a pilot tone, and data communication is performed using other tones.

FIG. 4 is a diagram showing the state of the frame on the transmission line and the unit of the symbol input to the FFT. For example, in the present embodiment, as shown in FIG. 4, the symbols constituting the frame include a cyclic prefix (CP) of 16 samples,
It consists of a data portion of 6 samples and one symbol is 27
There are two samples. Therefore, the receiving side demodulates the data in a state where the CP inserted at a known timing is deleted (corresponding to “to demodulation FFT” in FIG. 4). The data portion is a minimum unit of communication, and represents a composite wave of all tones to be transmitted in a 256-point sample. The CP is inserted between symbols in order to prevent inter-symbol interference, and is obtained by duplicating and pasting the last 16 samples of the data portion. It becomes a waveform.

Here, a method of establishing symbol synchronization when data communication is performed between the communication devices will be described in detail. In this embodiment, the symbol frequency F is set to F = 4 kHz.
z, and the sampling frequency S of D / A6 and A / D16 is S = 1.024 MHz. In this case, the signal for one symbol time is S / F (256 samples) + CP
(16 samples) = 272 samples. Further, the symbol here is the minimum unit of communication, for example, a symbol expressing a synthesized wave of a plurality of tones used for communication with 272 sample data.
When IFFT4 and FFT14 correspond to 256 samples, the tone frequency that can be generated is Fxx (x
= 1 to 128), and 128 tones can be used.

In such a state, the receiving system of the communication device first establishes symbol synchronization using the pilot tone transmitted by the clock master at the time of start-up and when data communication is not performed. Be prepared to start. Specifically, first, A /
D16 captures the signal on the transmission line by performing 272-point sampling. Then, the symbol boundary determination value calculation unit 21 performs an operation for establishing symbol synchronization with another communication device using the sampling data of the pilot tone after the A / D conversion.

The symbol boundary determination value calculator 21 calculates a determination value required for determining a symbol boundary using the sampling data of the pilot tone. The synchronous tone selector 23 selects at least one pilot tone from a plurality of tones according to an instruction from the control circuit 10. If the frequency of the selected pilot tone is, for example, M times the symbol frequency (M = 2
4, 40, 56, 72, 88), the symbol boundary determination value calculator 21 calculates the past S / F + CP = 272.
The sample data is buffered, and a symbol boundary determination value described later is calculated. However, here, the first content of the buffer is D ₀ , and the last content is D _{0.
(S / F + CP) -1} . Each time new sample data is obtained, the latest S / F + CP = 27
It is calculated using two sample data.

Next, the symbol boundary determining unit 22 searches for the timing at which the maximum value of the symbol boundary determination values for the past S / F + CP = 272 times has occurred, and uses the searched timing to determine the symbol. Establish synchronization.

FIG. 5 is a diagram showing a specific example of a method of establishing symbol synchronization between communication devices. Here, as the pilot tone, for example, a 24 × tone (tone 24)
Is selected (M = 24). Note that, as described above, the pilot tone is a signal having the same phase in a symbol cycle unit.

FIG. 5A shows a composite wave of a plurality of tones.
It expresses only the pilot tone. FIG.
In (a), the pilot tone includes a sine wave signal of 25 cycles (including CP) in one symbol period.
When one symbol is sampled at S / F + CP = 272 points, 16 samples have a period of 1.5, and have a value whose sign is inverted every 16 samples.

First, in the symbol boundary judgment value calculator 21, every time new sample data is obtained, the latest S / S
F + CP = using 272 sample data, and 16
Inverts the value in sample units and performs synchronous addition. That is, as shown in the figure, the sample value is inverted every 16 samples, and synchronous addition is performed within a range of one symbol length.

FIG. 5B is a diagram showing an example of the calculation range of the symbol boundary determination value, FIG. 5C is a diagram showing an example of the synchronous addition result, and FIG. FIG. 14 is a diagram illustrating a result of addition of absolute values of sample data in a result of synchronous addition, that is, a symbol boundary determination value. As shown, when the calculation range of the symbol boundary determination value is A (FIG. 5)
(See (b)), the pilot tone signal is enhanced,
It is possible to obtain a synchronous addition result for 1.5 cycles in which the amplitude becomes 17 times (see A ′ in FIG. 5C). In this case, the symbol boundary determination value becomes the maximum (see FIG. 5D). Then, as the calculation range of the symbol boundary determination value deviates from A, the symbol boundary determination value gradually decreases.
Note that signal components of tones other than the selected pilot tone (M = 24) are canceled by the above-described synchronous addition, and the value becomes 0.

On the other hand, when the calculation range of the symbol boundary determination value is B
5 (see FIG. 5B), since the first half (D _{0 to} D ₁₃₅ ) and the second half (D _{136 to} D ₂₇₂ ) of the 272-point signal are in-phase signals, the synchronous addition (in units of 16 samples) The signal of the pilot tone is canceled by the inversion, and a synchronous addition result for 1.5 cycles in which the amplitude becomes 0 can be obtained (see B ′ in FIG. 5C). In this case, the symbol boundary determination value becomes minimum (see FIG. 5D).

Then, the symbol boundary determining unit 22 that has received the output from the symbol boundary determining value calculator 21
The timing at which the symbol boundary determination value over the symbol period is maximum is detected, and this is used as the symbol timing between the communication devices.

As described above, when symbol synchronization is established between communication apparatuses, pilot tones (tones 24, 40, 56, 72, 8) satisfying 16n (n is a natural number) +8
The symbol synchronization process is performed using 8). More specifically, the value of the pilot tone is inverted in units of 1/17 symbol length (16 samples), and synchronous addition of sampling data is performed within one symbol length range. The timing at which the sum of the absolute values of the sampling points in, that is, the symbol boundary determination value, becomes maximum is defined as the symbol timing between the communication devices (the output timing of a symbol synchronization signal described later).

In the above description, the basic operation of the communication device and the method of establishing the symbol synchronization between the communication devices have been described. In the following description, a configuration for generating an optimal sample clock from a viewpoint of “further improvement in demodulation accuracy”, that is, a configuration for establishing sample synchronization with high accuracy will be described.

FIG. 6 is a diagram showing a configuration of the sample synchronization circuit 31 of the present embodiment. In FIG. 6, 41 is FFT.
Reference numeral 42 denotes a phase calculation circuit, 43 denotes a phase adjustment circuit, 44 denotes a sample clock generation unit, 45 denotes a counter, and 46 denotes a sample clock generation control circuit.

Here, the sample clock synchronization circuit 3
1 will be described.
7 and 8 are diagrams illustrating the sample clock generation processing according to the first embodiment. First, after the received symbol is determined (step S1), the A / D 16 samples the analog signal on the transmission path using the current sample clock (step S1).

Next, in the memory in the FFT module 41, the reception timing of the symbol synchronization signal (see FIG. 8)
That is, based on the write control signal generated by the sample clock generation control circuit 46 with reference to the output value of the counter 45, the writing of each A / D sample data is started (step S2). Then, when the A / D sample data of one symbol (272 samples) is written (reception timing of the next symbol synchronization signal), the FFT in the FFT module 41 starts the FFT processing (step S3). . Each A / D sample data is continuously written even after the above processing,
The FFT processing is performed for each symbol.

Next, the phase calculation circuit 42 executes the level measurement processing and the phase calculation processing of all the pilot tones at the timing of the control signal generated by the sample clock generation control circuit 46 (step S4). For example, in the level measurement process, for each pilot tone,
The levels of the real part and the imaginary part of the FFT processing result are measured. In the phase calculation processing, an angle value (0 to 360 °) is calculated for each pilot tone from the FFT result.

Next, the phase adjustment circuit 43 receives the individual level measurement results, and, at the timing of the control signal generated by the sample clock generation control circuit 46, sets the pilot tone having the highest reception level (highest reliability). Is selected (step S5). Then, the predetermined target phase of the selected pilot tone is compared with the actual reception phase (the above angle value) (step S6), and the phase adjustment amount of the sample clock is calculated according to the phase difference (step S6). S7). For example, at the time of the first phase adjustment after the start of pilot tone reception, it is necessary to quickly establish sample synchronization. Therefore, the phase difference is directly used as the phase adjustment amount. Is weighted (for example, “× 50%” or the like) is performed on the phase difference in consideration of the influence of the phase difference, and the result is used as the phase adjustment amount.

Finally, in the sample clock generation circuit 44, at the next symbol synchronization signal reception timing (see FIG. 8), that is, the sample clock generation control circuit 4
At the timing of the load signal generated by 6, the above-described phase adjustment amount is fetched, and the current phase of the sample clock is corrected (step S 8).

In this embodiment, each time the A / D sample data for one symbol is written to the memory in the FFT module 41, the processes of steps S3 to S8 are repeatedly executed.

As described above, in the present embodiment, the configuration is such that the amount of phase adjustment of the sample clock is calculated based on the difference between the target phase of the selected pilot tone and the actual reception phase. Since the synchronization is established, the demodulation accuracy can be greatly improved as compared with the related art.

Embodiment 2 In the first embodiment, one of a plurality of pilot tones is selected, and the phase adjustment amount is calculated based on the difference between the target phase of the pilot tone and the actual reception phase. On the other hand, in the present embodiment, the circuit size is reduced by calculating the amount of phase adjustment based on the difference between the predetermined target phase of the specific pilot tone and the actual reception phase. The basic operation of the communication device (see FIGS. 1 to 4), a method for establishing symbol synchronization between the communication devices (see FIG. 5), and the configuration of the sample synchronization circuit 31 (see FIG. 6)
Is the same as in the first embodiment.

FIG. 9 is a flowchart showing a sample clock generation process according to the second embodiment. First, after the received symbol is determined (step S1), the A / D 16 samples the analog signal on the transmission path using the current sample clock (step S1).

Next, in the memory in the FFT module 41, the control circuit 46 for generating the sample clock generates the counter 4 at the reception timing of the symbol synchronization signal.
Based on the write control signal generated with reference to the output value of No. 5, the writing of the A / D sample data is started (step S2). When the A / D sample data for one symbol (272 samples) is written (reception timing of the next symbol synchronization signal), the FFT
The FFT in the module 41 starts the FFT processing (Step S3). The A / D sample data is continuously written even after the above processing, and the FFT processing is executed for each symbol.

Next, the phase calculation circuit 42 executes the level measurement process and the phase calculation process of the pilot tone (for example, # 56) at the timing of the control signal generated by the sample clock generation control circuit 46 (step S).
4). For example, in the level measurement processing, the levels of the real part and the imaginary part of the FFT processing result are measured. Also,
In the phase calculation process, the angle value (0 to 3) is obtained from the FFT result.
60 °).

Next, the phase adjustment circuit 43 receives the level measurement result and compares the level measurement result with a predetermined threshold value at the timing of the control signal generated by the sample clock generation control circuit 46. (Step 11). If the level measurement result is higher than the threshold value, the target phase of the pilot tone is compared with the reception phase (the angle value) (step S6), and the phase adjustment amount of the sample clock is adjusted according to the phase difference. Is calculated (step S7). For example, at the time of the first phase adjustment after the reception of the pilot tone, it is necessary to quickly establish the sample synchronization. Therefore, the phase difference is used as the phase adjustment amount as it is. The phase difference is weighted (for example, “× 50%” or the like) in consideration of the influence of the phase difference, and the result is used as the phase adjustment amount. In the above processing, if the level measurement result is lower than the threshold, the phase adjustment amount calculation processing is not performed.

Finally, in the sample clock generation circuit 44, the reception timing of the next symbol synchronization signal (see FIG. 8), that is, the sample clock generation control circuit 4
At the timing of the load signal generated by 6, the above-described phase adjustment amount is fetched, and the current phase of the sample clock is corrected (step S 8).

In this embodiment, as described above, every time the A / D sample data for one symbol is written to the memory in the FFT module 41, the above steps S3, S4, S11 and S6 to S8 are performed. Repeat the process.

As described above, in the present embodiment, the configuration is such that the phase adjustment amount of the sample clock is calculated based on the difference between the target phase and the actual reception phase of one pilot tone defined in advance. Since the pilot tone selection processing described above is omitted, the circuit can be significantly reduced.

[0066]

As described above, according to the present invention, according to the present invention, the amount of phase adjustment of the sample clock is calculated based on the difference between the target phase of the selected pilot tone and the actual reception phase. It was decided to establish sample synchronization for accuracy. As a result, there is an effect that the demodulation accuracy can be greatly improved as compared with the related art.

According to the next invention, the configuration is such that the amount of phase adjustment of the sample clock is calculated based on the difference between the target phase of one pilot tone defined in advance and the actual reception phase. The processing was omitted. As a result, there is an effect that the circuit scale can be significantly reduced.

According to the next invention, for example, immediately after the start of pilot tone reception, it is possible to quickly establish sample synchronization. Furthermore, at the time of the second and subsequent phase adjustments, there is an effect that clock adjustment can be performed in consideration of the influence of noise and the like.

According to the next invention, the amount of phase adjustment of the sample clock is calculated based on the difference between the target phase of the selected pilot tone and the actual reception phase. As a result, there is an effect that the demodulation accuracy can be greatly improved as compared with the related art.

According to the next invention, the phase adjustment amount of the sample clock is calculated based on the difference between the target phase of one pilot tone defined in advance and the actual reception phase.
Furthermore, the pilot tone selection process is omitted.
As a result, there is an effect that the circuit scale can be significantly reduced.

According to the next invention, for example, immediately after the start of pilot tone reception, it is possible to quickly establish sample synchronization. Furthermore, at the time of the second and subsequent phase adjustments, there is an effect that clock adjustment can be performed in consideration of the influence of noise and the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a communication device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a frame generated by a framing process.

FIG. 3 is a diagram showing pilot tones and tones used by the communication device for data communication.

FIG. 4 is a diagram illustrating a state of a frame on a transmission path and a unit of a symbol input to an FFT.

FIG. 5 is a diagram illustrating a specific example of a method of establishing symbol synchronization between communication devices.

FIG. 6 is a diagram showing a configuration of a sample synchronization circuit 31 of the present invention.

FIG. 7 is a flowchart illustrating a sample clock generation process according to the first embodiment;

FIG. 8 is a diagram illustrating a sample clock generation process according to the first embodiment;

FIG. 9 is a flowchart illustrating a sample clock generation process according to the second embodiment;

[Explanation of symbols]

1 framing circuit, 2 mapper, 4 inverse fast Fourier transform circuit (IFFT), 5 parallel / serial converter circuit (P / S), 6 digital / analog converter circuit (D / A), 7 transmission line (power line), 8 coupling Circuit, 1
0 control circuit, 11 deframing circuit, 12 demapper, 14 fast Fourier transform circuit (FFT), 15
Serial / parallel converter (S / P), 16 analog / digital converter (A / D), 17 carrier detector, 21 symbol boundary determination value calculator, 22 symbol boundary determiner, 23 synchronous tone selector, 31 A sample synchronization circuit, 41 FFT module, 42 phase calculation circuit, 43 phase adjustment circuit, 44 sample clock generation unit, 45 counter, 46 sample clock generation control circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K022 AA04 AA16 AA26 AA30 DD01 DD33 DD42 5K046 AA03 BA01 BA05 BB05 PS03 PS11 PS42 PS44 PS53 5K047 BB06 GG09 GG45 MM18 MM38 MM59 MM63

Claims (6)

[Claims] 1. A communication apparatus for receiving a plurality of intermittently transmitted pilot tones and performing data communication with another apparatus in synchronization with the pilot tones, A / D converting an analog signal on a transmission path. A / D conversion means, memory means for storing the A / D sample data, and Fourier for performing a Fourier transform on the A / D sample data when one symbol of A / D sample data is written. Conversion means; level measurement means for measuring the reception level of each pilot tone from the real part and imaginary part of the Fourier transform result; phase calculation means for calculating the reception phase of each pilot tone from the Fourier transform result; High pilot tone, and
Comparing a target phase of the selected pilot tone with the reception phase and calculating a phase adjustment amount of the sample clock in accordance with the phase difference; and a phase adjustment amount at the next symbol synchronization timing. And a sample clock phase adjusting means for adjusting the phase of the current sample clock. 2. A communication apparatus for receiving a predetermined single pilot tone intermittently transmitted and performing data communication with another apparatus in a state synchronized with the pilot tone, wherein an analog signal on a transmission path is transmitted. A / D conversion means for A / D conversion, memory means for storing the A / D sample data, and at the stage where one symbol of A / D sample data is written, the A / D sample data Fourier transform means for performing Fourier transform; level measuring means for measuring a reception level of a pilot tone from a real part and an imaginary part of the Fourier transform result; and phase calculating means for calculating a reception phase of a pilot tone from the Fourier transform result When the level is higher than a predetermined threshold, the target phase of the pilot tone is compared with the reception phase, and Phase adjustment amount calculating means for calculating the phase adjustment amount of the sample clock according to the phase difference of the sample clock phase adjustment means for taking in the phase adjustment amount at the next symbol synchronization timing and adjusting the phase of the current sample clock A communication device comprising: 3. The phase adjustment amount calculating means, on a transmission path, after a pilot tone transitions from a transmission stop period to a transmission period, and starts receiving a pilot tone. 3. The communication according to claim 1, wherein a predetermined weighting process is performed on the phase difference during the second and subsequent phase adjustments, and the result is used as the phase adjustment amount. apparatus. 4. A sample clock generation method for a communication device that receives a plurality of intermittently transmitted pilot tones and performs data communication with another device in a state synchronized with the pilot tones. An A / D conversion step of A / D converting the A / D sample data; a storage step of storing the A / D sample data; and a step in which the A / D sample data for one symbol is written. A Fourier transform step of performing a Fourier transform on the basis of: a level measuring step of measuring a reception level of each pilot tone from a real part and an imaginary part of the Fourier transform result; and a phase of calculating a reception phase of each pilot tone from the Fourier transform result. A calculating step, a selecting step of selecting the highest level pilot tone, and a selecting step. Comparing the target phase of the obtained pilot tone with the reception phase, and calculating a phase adjustment amount of the sample clock according to the phase difference; anda phase adjustment amount at the next symbol synchronization timing. A sample clock phase adjusting step of adjusting the phase of the current sample clock by capturing the sample clock. 5. A sample clock generating method for a communication device that receives a single pilot tone that is predefined and transmitted intermittently and performs data communication with another device in synchronization with the pilot tone. An A / D conversion step of A / D converting an analog signal on the transmission path; a storage step of storing the A / D sample data; and a step in which the A / D sample data for one symbol is written. A Fourier transform step of performing a Fourier transform on the D sample data; a level measuring step of measuring a reception level of a pilot tone from a real part and an imaginary part of the Fourier transform result; and a receiving phase of a pilot tone from the Fourier transform result. Calculating a phase to be calculated; and, when the level is higher than a predetermined threshold, Comparing the target phase of the tone and the reception phase, and calculating a phase adjustment amount of the sample clock according to the phase difference; and capturing the phase adjustment amount at the next symbol synchronization timing. A sample clock phase adjusting step of adjusting the phase of the sample clock. 6. In the phase adjustment amount calculating step, after a pilot tone transitions from a transmission stop period to a transmission period on a transmission path and reception of the pilot tone is started, at the time of the first phase adjustment, The phase difference is defined as a phase adjustment amount. On the other hand, during the second and subsequent phase adjustments, a predetermined weighting process is performed on the phase difference, and the result is defined as the phase adjustment amount. The described sample clock generation method.