JP2002261295A - Schottky, p-n junction diode, and pin junction diode and their manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown voltage diode that prevents leakage current from increasing, reliably stabilizes operation, at the same time, has a high yield in making area larger, and uses silicon carbide. SOLUTION: In the Schottky diode 10, where a Schottky electrode 15 is joined to a 4H-type SiC semiconductor 13, the orientation of an SiC semiconductor 13 that comes into contact with the Schottky electrode 15 should have a 03-38} surface, or a surface at an off angle that is within 10 deg. from the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a silicon carbide (Si)
The present invention relates to a high breakdown voltage, low loss diode using C) and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional diode using silicon, for example, in order to provide a withstand voltage of 1700 V or more, the concentration of an n-type active layer is set to 2 × 10 ¹⁴ cm ⁻³ or less, and the thickness thereof is set to 170.
Although it is necessary to be at least μm, such a diode has a practical problem because the forward voltage drop is large. Therefore, it has been attempted to use silicon carbide (SiC), which is excellent in material in terms of withstand voltage characteristics, as a constituent material of the diode.

On the other hand, in a conventional pn junction diode using silicon, it is relatively easy to obtain a high withstand voltage and a low on-resistance, but it has a drawback that a switching speed is slow, so that a high-speed switching operation is required. In such a case, a Schottky diode is preferable. For example, 600V
Although a pn junction diode of silicon can cope with a voltage of about the same level, there is a problem of noise due to accumulated charge due to a low response speed.

[0004] In view of the above, diodes using silicon carbide have been studied. However, a diode using silicon carbide has the following design and manufacturing difficulties. That is, when a reverse bias is applied to the diode, a current path is formed in a non-uniform portion of the interface with the metal due to the disorder of the semiconductor junction interface or the crystal defect, and the leak current increases. .
In order to prevent this, it is necessary to form a homogeneous interface.

[0005]

As described above, a high-breakdown-voltage diode using silicon carbide is expected as a diode having excellent withstand voltage characteristics and capable of high-speed switching. Due to the defect, the conventional silicon carbide diode has a problem that the leak current increases. In particular, to allow a large amount of current to flow, it is necessary to increase the junction area. However, if the area is increased, the probability that a portion having interface disorder or a crystal defect is included in the junction surface increases, thereby increasing the leakage current. Was.

Therefore, for example, it is possible to reliably obtain a silicon carbide diode having a withstand voltage of 600 V or more and a current of several tens of A or more at a forward current density of 100 A / cm ² or more. The emergence of technology was strongly desired.

SUMMARY OF THE INVENTION The present invention has been made to address such a problem, and it is possible to reliably realize a stable operation without causing an increase in leak current and to increase the area. It is another object of the present invention to provide a high breakdown voltage diode using silicon carbide which has a high yield.

[0008]

In order to achieve the above object, the present inventors first focused on micropipes and stacking faults (stacking faults) which are crystal defects in a SiC single crystal substrate. Micro pipe is <0001>
When a SiC single crystal is epitaxially grown on a SiC single crystal substrate having a plane orientation of [0001], the micropipe reaches the surface of the single crystal, which causes an increase in leakage current. . As a technique for solving the problem related to the micropipe, for example, a method of growing a SiC single crystal disclosed in Japanese Patent No. 2880460 is known. This method uses a SiC single crystal in which a crystal plane shifted from the {0001} plane by an angle α of 60 ° to 120 ° is exposed as a seed crystal, and more preferably, a {1-100} plane or ｛11-
In this case, an SiC single crystal having a 20 ° face exposed is used. By using such a seed crystal, the number of micropipes reaching the surface of the single crystal can be reduced.

However, the method of growing a SiC single crystal disclosed in Japanese Patent No. 2804860 has the following problems. In other words, the inventors of the invention described in the same gazette report that Physica Status Solid (b) (202)
No. pp. 163 to 175, 1997), when a SiC single crystal having an exposed {1-100} plane or {11-20} plane is used as a seed crystal,
Although the polymorphism can be controlled and the arrival at the surface of the micropipe can be suppressed, there is a problem that high-density stacking faults (stacking faults) are exposed on the surface of the SiC single crystal. This stacking fault spreads in a plane when growing the crystal. When a diode is manufactured using a SiC single crystal having the stacking fault exposed on the surface, a micropipe uses the SiC single crystal having the surface exposed. As in the case, a leak current occurs.

Therefore, the present inventors have focused on the fact that the leakage current of a diode can be reduced by reducing these micropipes and stacking faults, and completed the present invention.

(1) The present invention relates to a Schottky diode in which a Schottky electrode is joined to a 4H type SiC semiconductor.
The plane orientation of the C semiconductor is a {03-38} plane or a plane having an off angle within 10 ° from this plane.

In the Schottky diode of the present invention, the plane orientation of the SiC semiconductor in contact with the Schottky electrode is set to {0}.
The plane is a 3-38 ° plane or a plane having an off angle within 10 ° from this plane. Here, a SiC semiconductor having the {03-38} plane as an exposed surface will be described. Such S
When fabricating an iC semiconductor, a seed crystal made of 4H-type SiC with the {03-38} plane exposed is used,
A single crystal is grown to form a columnar SiC semiconductor. At this time, the exposed surface of the seed crystal has a micropipe extending <00.
01> direction, the micropipe reaches the side surface of the SiC single crystal when a 4H-type SiC single crystal is grown on such a seed crystal. Is suppressed. Also,
The exposed surface of the seed crystal ({03-38} plane) has an inclination of about 55 ° with respect to a plane where stacking faults spread, that is, a plane perpendicular to the <0001> direction.
If an H-type SiC single crystal is grown, stacking faults
A situation where the side surface of the C single crystal is reached and stacking faults reach the surface is suppressed.

By forming the Schottky electrode on the micropipe and the 4H SiC semiconductor having reduced stacking faults as described above, the leak current of the Schottky diode can be reduced, and stable operation can be ensured. As a result, the yield can be increased even when the area is increased.

The following is also considered as a reason why the leak current is reduced in the present invention. That is,
Unlike the [0001] plane, the 4H-type SiC [03-38] plane has a 4H-type periodic structure at the interface. Therefore, even if the interface atoms are affected by disturbance, the disturbance is minimized by the potential of the periodic structure appearing on the surface, and the generation of crystal defects is also suppressed. On the other hand, on the [0001] plane, only silicon atoms or carbon atoms appear on the surface.
Since the potential force of the periodic structure of C does not work, the interface is easily disturbed. 4H especially on the surface shifted from the closest surface
The fact that a high-performance interface is obtained by using the type SiC [03-38] plane is the result of the inventors' investigation of various plane orientations. The reason why particularly good results were obtained with 4H-type SiC [03-38] is thought to be due to the fact that bonds of atoms appear on the surface relatively periodically even though the surface is far from the closest surface. .

Further, the exposed surface of the SiC semiconductor is
The same effect as described above can be obtained even when the plane is inclined by an off angle of about 10 ° or less with respect to the {03-38} plane instead of the 8 ° plane.

(2) The pn junction diode of the present invention
In a pn junction diode formed by forming a pn junction in an H-type SiC semiconductor, a main junction surface between a p layer and an n layer is
The SiC semiconductor is formed on a {03-38} plane or a plane having an off angle within 10 ° from this plane.

In the pn junction diode of the present invention, since the pn junction is formed in the 4H-type SiC semiconductor having few defects as described above, the p layer and the n layer are particularly joined by using a smooth surface having few defects as an interface. Therefore, the leakage current can be reduced, stable operation can be surely realized, and the yield can be increased even when the area is increased.

(3) The pin junction diode of the present invention comprises:
Pi formed by forming a pin junction in a 4H SiC semiconductor
In the n-junction diode, the main junction between the p-layer and the i-layer and the main junction between the i-layer and the n-layer have a {03-38} plane of the SiC semiconductor or an off angle within 10 ° from this plane. It is characterized by being formed on the surface.

In the pin junction diode of the present invention, since the pin junction is formed in the 4H-type SiC semiconductor having a small number of defects as described above, the p-layer and the i-layer and the smooth surface having few defects are used as interfaces. Since the i-layer and the n-layer are respectively joined, the leakage current can be reduced,
A stable operation can be reliably realized, and the yield can be increased even in a large area.

(4) The method of manufacturing a Schottky diode according to the present invention is the method of manufacturing a Schottky diode in which a Schottky electrode is joined to a 4H type SiC semiconductor. Growing a 4H-type SiC single crystal on a seed crystal made of a SiC single crystal having an exposed surface having an off angle of 10 ° or less;
Forming a Schottky electrode on a −38 ° plane or a plane having an off angle within 10 ° from this plane.

In the method of manufacturing a Schottky diode according to the present invention, a Schottky diode is manufactured by forming a Schottky electrode on a 4H SiC semiconductor having few defects as described above. As a result, a stable operation can be reliably realized, and the yield can be increased even when the area is increased.

(5) The method of manufacturing a pn junction diode according to the present invention is a method of manufacturing a pn junction diode formed by forming a pn junction in a 4H type SiC semiconductor.
On a seed crystal made of an SiC single crystal having an 8 ° plane or a plane having an off angle within 10 ° from this plane exposed, 4H
Growing a p-type and n-type layer on the {03-38} plane of the grown 4H-type SiC single crystal or a plane having an off angle of 10 ° or less from the plane. Forming a pn junction such that a main bonding surface is located.

According to the method of manufacturing a pn junction diode of the present invention, a 4H SiC semiconductor having few defects
Since a pn junction diode is formed by forming an n-junction, the p-layer and n-layer are particularly connected with a smooth surface having few defects as an interface.
Since the layers are joined, leakage current can be reduced, stable operation can be reliably realized, and the yield can be increased even in a large area.

(6) The method for manufacturing a pin junction diode of the present invention is the same as the method for manufacturing a pin junction diode in which a pin junction is formed in a 4H SiC semiconductor.
Growing a 4H-type SiC single crystal on a seed crystal made of a SiC single crystal exposing a 3-38 ° plane or a plane having an off angle within 10 ° from the plane; # 03-3 of type SiC single crystal
Forming a pin junction such that a main joint surface between the p-layer and the i-layer and a main joint surface between the i-layer and the n-layer are located on the 8 ° plane or a plane having an off angle of 10 ° or less from this plane. And characterized in that:

In the method for manufacturing a pin junction diode of the present invention, a pin junction is formed by forming a pin junction on a 4H SiC semiconductor having few defects as described above. With p as the interface
Since the layer and the i-layer and the i-layer and the n-layer are respectively bonded, the leakage current can be reduced, stable operation can be reliably realized, and the yield can be increased even in a large area. .

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a Schottky diode, a pn junction diode, a pin junction diode, and a manufacturing method according to the present invention will be described below in detail with reference to the accompanying drawings. Further, in the present embodiment, an explanation will be given together with experimental results. In the following description, the lattice direction and the lattice plane of the crystal may be used. Here, the symbols of the lattice direction and the lattice plane will be described. The individual direction is indicated by [], the set direction is indicated by <>, the individual plane is indicated by (), and the set plane is indicated by {}. For negative indices, "-" (bar) is attached to the number in crystallography, but a negative sign is added before the number for convenience in preparing the specification.

[First Embodiment] FIG. 1 is a sectional view showing a Schottky diode 10 of the present embodiment. n type 4
H-type SiC (hereinafter referred to as SiC) on a substrate using {03-38} plane, and 4H with a plane orientation of 8 degrees off-axis from the {0001} plane
An Schottky diode 10 was fabricated by forming an n-type 4H SiC epitaxial growth layer on a SiC substrate. Incidentally, 4
The “H” of the H type has a hexagonal system, and “4” means a crystal structure in which four layers of atomic layers form one period.

The substrate 11 used for device fabrication was fabricated by slicing an ingot grown by the improved Rayleigh method and mirror-polishing. The substrates 11 were all n-type, and the carrier concentration determined by Hall effect measurement was 8 to 9
x10 ¹⁸ cm ^-3 , thickness 160-210 μm. In this device, since a current flows in the vertical direction, it is effective to lower the resistance of the substrate and use a thin substrate. An n-type SiC layer using nitrogen as a dopant was epitaxially grown thereon by a chemical vapor deposition (hereinafter, referred to as CVD) method. The growth layer is composed of a buffer layer 12 and a drift layer 13, and the buffer layer 1
2 has a donor concentration of 1 to 5 × 10 ¹⁷ cm ⁻³ and a thickness of 2 μm, and the drift layer 13 has a donor concentration of 6 to 8 × 10 ¹⁵ cm ⁻³ and a thickness of 12 μm. The surfaces of both the buffer layer 12 and the drift layer 13 are {03-38} planes. The main growth conditions are as follows. In the following, the flow rate is indicated by sccm, but when 1 sccm is converted into SI unit system,
The standard value is 1 × 10 ⁻³ l / min.

Buffer layer: SiH ₄ flow rate 0.30 sccm C ₃ H ₈ flow rate 0.30 sccm N ₂ flow rate 1 × 10 ⁻² sccm for {03-38} face 8x10 ⁻² sccm H ₂ flow rate for {0001} face 3.0slm Substrate temperature 1550 ° C Growth time 45 minutes

Drift layer: SiH ₄ flow rate 0.50 sccm C ₃ H ₈ flow rate 0.50 sccm N ₂ flow rate ⁴ × 10 ⁻⁴ sccm for {03-38} face ³ × 10 ⁻³ sccm for {0001} face H ₂ flow rate 3.0slm Substrate temperature 1550 ° C Growth time 200 minutes

Using the thus produced SiC epitaxial wafer, a Schottky diode 10 having the structure shown in FIG. 1 was manufactured. First, a p-type guard ring 14 having a width of 150 μm and a depth of 0.5 μm was provided around the Schottky electrode in order to suppress electric field concentration and dielectric breakdown at the end of the Schottky electrode. The guard ring 14 was formed by ion implantation of boron (hereinafter, referred to as B). The energy of B ion implantation is 30 to 280 keV and the total dose is 1.1 × 10 ¹³ cm
^-2 . As a mask for ion implantation, a 4 μm-thick aluminum (hereinafter referred to as Al) film or a 5 μm-thick silicon oxide (SiO ₂ ) film formed by a CVD method was used. Heat treatment for activation of implanted ions is 1500 in Ar gas atmosphere.
C., for 30 minutes. After the heat treatment, a thermal oxide film 19 is formed by wet oxidation at 1150 ° C. for 2 hours, and further, CVD
A silicon nitride (SiN) film 18 having a thickness of 800 nm was deposited by the method. Next, nickel (thickness: 200 nm; hereinafter, referred to as Ni) was deposited on the back surface, and heat treatment was performed at 1000 ° C. for 20 minutes to form an ohmic electrode. Then, titanium /
Aluminum (titanium: 200 nm / aluminum: 850 nm; titanium is hereinafter referred to as Ti) was deposited to form a Schottky electrode 15. The Schottky electrode 15 is a Ti layer 15a
And an Al layer 15b. Schottky electrode 15 is 500
Stabilization was performed by performing a heat treatment at 30 ° C. for 30 minutes. The surface of the diode was protected by applying polyimide 17. The overlap between the Schottky electrode 15 and the guard ring region 14 is 20 μm
A number of diodes were manufactured by changing the Schottky electrode diameter from 300 μmφ to 3 mmφ.

Here, the (03-38) plane of the SiC single crystal will be described with reference to FIG. As shown in the figure, the (03-38) plane has an inclination of about 35 ° (35.26 °) with respect to the [0001] direction, and has an inclination of about 55 ° with respect to a plane perpendicular to the [0001] direction.゜ (54.74 ゜).

Next, with reference to FIG. 3, a process of manufacturing the substrate 11 will be described. Usually, when growing a SiC single crystal, a micropipe extending in the <0001> direction or a <0>
Stacking faults extending in a plane perpendicular to the <001> direction are often contained inside the SiC single crystal. When an element is manufactured using a large number of micropipes or a SiC single crystal having stacking faults exposed on the surface, a leak current or the like may occur.

In the present embodiment, the seed crystal 30 having the {03-38} plane exposed is used for manufacturing the substrate 11. Then, the surface 30u of the seed crystal 30 is extended with the micropipe 42 (indicated by a dashed line in the figure) <0001>.
It will have an inclination of about 35 ° to the direction. Therefore, when the SiC single crystal 40 is grown to a certain extent, the micropipe 42 reaches the side surface 40s of the SiC single crystal 40, and the situation where the micropipe 42 reaches the surface 40u can be suppressed. Also, the surface 30u of the seed crystal 30
Has an inclination of about 55 ° with respect to a plane where the stacking faults 44 (shown by broken lines in the figure) spread, that is, a plane perpendicular to the <0001> direction. For this reason, when the SiC single crystal 40 is grown to some extent, the stacking fault 44 becomes the side face 4 of the SiC single crystal 40.
0s, and the situation where the stacking fault 44 reaches the surface 40u can be suppressed.

Then, the substrate 11 is obtained by slicing the SiC single crystal 40 in which the micropipes 42 and the stacking faults 44 hardly exist. The surface of the substrate 11 is a {03-38} plane following the seed crystal 30. The buffer layer 12 and the drift layer 13 grown on the substrate 11 have very few crystal defects following the substrate 11.

Also, as shown in FIG. 4, the surface 30u of the seed crystal 30 is not set to the {03-38} plane as in the present embodiment, but is turned off within about 10 ° with respect to the {03-38} plane. Similarly, when the surface is inclined by the angle α, the grown S
The situation where the micropipe 42 and the stacking fault 44 reach the surface 40u of the iC single crystal 40 can be suppressed. Further, the off angle α is preferably within 5 °, more preferably within 3 °. In other words, as the surface of the seed crystal approaches the {03-38} plane, the micropipe 4
2 and the stacking fault 44 can be reliably prevented from reaching. Also, the surface 30 of the seed crystal 30
u is the off-angle α within about 10 ° with respect to the {03-38} plane.
When the surface is tilted only, the surface of the buffer layer 12 and the drift layer 13 grown on the
The plane is inclined at an off angle α with respect to the −38 ° plane.

Next, referring to FIG. 5, typical current-voltage characteristics of the produced Schottky diode (1 mmφ) will be described. As for the forward characteristics, the dependence on the plane orientation of the crystal was small, and a good value of on-resistance of 3 to 4 mΩ · cm ² was obtained. The ideal factor n value obtained from the semilogarithmic plot of the forward characteristic is 1.02 to
1.05eV, barrier height is 1.08eV on 4H type SiC {0001} plane, 4
It was 1.16 eV on the H-type SiC {03-38} plane. 1 for reverse characteristics
A withstand voltage of 500 V or more was achieved, and the leak current when 1000 V was applied was as small as about 10 ^-4 A / cm ^-2 .

In a diode having a small Schottky electrode of about 300 μmφ to about 1 mmφ, similar diode characteristics were obtained on a 4H-type SiC substrate having an off angle of 8 degrees from the {0001} plane, but the electrode area was large. In the diode, there was a large difference between the two.

FIG. 6 shows a Schottky diode fabricated using a growth layer on a 4H SiC {03-38} substrate and a 4H SiC substrate having an off angle of 8 degrees from the {0001} plane. Pressure resistance
4 is a graph showing electrode area dependence of (average value). For each electrode area, at least 20 diodes were measured to determine the average withstand voltage. A Schottky diode fabricated using a growth layer on a 4H SiC substrate having an off angle of 8 degrees from the {0001} plane has an electrode area of 7.9 × 10 ⁻³ cm ²
If it exceeds (1 mmφ), the withstand voltage rapidly decreases. On the other hand, a diode fabricated on a 4H SiC {03-38} substrate maintains a high breakdown voltage even with an electrode area of 7 × 10 ⁻² cm ² (3 mmφ). When the yield was calculated based on the breakdown voltage of 1200 V with this 3 mmφ diode, the yield was 13% for the 4H SiC {0001} diode and 72% for the 4H SiC {03-38} diode.

When not only the breakdown voltage but also the average value of the leak current density when a voltage of 1000 V is applied in the reverse direction is compared with a diode having an electrode diameter of 3 mmφ, the 4H-type SiC having a plane orientation with an off angle of 8 degrees from the {0001} plane is obtained. 9x10 for diode fabricated on substrate
^-2 A / cm ^-2 , 3x10 ^-4 A / cm ² for diode on {03-38}
And a difference of two digits or more was recognized. This is 4H SiC
It is considered that the use of the {03-38} plane suppressed the penetration of micropipes and screw dislocations from the substrate, resulting in a high-quality SiC crystal. Also, 4H SiC
The use of the {03-38} plane improves the flatness of the growth surface and the surface of the guard ring formed by ion implantation, and contributes to the effect of reducing the electric field concentration at the Schottky electrode / SiC interface. Seems to be. In this example, the guard ring was formed by B ion implantation, but the same effect was obtained when Al ion implantation was used.

As described above, in the present embodiment, the leak current of the Schottky diode can be reduced, stable operation can be reliably realized, and the yield can be increased even in a large area.

[Second Embodiment] Next, referring to FIG.
A second embodiment of the present invention will be described. This embodiment relates to a Schottky diode. As an example, the plane orientation in which an n ^- type layer is laminated as an intermediate layer is {03-38}
A 4H-type SiC Schottky diode having a plane and a {0001} plane was fabricated.

A low impurity concentration n ⁻ -type epitaxial layer 36 was grown on a high impurity concentration n-type SiC substrate 34, and a low impurity concentration n ⁻ -type epitaxial layer 38 was further grown. Then, a Schottky electrode 37 of Ti / Al and an ohmic electrode 35 of Ni were formed on the upper and lower sides of the stacked body to complete the diode. The impurity concentration of the SiC substrate 34 is 1 ×
10 ¹⁹ cm ⁻³ , thickness 330 μm, n ⁻ type epitaxial layer 38
Impurity concentration was ^{3 × 10 1 5 cm -3,} 5nm and 10n a thickness of
m. For comparison, a diode without an n ⁻ -type layer was also manufactured.

It is known that the leakage current can be suppressed by forming the n ⁻ -type layer as described above, but the on-resistance increases when the n ⁻ -type layer is formed. In the present embodiment, in the diode with the plane orientation of {03-38} on which the Schottky electrode is formed, even when the thickness of the n ⁻ type layer is 5 nm,
In the diode with the plane orientation of {0001} on which the Schottky electrode was formed, the same effect of suppressing the leakage current as when the thickness of the n ⁻ -type layer was set to 10 nm was obtained. This is because
By using the 4H type {03-38} plane, penetration of micropipe and screw transition from the substrate was suppressed, and the flatness of the n ^- type epitaxial layer and n ^- type epitaxial layer and the Schottky interface was improved. Can be considered.

[Third Embodiment] Next, referring to FIG.
A third embodiment of the present invention will be described. In the present embodiment, pn
It relates to a junction diode. As examples and comparative examples, n formed on an n-type 4H-type SiC (03-38) substrate 21 and a 4H-type SiC (0001) 8 ° off substrate (comparative example), respectively.
Implantation of Al ions into the 4H-type SiC epitaxial growth layer 22 to form a planar pn junction diode 20.
Was prepared. The main bonding surface (the surface extending in the horizontal direction in the figure) of the p-type SiC layer and the n-type SiC layer is a {03-38} plane.

The substrate 21 used for manufacturing the device was manufactured by slicing an ingot grown by the improved Rayleigh method and mirror-polishing it. The substrates 21 were all n-type, and the carrier concentration determined by Hall effect measurement was 8 to 9
x10 ¹⁸ cm ^-3 , thickness 160-210 μm. On top of this, CVD
The nitrogen-doped n-type SiC layer 22 was epitaxially grown by the method. The growth layer 22 includes the buffer layer 22a and the drift layer 2
2b, and the buffer layer 22a has a donor concentration of 1 to 5 × 10
¹⁷ cm ^-3 , thickness 4 μm, drift layer 22 b has a donor concentration of 1
22 × 10 ¹⁵ cm ⁻³ , and the film thickness is 75 μm. The main growth conditions are as follows.

Buffer layer: SiH ₄ flow rate 3.0 sccm C ₃ H ₈ flow rate 1.5 sccm N ₂ flow rate 8 × 10 ⁻² sccm for {03-38} face 6 × 10 ⁻¹ sccm H ₂ flow rate for {0001} face 3.0slm Substrate temperature 1750 ° C Pressure 10kPa Growth time 10min

The drift layer: SiH ₄ flow rate 15 sccm C ₃ H ₈ flow rate 4.5sccm N ₂ 4x10 ^-2 sccm H ₂ flow 3.0slm substrate temperature when 1x10 ^-3 sccm {0001} plane when the flow rate {03-38} plane 1750 ℃ pressure 10kPa growth time 180min

In this experiment, high-speed growth was performed at a high temperature so that a high-purity, thick-film growth layer could be formed in a short time in order to obtain a high breakdown voltage. Using the SiC epitaxial wafer thus manufactured, a planar type having a structure shown in FIG.
A pn junction diode was fabricated. First, the p-type anode 24
To form Al ions at 720 keV, 400 keV, and 280 keV.
V, 160 keV, 80 keV, 40 keV, and 20 keV were injected in seven stages.
The total dose is 4x10 ¹⁵ cm ^-2 . The dose of each implantation energy is set to 2.7x10 ¹³ cm ^-2 (720keV) and 1.8x10 ¹³ cm ^-2 (400keV
V), 1.2x10 ¹³ cm ^-2 (280keV), 1.0x10 ¹³ cm ^-2 (160keV),
7.2x10 ¹⁴ cm ^-2 (80 keV), 4.2x10 ¹⁴ cm ^-2 (40 keV), 1.3x10
^By setting it to ¹⁴ cm ^-2 (20 keV), the p of about 0.7 μm
High concentration layer 25 with a surface of about 0.2 μm of 10 ²⁰ cm ^-3 or more in the mold layer
Was formed.

Next, the electric field collection at the end of the p-type anode region
Medium, around 300μm width around this to suppress dielectric breakdown,
A p-type guard ring 23 having a depth of 0.7 μm was provided. Gardley
The ring 23 was also formed by ion implantation of Al. Al ion injection
Input energy is also total in seven stages of 20 to 720 keV
The dose is 1.0x10¹³cm^-2It is. At the time of guard ring formation
Designed the injection layer to have a box profile
Was. All ion implantation is performed at room temperature, and ion implantation mask
Al (5 μm thick) or SiO formed by CVD _Twofilm
(Thickness: 6 μm). Heat treatment for implanted ion activation
Was performed in an Ar gas atmosphere at 1500 ° C. for 30 minutes. Heat treatment
After processing, a thermal oxide film is formed by wet oxidation at 1150 ° C for 2 hours.
And then deposit an 800 nm thick SiO2 film 31 by CVD.
Stacked. Next, Ni (thickness: 200 nm) on the back surface and Ni / Al (Ni:
 (200 nm / Al: 1200 nm) and deposited in an Ar atmosphere at 1000 ° C and 20 ° C.
Heat treatment for 2 minutes to form ohmic electrodes 26 and 27
did. Diode 28 is coated on the surface of the diode
Protected. The size of the p-type anode is 3mm square (area 0.09cm^Two)
And

FIG. 9 shows typical current-voltage characteristics of the manufactured planar pn diode (3 mm square). Forward direction,
In both the reverse characteristics, a clear plane orientation dependency was observed.

First, focusing on the forward characteristics, 4H SiC
A diode manufactured on the {0001} plane has a relatively low current flow, and at about 5 A or more, electric conduction is dominated by a series resistance (on resistance) of about 12 mΩ · cm ² . On the other hand, 4H SiC
The on-resistance of the diode fabricated on the {03-38} plane is 2
The current is very small, about ³ mΩ · cm ^2, and the current sharply increases in a region higher than the rising voltage of about 2.8 V. 4H type SiC ｛03-
In the diode fabricated on the 38 mm plane, a high current of 30 A (333 A / cm ² ) was achieved with a voltage drop of 3.9 V.
This is because, when a 4H SiC {0001} surface is used, the high-concentration p-type layer formed on the surface of the p-type anode has a low electrical activation rate and thus has a high resistance. This is probably because the contact resistance of the electrode to the layer is high. 4H type SiC ｛0
When a 3-38 ° plane is used, a low-resistance and high-concentration p-type layer can be formed even at room temperature implantation, so that the resistance and contact resistance at this portion can be significantly reduced.

In the reverse characteristics, the withstand voltage of the diode using the 4H-type SiC {0001} plane is limited to 5210 V, while the diode using the 4H-type SiC {03-38} plane is 8860 V.
A high withstand voltage of V could be obtained. 4 at reverse bias
The leakage current when 500V is applied is 4H SiC {0001}
3x10 ^-5 A / cm ² , 4H SiCSi03-3
It was 5 × 10 ⁻⁸ A / cm ^{2 for} the diode using the 8｝ plane, and again a clear difference was seen.

Focusing on the avalanche current at the time of dielectric breakdown, a diode using a 4H type SiC {03-38} plane has a physical breakdown of the diode even if the current is increased to 5 A (55 A / cm ² ) at the time of dielectric breakdown. Stable characteristics that did not reach the limit were obtained. However, a diode using 4H type SiC {0001} has 1A (11A / cm
Beyond ² ), the majority of the diodes had rectification characteristics that deteriorated significantly due to physical destruction. This is 4H type SiC ｛03-
It is considered that the use of the 38 ° plane suppressed the penetration of micropipes and screw dislocations from the substrate, and resulted in a high-quality SiC crystal.

+4 V of the diode thus manufactured
Long-term reliability of switching characteristics between-and -1000V and off characteristics (-3000V) at high temperature (300 ° C) did not show any particular orientation dependence, but long-term on characteristics (200A / cm ² ) Differences in reliability due to plane orientation were observed.

FIG. 10 shows a forward direction of a pn diode fabricated using a growth layer on a substrate using a 4H SiC {03-38} plane or a substrate 8 degrees off from a 4H SiC {0001} plane. Current
This is a plot of the forward voltage drop when 18 A (200 A / cm ² ) is kept flowing for a long time. In the diode using the 4H-type SiC {0001} plane, the voltage drop started to increase from around 3000sec, and after 10,000sec, it increased from the initial 3.6V to 4.7V. However, in the diode using the 4H type SiC {03-38} surface, the voltage drop is 3.7V even after 10,000 seconds,
Almost no deterioration. To investigate the cause, a diode subjected to a long-term reliability test was mounted on a transmission electron microscope (TE
Observed by (M), the diode using deteriorated 4H-type SiC {0001} plane has many stacking faults on the [0001] plane, and 4H-type SiC {03-38} plane was used. It was found that such a stacking fault was not generated in the diode.

Although the generation mechanism of this stacking fault is not clear at present, in a light emitting diode of a III-V group semiconductor,
It is known that the energy radiated by carrier recombination at the time of forward bias generates partial dislocations in a portion where crystal distortion is large, and this partial dislocation extends into a close-packed plane, thereby forming stacking faults. . 4H type SiC ｛0
In the case of the 001 ° plane, the same phenomenon occurs at the time of forward bias, and it is presumed that stacking faults have occurred on the [0001] plane corresponding to the closest packed plane. It is considered that the influence of this stacking fault shortened the minority carrier lifetime and increased the forward voltage drop. The reason why the occurrence of such stacking faults is suppressed in the case of a diode using a 4H SiC {03-38} plane is as follows.
In this plane, since Si and C atoms are appropriately mixed, the strain at the pn junction interface is very small, and defects such as partial dislocations and stacking faults are unlikely to occur. Further, since the damage can be almost completely removed by the annealing heat treatment after the ion implantation, a very small number of strains or point defects which trigger the generation of defects also contributes. In this embodiment, the guard ring is formed by Al ion implantation, but the same effect can be obtained by using B ion implantation.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment,
High breakdown voltage JBS (Junc
tion Barrier Schottky) Diode.

As examples and comparative examples, n-type 4
JBS diodes were fabricated using n-type 4H-SiC epitaxial growth layers formed on H-SiC (03-38) and 4H-SiC (0001) 8 ° off substrates. Substrate 51 used for device fabrication
Was prepared by slicing an ingot grown by the modified Rayleigh method and mirror polishing. Substrate 51
Are all n-type, the carrier density determined by Hall effect measurement is 8 × 10 ¹⁸ cm ⁻³ , and the thickness is 180 μm. On top of this, CV
The nitrogen-doped n-type SiC layers 52 and 53 were epitaxially grown by the D method. The growth layer includes a buffer layer 52 and a drift layer 53, and the buffer layer 52 has a donor density of 2 to 5 × 10 ¹⁷ cm.
^-3 , the film thickness is 2 μm, and the drift layer 53 has a donor density of 4 × 10 ¹⁵ cm.
^-3 , the film thickness is 18 μm. The main growth conditions are as follows.

[0060] Buffer layer: SiH ₄ flow rate 0.30sccm C ₃ H ₈ flow rate 0.30Sccm N2 flow rate (03-38) when 2x10 ^-2 sccm (0001) plane when the plane 2x10 ^-1 sccm H ₂ flow 3.0slm substrate temperature 1550 ℃ Growth time 45 minutes

Drift layer: SiH ₄ flow rate 0.60 sccm C ₃ H ₈ flow rate 0.60 sccm N ₂ flow rate 3 × 10 ⁻⁴ sccm for (03-38) face 2 × 10 ⁻³ sccm for (0001) face H ₂ flow rate 3.0 slm 1550 ° C Growth time 250 minutes

Using the SiC epitaxial wafer thus manufactured, a JBS diode 50 having the structure shown in FIG. 11 was manufactured. In a normal Schottky diode, there is a problem that a high electric field is applied near the interface of the Schottky barrier at the time of reverse bias, and the leakage current increases. However, in the JBS diode, the p-type region 55 and the n-type
Since the depletion layer of the n-junction spreads, the Schottky interface is shielded by this depletion layer if properly designed, and the electric field at the interface of the Schottky barrier is greatly reduced. As a result, the leakage current is reduced. .

In this embodiment, the p-type stripe region 55 for JBS and the guard ring 54 for alleviating the electric field concentration at the end of the Schottky electrode are made of aluminum (Al) of the same process.
It was formed by ion implantation. The p-type stripe region 55 for JBS has a width of 8 μm and an interval of 12 μm, and the width of the p-type guard ring 54 is 150 μm. About 0.5μ in depth
m. The energy of Al ion implantation for forming the p-type stripe 55 or the guard ring 54 is 40 to 560 keV, and the total dose is 1.0 × 10 ¹³ cm ⁻² . As a mask for ion implantation, a SiO ₂ film (5 μm in thickness) formed by CVD was used. All the ion implantations were performed at room temperature, and the heat treatment for activating the implanted ions was performed at 1500 ° C. for 30 minutes in an argon gas atmosphere. After annealing, a thermal oxide film 56 was formed by wet oxidation at 1150 ° C. for 2 hours, and a 1 μm thick SiN film 57 was further deposited by CVD.

Next, Ni (thickness: 200 nm) is vapor-deposited on
Heat treatment was performed at 20 ° C. for 20 minutes to form an ohmic electrode 58. Next, Ni / Al (Ni: 200 nm / Al: 900 nm) was deposited on the surface side to form a Schottky electrode 59. The Schottky electrode 59 includes a Ni layer 59a and an Al layer 59b. The Schottky electrode was stabilized by performing a heat treatment at 500 ° C. for 30 minutes. The surface of the diode was protected by applying polyimide 61. Schottky electrode 59 and guard ring region 54
Are 20 μm, and the Schottky electrode diameter is 2 to 2.
5 mmφ. Photolithography technology was used to form these guard rings and electrode patterns.

FIG. 12 shows the manufactured JBS diode 50.
(2 mmφ) shows a typical current-voltage characteristic. As for the forward characteristics, the dependence on the plane orientation of the crystal is small, and the on-resistance is 8-9.
A good value of mΩcm ² was obtained. The ideal factor n value obtained from the semi-log plot of the forward characteristic is 1.02 to 1.05,
The barrier height was 1.68 eV on the 4H-SiC (0001) plane and 1.76 eV on the 4H-SiC (03-38) plane. In the reverse characteristics of the diodes, the leakage current when applying -1000 V is 10 ^-7 A /
It is very small, about ² cm2, and shows the effect of the JBS structure.

Also, when the turn-off characteristics of the diode in a conducting state of 100 A / cm ² were measured, high-speed switching of 10 ns or less and a very small reverse recovery current were observed in all cases. It was confirmed that the switching characteristics were obtained. However, 40
The average withstand voltage obtained by measuring more than two diodes is 4H-S
The difference was 2540 V on the iC (03-38) substrate and 2020 V on the 4H-SiC (0001) 8 ° off-substrate. In the case of a diode having a large diameter of 5 mm, the difference becomes more remarkable, while the 4H-SiC (03-38) diode maintains an average withstand voltage of 2310 V, while the 4H-SiC (0001) 8 ° off substrate The average withstand voltage dropped to 1470V. This is 4H-SiC
It is considered that the use of the (03-38) plane suppressed the penetration of micropipes and screw dislocations from the substrate, and obtained a high-quality SiC crystal. In addition, 4H-SiC (03-
By using the 38) plane, the flatness of the growth surface and the surface of the p-type stripe and guard ring formed by ion implantation are improved, and the effect of reducing the electric field concentration at the Schottky electrode / SiC interface also contributes Seems to be doing. In this embodiment, the guard ring is formed by Al ion implantation, but the same effect can be obtained by using B ion implantation.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to FIG. In this embodiment,
The present invention relates to a pn (pin) diode which is a development of the Schottky diode. As Examples and Comparative Examples, n-type 4H-SiC (03-38), and 4H-SiC (0001) 8 ° off n-type 4H-SiC, p-type 4H-SiC continuously epitaxial growth on 8 ° off substrate, epitaxial A pn (pin) junction diode 70 was manufactured. the main interface between the p-layer and the i-layer, and i
Main bonding surface of layer and n-layer (surface spreading in the horizontal direction in the figure)
Is the {03-38} plane.

The substrate 71 used for device fabrication was fabricated by slicing an ingot grown by the modified Rayleigh method and polishing the mirror to a mirror surface. The substrates 71 were all n-type, and the carrier density determined by Hall effect measurement was 9 × 10
¹⁸ cm ^-3 and thickness 200 μm. On this, a nitrogen-doped n-type SiC layer and an aluminum-doped p-type SiC layer were successively epitaxially grown by a CVD method. The n-type growth layer is a buffer layer 7
The buffer layer 72 has a donor density of 3 to 10 × 10 ¹⁷ cm ⁻³ and a thickness of 4 μm, and the drift layer 73 has a donor density of about 1 × 10 ¹⁵ cm ⁻³ and a thickness of 88 μm. Also, p
The type growth layer is composed of a p-type junction layer 74 and a p ⁺ -type contact layer 75. The p-type junction layer 74 has an acceptor density of 3 × 10 ¹⁸ cm ⁻³ ,
The film thickness is 3 μm, the acceptor density of the p ⁺ type contact layer 75 is about 1 × 10 ²⁰ cm ⁻³ , and the film thickness is 0.8 μm. The main growth conditions are as follows.

Buffer layer: SiH4 flow rate 3.0 sccm C3H8 flow rate 1.5 sccm N2 flow rate 2 × 10 ^-1 sccm for (03-38) face ¹ sccm H2 flow rate for (0001) face 3.0 slm Substrate temperature 1750 ° C. Pressure 100 Torr Growth time 10 minutes

[0070] drift layer: SiH4 flow rate 15 sccm C3H8 flow rate 4.5 sccm N2 flow rate (03-38) when 1x10 ^-3 sccm (0001) plane when the plane 4x10 ^-2 sccm H2 flow 3.0slm substrate temperature 1750 ° C. The pressure 100Torr Growth time 200 Minute

P-type bonding layer: SiH4 flow rate 3.0 sccm C3H8 flow rate 2.0 sccm Al (CH3) 3 flow rate (03-38) plane 9x10 ^-2 sccm (0001) plane 4x10 ^-2 sccm H2 flow 3.0slm Substrate temperature 1750 ℃ Pressure 100Torr Growth time 8min

P + type contact layer: SiH4 flow rate 2.0 sccm C3H8 flow rate 2.0 sccm Al (CH3) 3 flow rate (03-38) 1.2 sccm (0001) face 6 × 10 ^-1 sccm H2 flow rate 3.0 slm Substrate temperature 1750 ° C. Pressure 100 Torr Growth time 3 minutes

In this experiment, high-speed, high-temperature growth was performed so that a high-purity, thick-film growth layer could be formed in a short time in order to obtain a high breakdown voltage. Using the SiC epitaxial wafer thus manufactured, a planar pn diode 70 having a structure shown in FIG. 13 was manufactured.

First, in order to perform element isolation of the diode, it was processed into a mesa structure by reactive ion etching (RIE). NF ₃ and O ₂ are used for RIE etching gas
Etching was performed to a depth of about 8 μm under the conditions of 0.05 Torr and high frequency power of 260 W. At this time, an SiO ₂ film (thickness: 10 μm) deposited by CVD was used as a mask material.

Next, in order to reduce the electric field concentration at the bottom of the mesa formed by etching, a width of 300 μm is formed at the bottom of the mesa.
A p-type guard ring 76 having an m depth of 0.7 μm was provided. The guard ring 76 was formed by Al ion implantation. The energy of Al ion implantation is seven steps of 20 to 720 keV and the total dose is 1.2 × 10 ¹³ cm ⁻² . When forming the guard ring,
The injection layer was designed to have a box profile. All ion implantations are performed at room temperature.
Al (thickness: 5 μm) was used. The heat treatment for activating the implanted ions was performed at 1500 ° C. for 30 minutes in an argon gas atmosphere. After annealing, a thermal oxide film is formed by wet oxidation at 1150 ° C for 2 hours, and then a 800 nm thick Si
An O ₂ film 77 was deposited.

Next, Ni (thickness: 200 nm) was formed on the back surface, and Ni /
Al (Ni: 200 nm / Al: 2400 nm) was deposited, and heat treatment was performed at 1000 ° C. for 20 minutes to form ohmic electrodes 78 and 79, respectively. The ohmic electrode 79 is composed of the Ni layer 79 a and the Al layer 7.
9b. The surface of the diode was protected by applying polyimide 80. pn junction size is 3mm
It is a corner (area 0.09 cm ² ). Although the guard ring 76 is formed by Al ion implantation in this embodiment, the same effect can be obtained by using B ion implantation.

In the pn (pin) junction diode 70, the junction surfaces (the surfaces extending in the horizontal direction in the figure) of the respective layers 71 to 75 are all {03-38} surfaces.

FIG. 14 shows typical current-voltage characteristics of the manufactured epitaxial pn diode (3 mm square). First, focusing on forward characteristics, 4H-SiC (03-38), (00
01) Any diodes fabricated on the surface and excellent characteristics are obtained, the ON resistance is very small and 2~3mΩ · cm ^2, the current rapidly increases at higher than the rising voltage of about 2.8V region . A high current of 30 A (333 A / cm ² ) was achieved with a voltage drop of 3.78 V.

On the other hand, in the reverse characteristics, a clear difference depending on the plane orientation was observed. Withstand voltage of 4H-SiC (0001) diode is 5840V
4H-SiC (03-38) diode, a high withstand voltage of 9820V was obtained. Leakage current when applying -5000 V is 6x10 ^-5 A / cm for 4H-SiC (0001) diode
² , 4H-SiC (03-38) diode was 3 × 10 ⁻⁸ A / cm ² , again showing a large difference. Focusing on the avalanche current at the time of dielectric breakdown, the 4H-SiC (03-38) diode has a stable characteristic that does not lead to physical breakdown of the diode even if the current is increased to 5 A (55 A / cm ² ) at the time of dielectric breakdown. Obtained. However, most of the 4H-SiC (0001) diodes have a rectification characteristic that is significantly deteriorated due to physical destruction when the current exceeds 1 A (11 A / cm ² ).

FIG. 15 shows that the temperature dependence of the breakdown voltage is 0 ° C. to 30 ° C.
An example of the results of evaluation between 0 ° C is shown. 4H-SiC (03-38)
Among the diodes, 80% or more of the diodes exhibited a positive temperature coefficient in which the breakdown voltage increased with the temperature. This property is
It is extremely important in a power device that generates a great deal of heat due to Joule heat, and it is no exaggeration to say that reliability cannot be guaranteed unless this characteristic can be secured. Therefore,
On 4H-SiC (03-38) surface, it can be said that an excellent diode can be manufactured with high yield.

On the other hand, the 4H-SiC (0001) diode exhibited a characteristic that the withstand voltage showed a positive temperature coefficient did not reach 50% of the entire diode, and more than half of the diodes showed a characteristic that the withstand voltage decreased as the temperature increased. Although the essential factors that determine the temperature dependence of the breakdown voltage are not yet clear, it is considered that a positive temperature coefficient is exhibited as long as avalanche breakdown occurs if physical properties inherent to the semiconductor are exhibited. Therefore, the reason why the breakdown voltage exhibits a negative temperature coefficient is presumed to be the influence of structural defects (such as dislocations) existing in the crystal.

As described above, by using the 4H-SiC (03-38) plane, an excellent diode having a high withstand voltage and a positive temperature coefficient of withstand voltage can be manufactured even in a large area. Is very promising for fabricating large capacity devices. It is considered that the main reason for this is that penetration of micropipes and screw dislocations from the substrate was suppressed, and a high-quality SiC crystal was obtained.

As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments.

[0084]

As described above, according to the present invention,
The leakage current of the diode can be reduced, stable operation can be reliably realized, and the yield can be increased even in a large area.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a Schottky diode according to a first embodiment.

FIG. 2 is an explanatory diagram of a (03-38) plane.

FIG. 3 shows that Si is placed on a seed crystal having a plane orientation of {03-38}.
It is sectional drawing which shows the state of the micropipe and stacking fault when growing C single crystal.

FIG. 4 is a diagram showing a plane inclined at an off angle α from a {03-38} plane.

FIG. 5 is a diagram showing typical current-voltage characteristics of the Schottky diode of the first embodiment.

FIG. 6 is a graph showing the electrode area dependence of the breakdown voltage of the Schottky diode of the first embodiment.

FIG. 7 is a cross-sectional view illustrating a Schottky diode according to a second embodiment.

FIG. 8 is a cross-sectional view illustrating a pn junction diode according to a third embodiment.

FIG. 9 is a diagram showing typical current-voltage characteristics of a pn junction diode according to a third embodiment.

FIG. 10 is a diagram showing a forward voltage drop when a forward current of 18 A (200 A / cm ² ) is continuously supplied to the pn junction diode of the third embodiment.

FIG. 11 shows a JBS (Junction Barrier Schot) according to a fourth embodiment.
tky) FIG.

FIG. 12 is a diagram showing typical current-voltage characteristics of the JBS diode according to the fourth embodiment.

FIG. 13 is a sectional view showing a pn (pin) diode according to a fifth embodiment.

FIG. 14 is a diagram showing typical current-voltage characteristics of a pn (pin) diode according to a fifth embodiment.

FIG. 15 is a diagram showing the results of evaluating the temperature dependence of the breakdown voltage of the diode of the fifth embodiment between 0 ° C. and 300 ° C.

[Explanation of symbols]

10: Schottky diode, 11: n ⁺ type substrate, 12
... n-type buffer layer, 13 ... n-type drift layer, 14 ... guard ring region, 15 ... Schottky electrode, 18 ... ohmic electrode, 20 ... pn junction diode, 21 ... n ⁺ type substrate, 2
2a ... n-type buffer layer, 22b ... n-type drift layer, 23 ...
p-type guard ring, 24: p-type anode, 25: high concentration layer, 30: seed crystal, 42: micropipe, 44: stacking fault, 50: JBS diode, 70: pn (pin) junction diode.

 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 000005979 Mitsubishi Corporation 2-6-3 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Yoichi Miyanagi 8-1-1404 Daitocho, Ashiya-shi, Hyogo (72) Invention Koji Nakayama D-408 D-408 5-3 Furuedai, Suita-shi, Osaka (72) Inventor Hiroshi Shiomi 1-6-19, Haramachi, Suita-shi, Osaka (72) Inventor Tsunebuo Kimoto Matsuhira Chikuzen, Momoyama-cho, Fushimi-ku, Kyoto, Kyoto 1-39-605 (72) Inventor Hiroyuki Matsunami 1-9 Nishiyama Adachi, Yawata-shi, Kyoto F-term (reference) 4M104 AA03 BB05 BB14 CC01 CC03 DD26 DD34 DD79 FF13 FF35 GG02 GG03 HH20 5F045 AB06 AC01 AF02 AF13 BB12 BB16 DA53 DA61

Claims (6)

[Claims] 1. A Schottky diode in which a Schottky electrode is joined to a 4H-type SiC semiconductor, wherein a plane orientation of the SiC semiconductor in contact with the Schottky electrode is {03-38} plane or 10 degrees from this plane. A Schottky diode having a surface having an off angle of less than or equal to °. 2. A pn junction diode in which a pn junction is formed in a 4H-type SiC semiconductor, wherein a main junction surface between a p-layer and an n-layer is a {03-38} surface of the SiC semiconductor or from this surface. A pn junction diode formed on a surface having an off angle of 10 ° or less. 3. A pin junction diode in which a pin junction is formed in a 4H type SiC semiconductor, wherein a main junction surface between a p-layer and an i-layer and a main junction surface between an i-layer and an n-layer are formed of the SiC semiconductor. A pin junction diode formed on a 03-38 ° plane or a plane having an off angle of 10 ° or less from this plane. 4. A method of manufacturing a Schottky diode in which a Schottky electrode is joined to a 4H-type SiC semiconductor, wherein a {03-38} plane or a plane having an off angle within 10 ° from this plane is exposed. Growing a 4H-type SiC single crystal on the seed crystal made of the obtained SiC single crystal;
Forming a Schottky electrode on an 8 ° plane or a plane having an off angle of 10 ° or less from the plane, a method for manufacturing a Schottky diode. 5. A method of manufacturing a pn junction diode in which a pn junction is formed in a 4H type SiC semiconductor, wherein a {03-38} plane or a plane having an off angle within 10 ° from this plane is exposed. Growing a 4H-type SiC single crystal on a seed crystal made of a SiC single crystal;
In order that the main bonding surface of the p-layer and the n-layer is located on the 38 ° plane or a plane having an off angle within 10 ° from this plane,
forming an n-junction. A method for manufacturing a pn-junction diode, comprising: 6. A method of manufacturing a pin junction diode in which a pin junction is formed in a 4H type SiC semiconductor, wherein a {03-38} plane or a plane having an off angle within 10 ° from this plane is exposed. Growing a 4H-type SiC single crystal on a seed crystal made of a SiC single crystal;
Forming a pin junction such that the main junction between the p-layer and the i-layer and the main junction between the i-layer and the n-layer are located on the 38 ° plane or a plane having an off angle of 10 ° or less from this plane. A method for manufacturing a pin junction diode, comprising: