JP2008074664A - Epitaxial silicon carbide single crystal substrate and its producing method - Google Patents

Epitaxial silicon carbide single crystal substrate and its producing method Download PDF

Info

Publication number
JP2008074664A
JP2008074664A JP2006255674A JP2006255674A JP2008074664A JP 2008074664 A JP2008074664 A JP 2008074664A JP 2006255674 A JP2006255674 A JP 2006255674A JP 2006255674 A JP2006255674 A JP 2006255674A JP 2008074664 A JP2008074664 A JP 2008074664A
Authority
JP
Japan
Prior art keywords
single crystal
silicon carbide
carbide single
epitaxial
crystal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006255674A
Other languages
Japanese (ja)
Other versions
JP4954654B2 (en
Inventor
Takashi Aigo
崇 藍郷
Mitsuru Sawamura
充 澤村
Noboru Otani
昇 大谷
Taizo Hoshino
泰三 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP2006255674A priority Critical patent/JP4954654B2/en
Publication of JP2008074664A publication Critical patent/JP2008074664A/en
Application granted granted Critical
Publication of JP4954654B2 publication Critical patent/JP4954654B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an epitaxial silicon carbide single crystal substrate having a high quality silicon carbide single crystal thin film with few defects on a silicon carbide single crystal substrate and to provide its producing method. <P>SOLUTION: The epitaxial silicon carbide single crystal substrate is characterized by having the silicon carbide single crystal thin film for suppressing the occurrence of epitaxial defects on the silicon carbide single crystal substrate. In the producing method, the Ra value of the surface roughness of the silicon carbide single crystal thin film is 0.5 nm or more and 1.0 nm or less and the atomic number ratio (C/Si) of carbon and silicon is 1.0 or less. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、エピタキシャル炭化珪素(SiC)単結晶基板及びその製造方法に関するものである。   The present invention relates to an epitaxial silicon carbide (SiC) single crystal substrate and a method for manufacturing the same.

炭化珪素(SiC)は、耐熱性及び機械的強度に優れ、物理的、化学的に安定なことから、耐環境性半導体材料として注目されている。また、近年、高周波高耐圧電子デバイス等の基板としてSiC単結晶基板の需要が高まっている。   Silicon carbide (SiC) has attracted attention as an environmentally resistant semiconductor material because it is excellent in heat resistance and mechanical strength and is physically and chemically stable. In recent years, the demand for SiC single crystal substrates has increased as a substrate for high-frequency, high-voltage electronic devices.

SiC単結晶基板を用いて、電力デバイス、高周波デバイス等を作製する場合には、通常、基板上に熱CVD法(熱化学蒸着法)と呼ばれる方法を用いてSiC薄膜をエピタキシャル成長させたり、イオン注入法により直接ドーパントを打ち込んだりするのが一般的であるが、後者の場合には、注入後に高温でのアニ−ルが必要となるため、エピタキシャル成長による薄膜形成が多用されている。   When manufacturing a power device, a high-frequency device, etc. using a SiC single crystal substrate, a SiC thin film is epitaxially grown on the substrate by a method called thermal CVD (thermochemical vapor deposition) or ion implantation is usually performed. In general, the dopant is directly implanted by the method, but in the latter case, annealing at a high temperature is required after the implantation, so that thin film formation by epitaxial growth is frequently used.

SiC単結晶基板上にエピタキシャル成長を行った場合に観察される典型的な欠陥(エピタキシャル欠陥)の顕微鏡写真を図1(a)、(b)に示す。SiC単結晶基板は、(0001)面(Si面)である。図1に示す欠陥以外に、基板に存在するマイクロパイプ欠陥を引き継いだ欠陥があるが、近年の研究進展により、マイクロパイプが10個/cm2以下の基板が比較的容易に得られるようになっていることから、マイクロパイプに起因するエピタキシャル欠陥は大きな問題ではなくなりつつある。図1(a)、(b)に示す欠陥は、エピタキシャル層上にのみ見られる欠陥であり、特に、図1(a)はキャロット欠陥、図1(b)は三角形欠陥と呼ばれることが多く、これらがデバイスの電極下に存在すると、耐圧が低下する等の特性劣化を引き起こすことが知られている(非特許文献1)。これらの欠陥の密度は通常50〜100個/cm2程度であるが、近年のデバイスの高出力化に伴い、デバイス電極面積も1〜2mm角以上と大きくなっている。したがって、電極の下には、1個ないしそれ以上の欠陥が存在することになり、デバイスの特性を劣化させ、歩留りを低下させている。 Micrographs of typical defects (epitaxial defects) observed when epitaxial growth is performed on a SiC single crystal substrate are shown in FIGS. 1 (a) and 1 (b). The SiC single crystal substrate has a (0001) plane (Si plane). In addition to the defects shown in Fig. 1, there are defects that have inherited the micropipe defects present on the substrate, but due to recent research progress, it is relatively easy to obtain a substrate with 10 micropipes / cm 2 or less. Therefore, epitaxial defects caused by micropipes are not becoming a big problem. The defects shown in FIGS. 1 (a) and 1 (b) are defects that are found only on the epitaxial layer, and in particular, FIG. 1 (a) is often called a carrot defect, and FIG. 1 (b) is often called a triangular defect. When these exist under the electrodes of the device, it is known to cause characteristic deterioration such as a decrease in breakdown voltage (Non-patent Document 1). The density of these defects is usually about 50 to 100 pieces / cm 2 , but the device electrode area is increased to 1 to 2 mm square or more with the recent increase in output of devices. Therefore, one or more defects are present under the electrodes, degrading the device characteristics and reducing the yield.

通常、SiC基板上にエピタキシャル成長を行う場合、基板としては1°より大きいオフ角度を持つものを用い、所謂ステップフロー成長を実施する。図1(a)、(b)に示すような欠陥は、エピタキシャル成長前のSiC単結晶基板上に存在する研磨キズ、微小な凹凸による欠陥、あるいは基板自体に存在する欠陥等により、ステップフロー成長が妨げられたために生じるものである。一般的に、エピタキシャル成長には、横形のCVD装置が用いられることが多い。CVD法は、装置構成が簡単であり、ガスのon/offで成長を制御できるため、エピタキシャル膜の制御性、再現性に優れた成長方法である。図2に、成長を行う際の典型的な成長シーケンスを、ガスの導入タイミングと併せて示す。まず、成長炉に基板をセットし、成長炉内を真空排気した後、水素ガスを導入して圧力を1×104〜3×104Paに調整する。その後、圧力を一定に保ちながら成長炉の温度を上げ、1400℃程度で10〜30分間、水素中あるいは塩化水素を導入して塩化水素中での基板のエッチングを行う。これは、研磨等に伴う基板表面の変質層を取り除き、清浄な表面を出すためのものである。その後、温度を成長温度である1500〜1600℃に上げ、材料ガスであるSiH4とC3H8を導入して成長を開始する。SiH4流量は毎分4〜5cm3、C3H8流量は毎分1〜3cm3であり、成長速度は毎時5〜6μmである。この成長速度は、通常利用されるエピタキシャル層の膜厚が10μm程度であるため、生産性を考慮して決定されたものである。一定時間成長し、所望の膜厚が得られた時点でSiH4とC3H8の導入を止め、水素ガスのみ流した状態で温度を下げる。温度が常温まで下がった後、水素ガスの導入を止め、成長室内を真空排気し、不活性ガスを成長室に導入して、成長室を大気圧に戻してから、基板を取り出す。 Normally, when epitaxial growth is performed on a SiC substrate, a substrate having an off angle larger than 1 ° is used, and so-called step flow growth is performed. Defects as shown in FIGS. 1 (a) and 1 (b) are caused by step flow growth due to polishing scratches present on the SiC single crystal substrate before epitaxial growth, defects due to minute irregularities, or defects present on the substrate itself. It is caused by being disturbed. In general, a lateral CVD apparatus is often used for epitaxial growth. The CVD method has a simple apparatus configuration and can control growth by gas on / off, and is therefore a growth method with excellent controllability and reproducibility of the epitaxial film. FIG. 2 shows a typical growth sequence for the growth, together with the gas introduction timing. First, a substrate is set in a growth furnace, the inside of the growth furnace is evacuated, and hydrogen gas is introduced to adjust the pressure to 1 × 10 4 to 3 × 10 4 Pa. Thereafter, the temperature of the growth furnace is raised while keeping the pressure constant, and the substrate is etched in hydrogen chloride by introducing hydrogen or hydrogen chloride at about 1400 ° C. for 10 to 30 minutes. This is for removing the altered layer on the surface of the substrate due to polishing or the like, and providing a clean surface. Thereafter, the temperature is increased to 1500 to 1600 ° C. which is the growth temperature, and SiH 4 and C 3 H 8 which are material gases are introduced to start the growth. The SiH 4 flow rate is 4-5 cm 3 per minute, the C 3 H 8 flow rate is 1-3 cm 3 per minute, and the growth rate is 5-6 μm per hour. This growth rate is determined in consideration of productivity because the film thickness of the normally used epitaxial layer is about 10 μm. When the film is grown for a certain period of time and a desired film thickness is obtained, the introduction of SiH 4 and C 3 H 8 is stopped, and the temperature is lowered with only hydrogen gas flowing. After the temperature has dropped to room temperature, the introduction of hydrogen gas is stopped, the growth chamber is evacuated, an inert gas is introduced into the growth chamber, the growth chamber is returned to atmospheric pressure, and the substrate is taken out.

しかしながら、上記のような方法でエピタキシャル成長を行った場合、水素あるいは塩化水素中での基板エッチングの後でも、依然として基板上の微小な凹凸、荒れに起因する欠陥や基板自体の欠陥は存在する。これらの欠陥は、らせん転位として渦巻成長を起こすステップを供給する場合が多く、成長ステップがオフ方向へ進んでいくステップフロー成長を妨げるものになる。その結果、これらの欠陥が存在する部分では、正常なエピタキシャル成長が行われなくなり、図1(a)、(b)に示したようなエピタキシャル欠陥が発生し、このようなエピタキシャル膜を用いたデバイスは、その特性や歩留りが低下することになる。   However, when epitaxial growth is performed by the method as described above, even after etching the substrate in hydrogen or hydrogen chloride, there are still defects due to minute irregularities and roughness on the substrate and defects on the substrate itself. These defects often provide a step that causes vortex growth as a screw dislocation and hinders the step flow growth in which the growth step proceeds in the off direction. As a result, normal epitaxial growth is not performed in the portion where these defects exist, and epitaxial defects as shown in FIGS. 1 (a) and (b) occur. The characteristics and yield will be reduced.

したがって、今後デバイスへの応用が期待されるSiCエピタキシャル成長基板であるが、現状技術では、デバイスの特性や歩留りを劣化させない程度にまでエピタキシャル欠陥の数を減少させることは困難である。一方、SiCには、(0001)面(Si面)に対しc軸方向に反転位置関係にある(000-1)面(C面)が存在し、C面を用いると、上記のようなエピタキシャル欠陥の少ない良好な表面モホロジーが得られることが知られている。しかし、C面を用いた場合には、Si面に比べて、エピタキシャル成長層内の残留不純物密度を下げることが難しく、そのため、このようなエピタキシャル成長基板を用いた場合には、デバイスのリーク電流が大きくなる等の別の問題が発生し、実用化の弊害となる。
K. Kimoto, et al., IEEE Transactions on Electron Devices, Vol.46, No.3, (1999) pp.471-477
Therefore, it is a SiC epitaxial growth substrate that is expected to be applied to devices in the future. However, with the current technology, it is difficult to reduce the number of epitaxial defects to such an extent that the device characteristics and yield are not deteriorated. On the other hand, in SiC, there is a (000-1) plane (C plane) that is in the reversed position in the c-axis direction with respect to the (0001) plane (Si plane). It is known that good surface morphology with few defects can be obtained. However, when the C plane is used, it is difficult to reduce the residual impurity density in the epitaxial growth layer compared to the Si plane. Therefore, when such an epitaxial growth substrate is used, the device leakage current is large. Another problem occurs, which becomes an adverse effect of practical use.
K. Kimoto, et al., IEEE Transactions on Electron Devices, Vol.46, No.3, (1999) pp.471-477

本発明は、上記エピタキシャル成長において、エピタキシャル欠陥の少ない高品質エピタキシャル膜を有するエピタキシャルSiC単結晶基板、及びその製造方法を提供するものである。   The present invention provides an epitaxial SiC single crystal substrate having a high-quality epitaxial film with few epitaxial defects in the epitaxial growth, and a method for manufacturing the same.

本発明は、エピタキシャル成長を開始する際に用いられる材料ガス中に含まれる、炭素と珪素の原子数比(C/Si比)とエピタキシャル欠陥との関係に注目することにより、上記課題を解決できることを見出し、完成したものである。即ち、本発明は、
(1) 炭化珪素単結晶基板上に、欠陥の発生を抑止する炭化珪素単結晶薄膜であって、表面粗さのRa値が0.5nm以上1.0nm以下である少なくとも1つの抑止層と、前記抑止層の上に形成される炭化珪素単結晶薄膜の活性層とを有することを特徴とするエピタキシャル炭化珪素単結晶基板、
(2) 前記炭化珪素単結晶基板のオフ角度が1°よりも大きい(1)記載のエピタキシャル炭化珪素単結晶基板、
(3) 前記炭化珪素薄膜の抑止層の厚さが1μm以下である(1)記載のエピタキシャル炭化珪素単結晶基板、
(4) 前記炭化珪素薄膜の活性層の厚さが50μm以下である(1)記載のエピタキシャル炭化珪素単結晶基板、
(5) 炭化珪素単結晶基板上に、欠陥の発生を抑止する炭化珪素単結晶薄膜であって、表面粗さのRa値が0.5nm以上1.0nm以下である少なくとも1つの抑止層を、材料ガス中に含まれる炭素と珪素の原子数比(C/Si比)を1.0以下の状態でエピタキシャル成長させた後、前記抑止層上に炭化珪素単結晶薄膜の活性層を、材料ガス中に含まれる炭素と珪素の原子数比(C/Si比)を1.0よりも大きい状態でエピタキシャル成長させることを特徴とするエピタキシャル炭化珪素単結晶基板の製造方法、
(6) 前記抑止層及び活性層のエピタキシャル成長は、熱化学蒸着法(CVD法)で行なう(5)記載のエピタキシャル炭化珪素単結晶基板の製造方法、
(7) 前記炭化珪素単結晶基板のオフ角度が1°よりも大きい(5)又は(6)に記載のエピタキシャル炭化珪素単結晶基板の製造方法、
(8) (1)〜(4)のいずれかに記載のエピタキシャル炭化珪素単結晶基板を用いてなるデバイス、
である。
The present invention can solve the above problem by paying attention to the relationship between the atomic ratio of carbon and silicon (C / Si ratio) and epitaxial defects contained in the material gas used when starting epitaxial growth. Headline, completed. That is, the present invention
(1) A silicon carbide single crystal thin film that suppresses the occurrence of defects on a silicon carbide single crystal substrate, wherein the Ra value of surface roughness is 0.5 nm or more and 1.0 nm or less, and the suppression An epitaxial silicon carbide single crystal substrate comprising an active layer of a silicon carbide single crystal thin film formed on the layer,
(2) The epitaxial silicon carbide single crystal substrate according to (1), wherein an off angle of the silicon carbide single crystal substrate is larger than 1 °,
(3) The epitaxial silicon carbide single crystal substrate according to (1), wherein the thickness of the suppression layer of the silicon carbide thin film is 1 μm or less,
(4) The epitaxial silicon carbide single crystal substrate according to (1), wherein the thickness of the active layer of the silicon carbide thin film is 50 μm or less,
(5) A silicon carbide single crystal thin film that suppresses the occurrence of defects on a silicon carbide single crystal substrate, and has at least one suppression layer having a surface roughness Ra value of 0.5 nm to 1.0 nm. After epitaxial growth with an atomic ratio (C / Si ratio) of carbon and silicon contained in 1.0 or less, an active layer of a silicon carbide single crystal thin film is formed on the suppression layer, and carbon contained in the material gas. And an epitaxial silicon carbide single crystal substrate manufacturing method, characterized in that the atomic ratio of silicon and silicon (C / Si ratio) is epitaxially grown in a state larger than 1.0,
(6) The method for producing an epitaxial silicon carbide single crystal substrate according to (5), wherein the epitaxial growth of the suppression layer and the active layer is performed by a thermal chemical vapor deposition method (CVD method),
(7) The method for producing an epitaxial silicon carbide single crystal substrate according to (5) or (6), wherein the off angle of the silicon carbide single crystal substrate is larger than 1 °,
(8) A device using the epitaxial silicon carbide single crystal substrate according to any one of (1) to (4),
It is.

本発明によれば、SiC単結晶基板のSi面上にSiC単結晶薄膜をエピタキシャル成長させたエピタキシャルSiC単結晶基板であっても、エピタキシャル欠陥の少ない高品質なエピタキシャル膜を有するエピタキシャルSiC単結晶基板を提供することが可能である。   According to the present invention, an epitaxial SiC single crystal substrate having a high-quality epitaxial film with few epitaxial defects can be obtained even if the SiC single crystal thin film is epitaxially grown on the Si surface of the SiC single crystal substrate. It is possible to provide.

また、本発明の製造方法は、CVD法によってSiC単結晶薄膜を成長させることができるため、装置構成が容易で制御性にも優れ、均一性、再現性の高いエピタキシャル膜が得られる。   In addition, since the manufacturing method of the present invention can grow a SiC single crystal thin film by the CVD method, an epitaxial film with an easy apparatus configuration, excellent controllability, and high uniformity and reproducibility can be obtained.

さらに、本発明のエピタキシャルSiC単結晶基板を用いたデバイスは、エピタキシャル欠陥の少ない高品質エピタキシャル膜上に形成されるため、その特性及び歩留りが向上する。   Furthermore, since the device using the epitaxial SiC single crystal substrate of the present invention is formed on a high quality epitaxial film with few epitaxial defects, its characteristics and yield are improved.

本発明の具体的な内容について述べる。
まず、SiC基板上へのエピタキシャル成長について述べる。本発明で好適にエピタキシャル成長に用いる装置は、横型のCVD装置である。CVD法は、装置構成が簡単であり、ガスのon/offで成長を制御できるため、エピタキシャル膜の制御性、再現性に優れた成長方法である。成長シーケンスとしては、SiC基板をセットし、水素あるいは塩化水素中でのエッチングまでは、図2と同様である。
The specific contents of the present invention will be described.
First, epitaxial growth on a SiC substrate is described. The apparatus preferably used for epitaxial growth in the present invention is a horizontal CVD apparatus. The CVD method has a simple apparatus configuration and can control growth by gas on / off, and is therefore a growth method with excellent controllability and reproducibility of the epitaxial film. The growth sequence is the same as in FIG. 2 until the SiC substrate is set and etching in hydrogen or hydrogen chloride is performed.

その後、1500〜1600℃の成長温度に上げ、材料ガスであるSiH4とC3H8を流すが、その時のSiH4ガスに対するC3H8ガスの流量を通常よりも小さくして成長を開始する。通常、材料ガスにおける炭素原子と珪素原子の比(C/Si比)は1.5〜2.0程度であり、これはステップフロー成長の場合、成長がSi原子の供給に律速されているためであるが、本発明の場合は成長初期のC/Si比を0.5〜1.0に下げる。この時、Si原子が過剰になっているため、ステップの成長が遅く、またステップに付着したC原子及びSi原子も、不安定な成長条件であるため、表面からの離脱が生じ易く、この事もステップの成長を抑制する。この現象は、通常のステップフロー成長に対しても前記らせん転位を起点とした渦巻成長に対しても同様と考えられる。しかし、オフ角度が1°より大きい通常の基板の場合、オフ角をつけることで表面に形成されるステップの数は、基板上の微小な凹凸、荒れに起因する欠陥や基板自体の欠陥の数よりも2〜3桁以上大きい。したがって、これら欠陥によるらせん転位を起点とした渦巻成長の数は、ステップフロー成長の数に比べて圧倒的に小さく、かつC/Si比が0.5〜1.0という不安定な成長条件であるため、渦巻成長が安定して進行せず、周囲からの大量のステップフロー成長に覆われて消滅する確率が高くなると考えられる。C/Si比が1.5〜2.0の場合には、成長が安定になっているため、周囲のステップフロー成長の数が圧倒的に多いとしても、渦巻成長の消滅の確率は小さくなると思われる。したがって、成長初期のC/Si比を0.5〜1.0に下げることで、らせん転位を起点とした渦巻成長の発生を抑え、周囲の大量のステップフローに覆われる確率を高めて、エピタキシャル欠陥を減らすことが可能になると考えられる。さらに、不安定な成長によって増加するミクロなステップバンチングが、表面粗さのRa値をある程度大きくすることで、ステップに取り込まれる原子の数を増やし、ステップフローの促進には有効に働くと考えられる。また、C/Si比が0.5未満になると、過剰なSi原子が基板表面に凝縮し、Siドロップレットと呼ばれる欠陥が形成され易くなるため好ましくない。 After that, the growth temperature is raised to 1500-1600 ° C, and the material gases SiH 4 and C 3 H 8 are allowed to flow, but the growth is started with the flow rate of C 3 H 8 gas relative to the SiH 4 gas smaller than usual. To do. Usually, the ratio of carbon atoms to silicon atoms (C / Si ratio) in the material gas is about 1.5 to 2.0, because in the case of step flow growth, the growth is rate-controlled by the supply of Si atoms, In the present invention, the C / Si ratio at the initial stage of growth is lowered to 0.5 to 1.0. At this time, since the Si atoms are excessive, the step growth is slow, and the C atoms and Si atoms adhering to the step are also unstable growth conditions. Even suppress the growth of steps. This phenomenon is considered to be the same for both normal step flow growth and spiral growth starting from the screw dislocation. However, in the case of a normal substrate with an off angle of more than 1 °, the number of steps formed on the surface by setting the off angle is the number of minute irregularities on the substrate, defects due to roughness, and defects on the substrate itself. 2 or 3 orders of magnitude greater than Therefore, the number of spiral growth starting from screw dislocations due to these defects is overwhelmingly smaller than the number of step flow growth and the C / Si ratio is an unstable growth condition of 0.5 to 1.0. It is considered that the growth does not proceed stably and the probability of disappearing covered with a large amount of step flow growth from the surroundings is increased. When the C / Si ratio is 1.5 to 2.0, the growth is stable, so even if the number of surrounding step flow growths is overwhelmingly large, the probability of vortex growth disappearing is likely to be small. Therefore, by reducing the initial C / Si ratio to 0.5-1.0, the occurrence of spiral growth starting from screw dislocations is suppressed, and the probability of being covered by a large amount of surrounding step flow is increased, thereby reducing epitaxial defects. Will be possible. Furthermore, micro step bunching, which increases due to unstable growth, increases the number of atoms taken into the step by increasing the Ra value of the surface roughness to some extent, and is thought to work effectively in promoting step flow. . On the other hand, when the C / Si ratio is less than 0.5, excessive Si atoms are condensed on the substrate surface, and defects called Si droplets are easily formed.

このような考察の基、例えば実施例に示すように、材料ガスである、SiH4とC3H8の流量に関し、成長開始時のSiH4流量を毎分4cm3、C3H8流量を毎分1 cm3にし、C/Si比を0.75として成長を行ったところ、エピタキシャル欠陥を低減させることができた。この時の成長速度は、毎時3.5μmであった。 Based on such considerations, for example, as shown in the examples, regarding the flow rates of SiH 4 and C 3 H 8 which are material gases, the SiH 4 flow rate at the start of growth is 4 cm 3 per minute, and the C 3 H 8 flow rate is When growth was carried out at 1 cm 3 / min and a C / Si ratio of 0.75, epitaxial defects could be reduced. The growth rate at this time was 3.5 μm per hour.

本発明により、成長開始時のC/Si比を1.0以下に下げることで、エピタキシャル欠陥の発生を従来よりも低減させることが可能になったが、そのために成長初期に形成する層(抑止層)の厚さは、1μm以下で十分であり、さらには0.5μm〜1μmの間が好ましい。抑止層はC/Si比1.0以下で成長するため、所謂site-competition効果で雰囲気からの不純物の取り込みが多くなり、膜厚が大きくなると残留不純物が増加して膜の品質に影響を与えるため1μm以下とすることが望ましい。また、基板上に存在する欠陥の影響を受けなくするためには、抑止層は0.5μm以上の膜厚とすることが望ましい。一方、抑止層のRa値は、上述の理由から、ミクロなステップバンチングが生じる程度の大きさが必要だが、大き過ぎるとその上に成長する層の表面状態が悪化するため、0.5nm〜1.0nmの間が望ましい。尚、表面粗さRaはJIS B0601-1994に準拠する。   According to the present invention, by reducing the C / Si ratio at the start of growth to 1.0 or less, it has become possible to reduce the occurrence of epitaxial defects as compared with the prior art. 1 μm or less is sufficient, and more preferably between 0.5 μm and 1 μm. Since the suppression layer grows with a C / Si ratio of 1.0 or less, the so-called site-competition effect increases the uptake of impurities from the atmosphere, and as the film thickness increases, residual impurities increase and affect the film quality. The following is desirable. Further, in order to avoid the influence of defects existing on the substrate, it is desirable that the suppression layer has a thickness of 0.5 μm or more. On the other hand, the Ra value of the suppression layer needs to be large enough to cause micro step bunching for the reasons described above, but if it is too large, the surface state of the layer grown on it will deteriorate, so 0.5 nm to 1.0 nm Between is desirable. The surface roughness Ra conforms to JIS B0601-1994.

この抑止層を成長させた後、成長温度を1500℃以上、好ましくは1500〜1600℃、また成長速度は、C/Si比が1.0を越えるように、好ましくは1.5〜2.0になるように、SiH4流量を毎分4〜5cm3、C3H8流量を毎分2〜3cm3に設定し、毎時5〜6μmにして、デバイスが形成される層(活性層)の成長を行う。活性層において、C/Si比が1.0を越えるようにするのは、成長がSi原子の供給律速であるため、成長速度の制御を行い易くするためと、site-competition効果によって雰囲気からの不純物の取り込みを下げるためである。また、C/Si比が大き過ぎるとガスの消費効率が悪化するため、C/Si比は3.0以下が望ましい。 After growing this deterrent layer, the growth temperature is 1500 ° C. or higher, preferably 1500-1600 ° C., and the growth rate is SiH so that the C / Si ratio exceeds 1.0, preferably 1.5-2.0. 4. The flow rate is set to 4 to 5 cm 3 / min, the C 3 H 8 flow rate is set to 2 to 3 cm 3 / min, and the flow rate is set to 5 to 6 μm / hr to grow the layer (active layer) in which the device is formed. The reason why the C / Si ratio exceeds 1.0 in the active layer is that the growth is controlled by the supply of Si atoms, so that the growth rate can be easily controlled, and the site-competition effect is effective for impurities from the atmosphere. This is to lower the uptake. Further, if the C / Si ratio is too large, the gas consumption efficiency deteriorates, so the C / Si ratio is preferably 3.0 or less.

このようにして得たエピタキシャルSiC単結晶基板の模式図を図3に示す。図3の1がSiC単結晶基板、2が抑止層、3が活性層である。この活性層の上にデバイスが形成されるが、活性層の厚さは、デバイスの耐圧、エピタキシャル膜の生産性等を考慮した場合、10μm以上50μm以下が望ましい。   A schematic diagram of the epitaxial SiC single crystal substrate thus obtained is shown in FIG. In FIG. 3, 1 is a SiC single crystal substrate, 2 is a suppression layer, and 3 is an active layer. A device is formed on the active layer. The thickness of the active layer is preferably 10 μm or more and 50 μm or less in consideration of the breakdown voltage of the device, the productivity of the epitaxial film, and the like.

また、SiC単結晶基板のオフ角については、1°以下であると基板表面に存在するステップ数が少ないため、正常なエピタキシャル成長が行われ難く、また10°を越えるとインゴットから基板を作製する際に、より斜めに切り出す必要があるため収率が下がる。従って1°より大きく10°以下が望ましいが、より好ましくは4°〜8°の間である。   If the SiC single crystal substrate has an off angle of 1 ° or less, the number of steps existing on the surface of the substrate is small, so that normal epitaxial growth is difficult to perform, and if it exceeds 10 °, the substrate is made from an ingot. In addition, the yield is lowered because it is necessary to cut more obliquely. Therefore, it is desirable to be greater than 1 ° and not more than 10 °, but more preferably between 4 ° and 8 °.

このようにして得たエピタキシャルSiC単結晶基板上に好適に形成されるデバイスは、ショットキーバリアダイオード、MOSダイオード、MOSトランジスタ等、特に電力制御用に用いられるデバイスである。   Devices suitably formed on the epitaxial SiC single crystal substrate thus obtained are Schottky barrier diodes, MOS diodes, MOS transistors, and the like, particularly devices used for power control.

(実施例)
2インチ(50mm)ウェハ用SiC単結晶インゴットから、約400μmの厚さでスライスし、粗削りとダイヤモンド砥粒による通常研磨を実施した、4H型のポリタイプを有するSiC単結晶基板のSi面に、エピタキシャル成長を実施した。基板のオフ角は8°である。成長の手順としては、成長炉に基板をセットし、成長炉内を真空排気した後、水素ガスを毎分16L導入しながら圧力を1.6×104 Paに調整した。その後、圧力を一定に保ちながら成長炉の温度を上げ、1400℃に到達した後、塩化水素を毎分10cm3流し、10分間基板のエッチングを行った。エッチング後、温度を1550℃まで上げ、SiH4流量を毎分4cm3、C3H8流量を毎分1cm3にして(C/Si比は0.75)、抑止層を約0.5μm成長した。この時の成長速度は毎時3.5μm程度であった。抑止層を成長後、温度は変えず、SiH4流量を毎分5cm3、C3H8流量を毎分3cm3にして(C/Si比は1.8)、活性層を約10μm成長した。この時の成長速度は毎時5μm程度であった。
(Example)
From a SiC single crystal ingot for a 2 inch (50 mm) wafer, sliced at a thickness of about 400 μm, and then subjected to rough grinding and normal polishing with diamond abrasive grains, on the Si surface of a SiC single crystal substrate having a 4H type polytype, Epitaxial growth was performed. The off angle of the substrate is 8 °. As a growth procedure, a substrate was set in a growth furnace, the inside of the growth furnace was evacuated, and then the pressure was adjusted to 1.6 × 10 4 Pa while introducing 16 L of hydrogen gas per minute. Thereafter, the temperature of the growth furnace was raised while keeping the pressure constant, and after reaching 1400 ° C., 10 cm 3 of hydrogen chloride was flowed per minute and the substrate was etched for 10 minutes. After etching, the temperature was raised to 1550 ° C., the SiH 4 flow rate was 4 cm 3 / min, the C 3 H 8 flow rate was 1 cm 3 / min (C / Si ratio was 0.75), and a deterrent layer was grown about 0.5 μm. The growth rate at this time was about 3.5 μm per hour. After growing the suppression layer, the temperature was not changed, the SiH 4 flow rate was 5 cm 3 / min, the C 3 H 8 flow rate was 3 cm 3 / min (C / Si ratio was 1.8), and the active layer was grown about 10 μm. The growth rate at this time was about 5 μm per hour.

エピタキシャル成長後の表面の光学顕微鏡写真を図4に示す。成長面は鏡面であり、欠陥密度としては、三角形状あるいはキャロット、コメット欠陥の密度が20個/cm2以下と通常の1/5程度になっていた。また、上記の条件で抑止層のみを約0.5μm成長して表面のAFM評価を行ったところ、Ra値は0.55nmであった。活性層を成長した後の最終的な表面のRa値は0.23nmと平坦性は高く、抑止層のRa値の影響は受けていないことが示された。なお、抑止層と活性層を成長した後、断面TEM像を観察することで抑止層の表面粗さを評価することも可能である。 An optical micrograph of the surface after the epitaxial growth is shown in FIG. The growth surface was a mirror surface, and the defect density was a triangular shape, or the density of carrot and comet defects was about 1/5, which is 20 pieces / cm 2 or less. Further, when the surface AFM evaluation was performed by growing only the suppression layer by about 0.5 μm under the above conditions, the Ra value was 0.55 nm. The final surface Ra value after growth of the active layer was 0.23 nm and the flatness was high, indicating that it was not affected by the Ra value of the suppression layer. It is also possible to evaluate the surface roughness of the suppression layer by observing a cross-sectional TEM image after growing the suppression layer and the active layer.

このようにして得たエピタキシャルSiC単結晶基板を用いてショットキーバリアダイオードを形成した際、ドーピング密度が約1×1016cm-3の時、逆方向耐圧は250〜300Vであり、ほぼ理論値に近い値が得られた。 When a Schottky barrier diode is formed using the epitaxial SiC single crystal substrate thus obtained, the reverse breakdown voltage is 250 to 300 V when the doping density is about 1 × 10 16 cm −3 , which is almost theoretical value. A value close to was obtained.

(比較例)
比較例として、実施例1と同様にスライス、粗削り、通常研磨を行った、4H型のポリタイプを有する2インチ(50mm)のSiC単結晶基板のSi面に、エピタキシャル成長を実施した。基板のオフ角は8°である。成長手順は、塩化水素のエッチングまでは、実施例と同様である。エッチング後、温度を1550℃まで上げ、SiH4流量を毎分5cm3、C3H8流量を毎分3cm3にして(C/Si比は1.8)、抑止層を成長させずに活性層を約10μm成長した。成長後の表面には、図1(a)、(b)で示したようなエピタキシャル欠陥が発生し、その密度は約100個/cm2であり、抑止層がないとエピタキシャル欠陥の発生を抑えられないことが分かった。
(Comparative example)
As a comparative example, epitaxial growth was performed on the Si surface of a 2 inch (50 mm) SiC single crystal substrate having a 4H type polytype, which was sliced, roughly ground, and normally polished as in Example 1. The off angle of the substrate is 8 °. The growth procedure is the same as in the example up to the etching of hydrogen chloride. After etching, the temperature is raised to 1550 ° C, the SiH 4 flow rate is 5 cm 3 / min, the C 3 H 8 flow rate is 3 cm 3 / min (C / Si ratio is 1.8), and the active layer is grown without growing the deterrent layer. Growing about 10 μm. Epitaxial defects as shown in Fig. 1 (a) and (b) occur on the surface after growth, and the density is about 100 / cm 2. I found it impossible.

このようにして得たエピタキシャルSiC単結晶基板を用いてショットキーバリアダイオードを形成した際、ドーピング密度が約1×1016cm-3の時、逆方向耐圧は200V以下であった。 When a Schottky barrier diode was formed using the epitaxial SiC single crystal substrate thus obtained, the reverse breakdown voltage was 200 V or less when the doping density was about 1 × 10 16 cm −3 .

この発明によれば、SiC単結晶基板上へのエピタキシャル成長において、欠陥の少ない高品質エピタキシャル膜を有するエピタキシャルSiC単結晶基板を作成することが可能である。そのため、このような基板上に電子デバイスを形成すればデバイスの特性及び歩留まりが向上することが期待できる。本実施例においては材料ガスとしてSiH4およびC3H8を用いているが、Si源としてトリクロルシラン、C源としてC2H4等を用いた場合についても同様である。 According to the present invention, it is possible to produce an epitaxial SiC single crystal substrate having a high-quality epitaxial film with few defects in epitaxial growth on the SiC single crystal substrate. Therefore, if an electronic device is formed on such a substrate, it can be expected that the characteristics and yield of the device are improved. In this embodiment, SiH 4 and C 3 H 8 are used as the material gas, but the same applies to the case where trichlorosilane is used as the Si source and C 2 H 4 is used as the C source.

従来技術によって成長させたSiCエピタキシャル膜上に存在する欠陥の状態を示す光学顕微鏡像。An optical microscope image showing the state of defects existing on a SiC epitaxial film grown by a conventional technique. 従来技術によるSiCエピタキシャル膜の成長シーケンスを示す図。The figure which shows the growth sequence of the SiC epitaxial film by a prior art. 本発明の一例によって成長させたエピタキシャルSiC単結晶基板の断面模式図。The cross-sectional schematic diagram of the epitaxial SiC single crystal substrate grown by the example of this invention. 本発明の一例によって成長したSiCエピタキシャル膜の表面状態を示す光学顕微鏡像。The optical microscope image which shows the surface state of the SiC epitaxial film grown by the example of this invention.

符号の説明Explanation of symbols

1 SiC単結晶基板
2 抑止層
3 活性層
1 SiC single crystal substrate
2 Deterrence layer
3 Active layer

Claims (8)

炭化珪素単結晶基板上に、欠陥の発生を抑止する炭化珪素単結晶薄膜であって、表面粗さのRa値が0.5nm以上1.0nm以下である少なくとも1つの抑止層と、前記抑止層の上に形成される炭化珪素単結晶薄膜の活性層とを有することを特徴とするエピタキシャル炭化珪素単結晶基板。   A silicon carbide single crystal thin film that suppresses the occurrence of defects on a silicon carbide single crystal substrate, the surface roughness Ra value being 0.5 nm or more and 1.0 nm or less, and at least one suppression layer And an active layer of a silicon carbide single crystal thin film formed on the substrate. 前記炭化珪素単結晶基板のオフ角度が1°よりも大きい請求項1記載のエピタキシャル炭化珪素単結晶基板。   2. The epitaxial silicon carbide single crystal substrate according to claim 1, wherein an off angle of the silicon carbide single crystal substrate is larger than 1 °. 前記炭化珪素薄膜の抑止層の厚さが1μm以下である請求項1記載のエピタキシャル炭化珪素単結晶基板。   2. The epitaxial silicon carbide single crystal substrate according to claim 1, wherein the thickness of the suppression layer of the silicon carbide thin film is 1 μm or less. 前記炭化珪素薄膜の活性層の厚さが50μm以下である請求項1記載のエピタキシャル炭化珪素単結晶基板。   2. The epitaxial silicon carbide single crystal substrate according to claim 1, wherein the thickness of the active layer of the silicon carbide thin film is 50 μm or less. 炭化珪素単結晶基板上に、欠陥の発生を抑止する炭化珪素単結晶薄膜であって、表面粗さのRa値が0.5nm以上1.0nm以下である少なくとも1つの抑止層を、材料ガス中に含まれる炭素と珪素の原子数比(C/Si比)を1.0以下の状態でエピタキシャル成長させた後、前記抑止層上に炭化珪素単結晶薄膜の活性層を、材料ガス中に含まれる炭素と珪素の原子数比(C/Si比)を1.0よりも大きい状態でエピタキシャル成長させることを特徴とするエピタキシャル炭化珪素単結晶基板の製造方法。   A silicon carbide single crystal thin film that suppresses the occurrence of defects on a silicon carbide single crystal substrate and includes at least one suppression layer having a surface roughness Ra value of 0.5 nm or more and 1.0 nm or less in the material gas. After epitaxial growth with a carbon / silicon atomic ratio (C / Si ratio) of 1.0 or less, an active layer of a silicon carbide single crystal thin film is formed on the deterring layer with carbon / silicon contained in the material gas. A method of manufacturing an epitaxial silicon carbide single crystal substrate, wherein epitaxial growth is performed with an atomic ratio (C / Si ratio) being greater than 1.0. 前記抑止層及び活性層のエピタキシャル成長は、熱化学蒸着法(CVD法)で行なう請求項5記載のエピタキシャル炭化珪素単結晶基板の製造方法。   6. The method for producing an epitaxial silicon carbide single crystal substrate according to claim 5, wherein the epitaxial growth of the suppression layer and the active layer is performed by a thermal chemical vapor deposition method (CVD method). 前記炭化珪素単結晶基板のオフ角度が1°よりも大きい請求項5又は6に記載のエピタキシャル炭化珪素単結晶基板の製造方法。   7. The method for producing an epitaxial silicon carbide single crystal substrate according to claim 5, wherein an off angle of the silicon carbide single crystal substrate is larger than 1 °. 請求項1〜4のいずれかに記載のエピタキシャル炭化珪素単結晶基板を用いてなるデバイス。   A device comprising the epitaxial silicon carbide single crystal substrate according to claim 1.
JP2006255674A 2006-09-21 2006-09-21 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof Active JP4954654B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006255674A JP4954654B2 (en) 2006-09-21 2006-09-21 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006255674A JP4954654B2 (en) 2006-09-21 2006-09-21 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2008074664A true JP2008074664A (en) 2008-04-03
JP4954654B2 JP4954654B2 (en) 2012-06-20

Family

ID=39347108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006255674A Active JP4954654B2 (en) 2006-09-21 2006-09-21 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4954654B2 (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040652A (en) * 2008-08-01 2010-02-18 Fuji Electric Systems Co Ltd Method of manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
WO2010087518A1 (en) 2009-01-30 2010-08-05 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and mehtod for producing same
JP2010278120A (en) * 2009-05-27 2010-12-09 Mitsubishi Electric Corp Method of manufacturing silicon carbide semiconductor device
KR20130070480A (en) * 2011-12-19 2013-06-27 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer and silicon carbide epi wafer
KR20130070482A (en) * 2011-12-19 2013-06-27 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer
JP2013239606A (en) * 2012-05-16 2013-11-28 Mitsubishi Electric Corp Method for manufacturing silicon carbide epitaxial wafer
JP2014043369A (en) * 2012-08-26 2014-03-13 Nagoya Univ METHOD FOR MAKING SiC SINGLE CRYSTAL AND SiC SINGLE CRYSTAL
JP2014154587A (en) * 2013-02-05 2014-08-25 Sumitomo Electric Ind Ltd Silicon carbide semiconductor substrate manufacturing method and silicon carbide semiconductor device manufacturing method
KR20150002062A (en) * 2013-06-28 2015-01-07 엘지이노텍 주식회사 Epitaxial wafer
US9279192B2 (en) 2014-07-29 2016-03-08 Dow Corning Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
US9318324B2 (en) 2014-03-19 2016-04-19 Kabushiki Kaisha Toshiba Manufacturing method of SiC epitaxial substrate, manufacturing method of semiconductor device, and semiconductor device
US9337277B2 (en) 2012-09-11 2016-05-10 Dow Corning Corporation High voltage power semiconductor device on SiC
CN106715767A (en) * 2014-10-01 2017-05-24 住友电气工业株式会社 Silicon carbide epitaxial substrate
KR20170070104A (en) 2015-02-18 2017-06-21 신닛테츠스미킨 카부시키카이샤 Method for producing silicon carbide single crystal epitaxial wafer and silicon carbide single crystal epitaxial wafer
US9738991B2 (en) 2013-02-05 2017-08-22 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion
US9797064B2 (en) 2013-02-05 2017-10-24 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion
KR20180016585A (en) 2015-07-29 2018-02-14 신닛테츠스미킨 카부시키카이샤 Process for manufacturing epitaxial silicon carbide single crystal wafers
KR20180090814A (en) 2015-12-24 2018-08-13 쇼와 덴코 가부시키가이샤 Method of manufacturing SiC epitaxial wafer
KR101936170B1 (en) 2011-12-19 2019-01-08 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer
KR101942514B1 (en) 2011-12-16 2019-01-28 엘지이노텍 주식회사 Method for deposition of silicon carbide and silicon carbide epi wafer
US20200020528A1 (en) * 2017-04-06 2020-01-16 Mitsubishi Electric Corporation Sic epitaxial wafer, method for manufacturing sic epitaxial wafer, sic device, and power conversion apparatus
WO2020179796A1 (en) * 2019-03-05 2020-09-10 学校法人関西学院 SiC EPITAXIAL SUBSTRATE MANUFACTURING METHOD AND MANUFACTURING DEVICE THEREFOR
WO2021025086A1 (en) * 2019-08-06 2021-02-11 学校法人関西学院 SiC SUBSTRATE PRODUCTION METHOD

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000053498A (en) * 1998-07-31 2000-02-22 Denso Corp Production of silicon carbide single crystal
JP2000319099A (en) * 1999-05-07 2000-11-21 Hiroyuki Matsunami SiC WAFER, SiC SEMICONDUCTOR DEVICE AND PRODUCTION OF SiC WAFER
WO2001018872A1 (en) * 1999-09-07 2001-03-15 Sixon Inc. SiC WAFER, SiC SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD OF SiC WAFER
JP2002261295A (en) * 2001-03-05 2002-09-13 Shikusuon:Kk Schottky, p-n junction diode, and pin junction diode and their manufacturing method
WO2003078702A1 (en) * 2002-03-19 2003-09-25 Central Research Institute Of Electric Power Industry METHOD FOR PREPARING SiC CRYSTAL AND SiC CRYSTAL
JP2005294611A (en) * 2004-04-01 2005-10-20 Toyota Motor Corp Silicon carbide semiconductor substrate and its manufacturing method
JP2005311348A (en) * 2004-03-26 2005-11-04 Kansai Electric Power Co Inc:The Bipolar semiconductor device and process for producing the same
JP2007131504A (en) * 2005-11-14 2007-05-31 Shikusuon:Kk SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE USING THE SAME

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000053498A (en) * 1998-07-31 2000-02-22 Denso Corp Production of silicon carbide single crystal
JP2000319099A (en) * 1999-05-07 2000-11-21 Hiroyuki Matsunami SiC WAFER, SiC SEMICONDUCTOR DEVICE AND PRODUCTION OF SiC WAFER
WO2001018872A1 (en) * 1999-09-07 2001-03-15 Sixon Inc. SiC WAFER, SiC SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD OF SiC WAFER
JP2002261295A (en) * 2001-03-05 2002-09-13 Shikusuon:Kk Schottky, p-n junction diode, and pin junction diode and their manufacturing method
WO2003078702A1 (en) * 2002-03-19 2003-09-25 Central Research Institute Of Electric Power Industry METHOD FOR PREPARING SiC CRYSTAL AND SiC CRYSTAL
JP2005311348A (en) * 2004-03-26 2005-11-04 Kansai Electric Power Co Inc:The Bipolar semiconductor device and process for producing the same
JP2005294611A (en) * 2004-04-01 2005-10-20 Toyota Motor Corp Silicon carbide semiconductor substrate and its manufacturing method
JP2007131504A (en) * 2005-11-14 2007-05-31 Shikusuon:Kk SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE USING THE SAME

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040652A (en) * 2008-08-01 2010-02-18 Fuji Electric Systems Co Ltd Method of manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
WO2010087518A1 (en) 2009-01-30 2010-08-05 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and mehtod for producing same
JP2010278120A (en) * 2009-05-27 2010-12-09 Mitsubishi Electric Corp Method of manufacturing silicon carbide semiconductor device
KR101942514B1 (en) 2011-12-16 2019-01-28 엘지이노텍 주식회사 Method for deposition of silicon carbide and silicon carbide epi wafer
KR101936171B1 (en) 2011-12-19 2019-04-04 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer and silicon carbide epi wafer
KR20130070480A (en) * 2011-12-19 2013-06-27 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer and silicon carbide epi wafer
KR20130070482A (en) * 2011-12-19 2013-06-27 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer
KR101942536B1 (en) 2011-12-19 2019-01-29 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer
KR101936170B1 (en) 2011-12-19 2019-01-08 엘지이노텍 주식회사 Method for fabrication silicon carbide epi wafer
JP2013239606A (en) * 2012-05-16 2013-11-28 Mitsubishi Electric Corp Method for manufacturing silicon carbide epitaxial wafer
JP2014043369A (en) * 2012-08-26 2014-03-13 Nagoya Univ METHOD FOR MAKING SiC SINGLE CRYSTAL AND SiC SINGLE CRYSTAL
US9337277B2 (en) 2012-09-11 2016-05-10 Dow Corning Corporation High voltage power semiconductor device on SiC
US9797064B2 (en) 2013-02-05 2017-10-24 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion
US9738991B2 (en) 2013-02-05 2017-08-22 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion
JP2014154587A (en) * 2013-02-05 2014-08-25 Sumitomo Electric Ind Ltd Silicon carbide semiconductor substrate manufacturing method and silicon carbide semiconductor device manufacturing method
KR102131245B1 (en) 2013-06-28 2020-08-05 엘지이노텍 주식회사 Epitaxial wafer
KR20150002062A (en) * 2013-06-28 2015-01-07 엘지이노텍 주식회사 Epitaxial wafer
US9318324B2 (en) 2014-03-19 2016-04-19 Kabushiki Kaisha Toshiba Manufacturing method of SiC epitaxial substrate, manufacturing method of semiconductor device, and semiconductor device
US9279192B2 (en) 2014-07-29 2016-03-08 Dow Corning Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
US10002760B2 (en) 2014-07-29 2018-06-19 Dow Silicones Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
CN106715767A (en) * 2014-10-01 2017-05-24 住友电气工业株式会社 Silicon carbide epitaxial substrate
EP3260581A4 (en) * 2015-02-18 2018-08-29 Showa Denko K.K. Method for producing silicon carbide single crystal epitaxial wafer and silicon carbide single crystal epitaxial wafer
US11114295B2 (en) 2015-02-18 2021-09-07 Showa Denko K.K. Epitaxial silicon carbide single crystal wafer and process for producing the same
KR20170070104A (en) 2015-02-18 2017-06-21 신닛테츠스미킨 카부시키카이샤 Method for producing silicon carbide single crystal epitaxial wafer and silicon carbide single crystal epitaxial wafer
US10727047B2 (en) 2015-02-18 2020-07-28 Showa Denko K.K. Epitaxial silicon carbide single crystal wafer and process for producing the same
KR20180016585A (en) 2015-07-29 2018-02-14 신닛테츠스미킨 카부시키카이샤 Process for manufacturing epitaxial silicon carbide single crystal wafers
US10626520B2 (en) 2015-07-29 2020-04-21 Showa Denko K.K. Method for producing epitaxial silicon carbide single crystal wafer
US10774444B2 (en) 2015-12-24 2020-09-15 Showa Denko K.K. Method for producing SiC epitaxial wafer including forming epitaxial layer under different conditions
KR20180090814A (en) 2015-12-24 2018-08-13 쇼와 덴코 가부시키가이샤 Method of manufacturing SiC epitaxial wafer
US20200020528A1 (en) * 2017-04-06 2020-01-16 Mitsubishi Electric Corporation Sic epitaxial wafer, method for manufacturing sic epitaxial wafer, sic device, and power conversion apparatus
US10950435B2 (en) * 2017-04-06 2021-03-16 Mitsubishi Electric Corporation SiC epitaxial wafer, method for manufacturing SiC epitaxial wafer, SiC device, and power conversion apparatus
WO2020179796A1 (en) * 2019-03-05 2020-09-10 学校法人関西学院 SiC EPITAXIAL SUBSTRATE MANUFACTURING METHOD AND MANUFACTURING DEVICE THEREFOR
TWI824118B (en) * 2019-03-05 2023-12-01 學校法人關西學院 Silicon carbide epitaxial substrate, manufacturing method of silicon carbide epitaxial substrate, and manufacturing device of silicon carbide epitaxial substrate
WO2021025086A1 (en) * 2019-08-06 2021-02-11 学校法人関西学院 SiC SUBSTRATE PRODUCTION METHOD

Also Published As

Publication number Publication date
JP4954654B2 (en) 2012-06-20

Similar Documents

Publication Publication Date Title
JP4954654B2 (en) Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP4954593B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method, and device using the obtained epitaxial silicon carbide single crystal substrate
JP4987792B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
JP4719314B2 (en) Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP6237848B2 (en) Method for manufacturing silicon carbide single crystal substrate for epitaxial silicon carbide wafer and silicon carbide single crystal substrate for epitaxial silicon carbide wafer
JP4842094B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
JP4850960B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
JP4937685B2 (en) Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP6524233B2 (en) Method of manufacturing epitaxial silicon carbide single crystal wafer
JP4786223B2 (en) Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP6742477B2 (en) Epitaxial silicon carbide single crystal wafer manufacturing method and epitaxial silicon carbide single crystal wafer
JP6304699B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP5786759B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP5664534B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP6052465B2 (en) Method for manufacturing epitaxial silicon carbide wafer

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080806

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100402

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110913

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111114

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120306

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120314

R151 Written notification of patent or utility model registration

Ref document number: 4954654

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150323

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150323

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150323

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350