JP4872158B2 - Schottky diode, pn junction diode, pin junction diode, and manufacturing method - Google Patents

Description

【００３０】

【００３１】
このようにして作製したSiCエピタキシャルウェハを用いて、図１に示す構造のショットキーダイオード１０を作製した。まず、ショットキー電極端部での電界集中、絶縁破壊を抑制するために、ショットキー電極の周囲に幅150μｍ、深さ0.5μｍのp型ガードリング１４を設けた。ガードリング１４はホウ素(以下、Bと記す。)のイオン注入により形成した。Bイオン注入のエネルギーは30〜280keVでトータルドーズ量は1.1x10¹³cm^-2である。イオン注入のマスクには、厚さ4μｍのアルミニウム(以下、Alと記す。)膜、あるいはCVD法により形成した厚さ5μｍの酸化硅素(SiO₂)膜を用いた。注入イオン活性化のための熱処理はArガス雰囲気中で1500℃、30分の条件で行った。熱処理後、1150℃、2時間のウェット酸化により熱酸化膜１９を形成し、さらにCVD法によって厚さ800nmの窒化硅素(SiN)膜１８を堆積した。次に、裏面にニッケル(厚さ200nm。以下、Niと記す。)を蒸着し、1000℃、20分間の熱処理を行ってオーミック電極１８を形成した。次いで、表面側にチタン/アルミニウム(チタン: 200nm/アルミニウム: 850nm。以下、チタンをTiと記す。)を蒸着してショットキー電極１５を形成した。ショットキー電極１５は、Ti層１５ａとAl層１５ｂからなる。ショットキー電極１５は500℃、30分間の熱処理を行って安定化させた。ダイオードの表面はポリイミド１７を塗布して保護した。ショットキー電極１５とガードリング領域１４の重なりは20μｍであり、ショットキー電極直径を300μmφ〜3mmφの間で変化させて多数のダイオードを作製した。
【００３２】
ここで、図２を参照して、ＳｉＣ単結晶の（０３−３８）面について説明する。同図に示すように、（０３−３８）面は、［０００１］方向に対して約３５゜（３５．２６゜）の傾きを有し、［０００１］方向と垂直な面に対して約５５゜（５４．７４゜）の傾いている。
【００３３】
次に、図３を参照して、基板１１の作製過程を説明する。通常、ＳｉＣ単結晶を成長させるに際して、＜０００１＞方向に延びるマイクロパイプや、＜０００１＞方向と垂直な面に広がる積層欠陥がＳｉＣ単結晶の内部に含まれることが多い。そして、多数のマイクロパイプや積層欠陥が表面に露出したＳｉＣ単結晶を用いて素子を作製すると、リーク電流等が発生するおそれがある。
【００３４】
本実施形態では、基板１１の作製にあたって、｛０３−３８｝面を露出させた種結晶３０を用いている。すると、種結晶３０の表面３０ｕは、マイクロパイプ４２（図中一点鎖線で示す）が延びる＜０００１＞方向に対して約３５゜の傾きを有することになる。このため、ある程度ＳｉＣ単結晶４０を成長させると、マイクロパイプ４２はＳｉＣ単結晶４０の側面４０ｓに到達し、マイクロパイプ４２が表面４０ｕに到達する事態を抑制することができる。また、種結晶３０の表面３０ｕは、積層欠陥４４（図中破線で示す）が広がる面、すなわち＜０００１＞方向と垂直な面に対して約５５゜の傾きを有する。このため、ある程度ＳｉＣ単結晶４０を成長させると、積層欠陥４４はＳｉＣ単結晶４０の側面４０ｓに到達し、積層欠陥４４が表面４０ｕに到達する事態を抑制することができる。
【００３５】
そして、このようにマイクロパイプ４２および積層欠陥４４が殆ど存在しないＳｉＣ単結晶４０をスライスして、上記基板１１が得られている。また、基板１１の表面は、種結晶３０に倣って｛０３−３８｝面となっている。そして、基板１１上に成長させたバッファ層１２とドリフト層１３は、基板１１に倣っていずれも結晶欠陥が極めて少ないものとなっている。
【００３６】
また、図４に示すように、種結晶３０の表面３０ｕを本実施形態のように｛０３−３８｝面とせず、この｛０３−３８｝面に対して約１０゜以内のオフ角αだけ傾けた面としても、同様に、成長させられたＳｉＣ単結晶４０の表面４０ｕにマイクロパイプ４２および積層欠陥４４が到達する事態を抑制することができる。さらに、オフ角αは５゜以内であることが好ましく、より好適には、３゜以内であることが好ましい。すなわち、種結晶の表面が｛０３−３８｝面に近くなるほど、ＳｉＣ単結晶４０の表面４０ｕにマイクロパイプ４２および積層欠陥４４が到達する事態を確実に抑制することができる。また、このように種結晶３０の表面３０ｕを｛０３−３８｝面に対して約１０゜以内のオフ角αだけ傾けた面とした場合は、基板１１に成長させるバッファ層１２とドリフト層１３についても、表面が｛０３−３８｝面に対してオフ角α傾いた面となる。
【００３７】
次に、図５を参照して、作製したショットキーダイオード（1mmφ）の典型的な電流−電圧特性を示す。順方向特性は、結晶の面方位依存性は小さく、オン抵抗3〜4mΩ・cm²という良好な値が得られた。順方向特性の片対数プロットから求めた理想因子n値は1.02〜1.05であり、障壁高さは4H型SiC｛0001｝面で1.08eV、4H型SiC｛03-38｝面で1.16eVとなった。逆方向特性では1500V以上の耐圧を達成し、しかも1000V印加時のリーク電流も10^-4A/cm^-2程度と小さかった。
【００３８】
ショットキー電極が300μmφ〜1mmφ程度の小さいダイオードでは面方位が｛0001｝面から8度のオフ角をもつ4H型SiC基板上でも同様のダイオード特性が得られたが、電極面積の大きいダイオードでは両者の間に大きな差が見られた。
【００３９】
図６は、4H型SiC｛03-38｝基板上及び面方位が｛0001｝面から8度のオフ角をもつ4H型SiC基板上の成長層を用いて作製したショットキーダイオードの耐圧(平均値)の電極面積依存性を示すグラフである。各電極面積について、少なくとも20個のダイオードを測定して耐圧の平均値を求めた。面方位が｛0001｝面から8度のオフ角をもつ4H型SiC基板上の成長層を用いて作製したショットキーダイオードでは、電極面積が7.9x10^-3cm²（1mmφ）を超えると急激に耐圧が低下する。これに対して、4H型SiC｛03-38｝基板上に作製したダイオードは、7x10^-2cm²（3mmφ）の電極面積でも高い耐圧を維持している。この3mmφのダイオードで耐圧1200Vを基準にして歩留まりを求めると、4H型SiC｛0001｝ダイオードで13％、4H型SiC｛03-38｝ダイオードでは72％となった。
【００４０】
また、耐圧だけでなく、逆方向1000V印加時のリーク電流密度の平均値を電極直径3mmφのダイオードで比較すると、面方位が｛0001｝面から8度のオフ角をもつ4H型SiC基板上に作製したダイオードでは9x10^-2A/cm^-2、｛03-38｝面上のダイオードでは3x10^-4A/cm²となり、二桁以上の差が認められた。これは、4H型SiC｛03-38｝面を用いることによって、基板からのマイクロパイプやらせん転位の貫通が抑制され、高品質SiC結晶が得られたからであると考えられる。また、4H型SiC｛03-38｝面を用いることによって成長表面、及びイオン注入により形成したガードリング部の表面の平坦性が良くなり、ショットキー電極/SiC界面での電界集中が低減されるという効果も寄与していると思われる。この実施例ではBイオン注入によってガードリングを形成したが、Alイオン注入を用いた場合でも同様の効果があった。
【００４１】
以上のように、本実施形態では、ショットキーダイオードのリーク電流を低減することができ、安定した動作を確実に実現できるとともに、大面積化においても歩留まりを高くすることができる。
【００４２】
［第２実施形態］
次に、図７を参照して、本発明の第２実施形態を説明する。本実施形態は、ショットキーダイオードに関するものである。実施例として、中間層としてn^--型層を積層した面方位が｛03-38｝面および｛0001｝面の４Ｈ型SiCショットキーダイオードを作製した。
【００４３】
高不純物濃度のｎ型SiC基板３４上に低不純物濃度のn^-型エピタキシャル層３６を成長させ、さらに低不純物濃度のn^--型エピタキシャル層３８を成長させた。そして、この積層体の上下に、Ti/Alのショットキー電極３７、Niのオーミック電極３５を形成して、ダイオードを完成させた。SiC基板３４の不純物濃度は1×10¹⁹cm^-3、厚さ３３０μm、n^--型エピタキシャル層３８の不純物濃度は3×10¹⁵cm^-3とし、厚さを５nmおよび10nmとした。また、比較のためn^--型層を形成しないダイオードも作製した。
【００４４】
上記のようなn^--型層を形成することでリーク電流を抑制できることが知られているが、n^--型層を形成するとｏｎ抵抗が増加する。本実施形態においては、ショットキー電極を形成した面方位が｛03-38｝のダイオードでは、n^--型層の厚みを5nmとした場合でも、ショットキー電極を形成した面方位が｛0001｝のダイオードにおいてn^--型層の厚みを10nmとした場合と同等のリーク電流の抑制効果が得られた。この理由としては、4H型｛03-38｝面を用いることによって、基板からのマイクロパイプやらせん転移の貫通が抑制され、n^-型エピタキシャル層とn^--型エピタキシャル層およびショットキー界面の平坦性が向上したことが考えられる。
【００４５】
［第３実施形態］
次に、図８を参照して、本発明の第３実施形態を説明する。本実施形態は、ｐｎ接合ダイオードに関するものである。実施例および比較例として、それぞれn型の4H型SiC(03-38)基板２１、及び4H型SiC(0001)8°オフ基板（比較例）上に形成したn型の4H型SiCエピタキシャル成長層２２にAlイオンを注入することによってプレーナ型のpn接合ダイオード２０を作製した。ｐ型ＳｉＣ層とｎ型ＳｉＣ層の主たる接合面（図中水平方向に広がる面）は、｛03-38｝面となっている。
【００４６】
デバイス作製に用いた基板２１は、改良レーリー法によって成長したインゴットをスライスし、鏡面研磨することによって作製した。基板２１は全てn型で、ホール効果測定によって求めたキャリヤ濃度は8〜9x10¹⁸cm^-3、厚さは160〜210μmである。この上に、CVD法によって窒素ドープn型SiC層２２をエピタキシャル成長した。成長層２２はバッファ層２２ａとドリフト層２２ｂからなり、バッファ層２２ａはドナー濃度1〜5x10¹⁷cm^-3、膜厚は4μm、ドリフト層２２ｂはドナー濃度1〜2x10¹⁵cm^-3、膜厚は75μmである。主な成長条件は下記の通りである。
【００４７】

【００４８】

【００４９】
この実験では、高い耐圧を得るために高純度・厚膜成長層を短時間で成膜できるように、高温での高速成長を行った。このようにして作製したSiCエピタキシャルウェハを用いて、図８に示す構造のプレーナ型pn接合ダイオードを作製した。まず、p型アノード２４を形成するために、Alイオンを720keV、400keV、280keV、160keV、80keV、40keV、20keVの7段階で注入した。総ドーズ量は4x10¹⁵cm^-2である。各注入エネルギーのドーズ量を2.7x10¹³cm^-2 (720keV)、1.8x10¹³cm^-2 (400keV)、1.2x10¹³cm^-2 (280keV)、1.0x10¹³cm^-2 (160keV)、7.2x10¹⁴cm^-2 (80keV)、4.2x10¹⁴cm^-2 (40keV)、1.3x10¹⁴cm^-2 (20keV)とすることによって、深さ約0.7μmのp型層の内、表面約0.2μmが10²⁰cm^-3以上の高濃度層２５となるドーピングプロファイルを形成した。
【００５０】
次に、p型アノード領域端部での電界集中、絶縁破壊を抑制するために、この周囲に幅300μm、深さ0.7μmのp型ガードリング２３を設けた。ガードリング２３もAlのイオン注入により形成した。Alイオン注入のエネルギーは同じく20〜720keVの7段階でトータルドーズ量は1.0x10¹³cm^-2である。ガードリング形成時には、注入層がボックスプロファイルとなるよう設計した。イオン注入は全て室温で行い、イオン注入のマスクにはAl(厚さ5μm)、あるいはCVDにより形成したSiO₂膜(厚さ6μm)を用いた。注入イオン活性化のための熱処理はArガス雰囲気中で1500℃、30分の条件で行った。熱処理後、1150℃、2時間のウェット酸化により熱酸化膜を形成し、さらにCVDによって厚さ800nmのSiO2膜３１を堆積した。次に、裏面にNi(厚さ200nm)、表面にNi/Al(Ni: 200nm/Al: 1200nm)を蒸着し、Ar雰囲気中で1000℃、20分間の熱処理を行ってオーミック電極２６，２７を形成した。ダイオードの表面はポリイミド２８を塗布して保護した。p型アノードのサイズは3mm角（面積0.09cm²）とした。
【００５１】
図９に、作製したプレーナ型pnダイオード（3mm角）の典型的な電流−電圧特性を示す。順方向、逆方向特性とも、明らかな面方位依存性が見られた。
【００５２】
まず、順方向特性に着目すると、4H型SiC｛0001｝面上に作製したダイオードは比較的電流が流れにくく、5A程度以上では約12mΩ・cm²の直列抵抗（オン抵抗）によって電気伝導が支配される。一方、4H型SiC｛03-38｝面上に作製したダイオードでは、オン抵抗は2〜3mΩ・cm²と非常に小さく、約2.8Vの立ち上がり電圧より高い領域では急激に電流が増大する。4H型SiC｛03-38｝面上に作製したダイオードでは30A(333A/cm²)という高い電流を3.9Vの電圧降下で達成することができた。これは、4H型SiC｛0001｝面を用いた場合には、p型アノードの表面部に形成した高濃度p型層の電気的活性化率が低いために抵抗が高いこと、及びこのp型層への電極の接触抵抗が高いことが原因と考えられる。4H型SiC｛03-38｝面を用いると、室温注入でも低抵抗・高濃度ｐ型層が形成できるので、この部分の抵抗と接触抵抗を大幅に低減できる。
【００５３】
また、逆方向特性では4H型SiC｛0001｝面を用いたダイオードの耐圧が5210Vに留まっているのに対し、4H型SiC｛03-38｝面を用いたダイオードでは8860Vもの高耐圧を得ることができた。逆方向バイアス時に4500Vを印加した場合のリーク電流は、4H型SiC｛0001｝面を用いたダイオードで3x10^-5A/cm²、4H型SiC｛03-38｝面を用いたダイオードで5x10^-8A/cm²となり、やはり明確な差が見られた。
【００５４】
また、絶縁破壊時のアバランシェ電流に着目すると、4H型SiC｛03-38｝面を用いたダイオードでは絶縁破壊時に5A(55A/cm²)まで電流を増してもダイオードの物理的破壊に至らない安定な特性が得られた。しかし、4H型SiC｛0001｝を用いたダイオードでは1A(11A/cm²)を超えると物理的破壊によって整流特性が著しく悪化するダイオードが大半を占めた。これは、4H型SiC｛03-38｝面を用いることによって、基板からのマイクロパイプやらせん転位の貫通が抑制され、高品質SiC結晶が得られたからであると考えられる。
【００５５】
このようにして作製したダイオードの+4Vと‐1000Vの間のスイッチング特性や高温(300℃)でのオフ特性（‐3000Ｖ）の長期信頼性には特に面方位依存性が見られなかったが、オン特性（200A/cm²）の長期信頼性には面方位による差が認められた。
【００５６】
図１０は、4H型SiC｛03-38｝面を用いた基板上、あるいは4H型SiC｛0001｝面から8度オフした基板上の成長層を用いて作製したpnダイオードに順方向電流18A(200A/cm²)を長時間流し続けたときの順方向電圧降下をプロットしたものである。4H型SiC｛0001｝面を用いたダイオードでは約3000secを超えた付近から電圧降下が増大し始め、10000sec後には初期の3.6Vから4.7Vまで増大した。しかしながら、4H型SiC｛03-38｝面を用いたダイオードでは10000sec後も電圧降下は3.7Vであり、ほとんど劣化していない。この原因を調べるために、長期信頼性試験を行ったダイオードを透過電子顕微鏡(TEM)により観察したところ、劣化した4H型SiC｛0001｝面を用いたダイオードでは[0001]面に多数の積層欠陥が発生していること、及び4H型SiC｛03-38｝面を用いたダイオードではこのような積層欠陥の発生が見られないことがわかった。
【００５７】
この積層欠陥の発生機構は現在のところ明らかでないが、III-V族半導体の発光ダイオードでは、順方向バイアス時にキャリヤ再結合によって放射されるエネルギーが結晶歪みの大きい部分に部分転位を発生させ、この部分転位が最密充填面内に伸びることによって積層欠陥が形成されることが知られている。4H型SiC｛0001｝面の場合も順方向バイアス時に同様の現象が起こり、最密充填面に相当する[0001]面に積層欠陥が発生したものと推測される。この積層欠陥の影響によって少数キャリヤ寿命が低下し、順方向電圧降下が増大したものと思われる。4H型SiC｛03-38｝面を用いたダイオードの場合にこのような積層欠陥の発生が抑制される理由は、この面ではSiとC原子が適度に混在するので、pn接合界面における歪みが非常に小さく、部分転位や積層欠陥などの欠陥が発生しにくいものと思われる。また、イオン注入後のアニーリング熱処理によって損傷がほぼ完全に除去できるので、欠陥発生の引き金になる歪みや点欠陥の集合体が非常に少ないことも寄与している。なお、この実施例ではAlイオン注入によってガードリングを形成したが、Bイオン注入を用いた場合でも同様の効果がある。
【００５８】
［第４実施形態］
次に、図１１を参照して、本発明の第４実施形態を説明する。本実施形態は、ショットキーダイオードの発展形である高耐圧JBS(Junction Barrier Schottky)ダイオードに関するものである。
【００５９】
実施例および比較例として、それぞれn型4H-SiC(03-38)、および4H-SiC(0001)8°オフ基板上に形成したｎ型4H-SiCエピタキシャル成長層を用いてJBSダイオードを作製した。デバイス作製に用いた基板５１は、改良レーリー法によって成長したインゴットをスライスし、鏡面研磨することによって作製した。基板５１は全てn型で、ホール効果測定によって求めたキャリヤ密度は8x10¹⁸cm^-3、厚さは180μmである。この上に、CVD法によって窒素ドープn型SiC層５２，５３をエピタキシャル成長した。成長層はバッファ層５２とドリフト層５３からなり、バッファ層５２はドナー密度2~5x10¹⁷cm^-3、膜厚は2μm、ドリフト層５３はドナー密度4x10¹⁵cm^-3、膜厚は18μmである。主な成長条件は下記の通りである。
【００６０】

【００６１】

【００６２】
このようにして作製したSiCエピタキシャルウェーハを用いて、図１１に示す構造のJBSダイオード５０を作製した。通常のショットキーダイオードでは、逆バイアス時にショットキー障壁の界面近傍に高電界が印加されて漏れ電流が大きくなるという問題がある。しかしながら、JBSダイオードではストライプ状に形成されたp型領域５５とｎ型ドリフト層５３の間でｐｎ接合の空乏層が広がるために、適切に設計すればこの空乏層によってショットキー界面が遮蔽され、ショットキー障壁の界面における電界が大幅に低減され、結果として漏れ電流が小さくなるという効果がある。
【００６３】
本実施例では、JBS用のｐ型ストライプ領域５５と、ショットキー電極端部での電界集中を緩和するためのガードリング５４を同一プロセスのアルミ(Al)イオン注入によって形成した。JBS用のｐ型ストライプ領域５５は、幅８μｍ、間隔１２μｍであり、p型ガードリング５４の幅は150μｍである。深さは共に約0.5μｍである。ｐ型ストライプ５５、あるいはガードリング５４形成時のAlイオン注入のエネルギーは40~560keVでトータルドーズ量は1.0x10¹³cm^-2である。イオン注入のマスクには、CVDにより形成したSiO₂膜(厚さ5μｍ)を用いた。イオン注入は全て室温で行い、注入イオン活性化のための熱処理はアルゴンガス雰囲気中1500℃、30分の条件で行った。アニールの後、1150℃、2時間のウェット酸化により熱酸化膜５６を形成し、さらにCVDによって厚さ1μｍのSiN膜５７を堆積した。
【００６４】
次に裏面にNi(厚さ200nm)を蒸着し、1000℃、20分間の熱処理を行ってオーミック電極５８を形成した。次いで表面側にNi/Al(Ni: 200nm/Al: 900nm)を蒸着してショットキー電極５９を形成した。ショットキー電極５９は、Ni層５９ａとAl層５９ｂからなる。ショットキー電極は500℃、30分間の熱処理を行って安定化させた。ダイオードの表面はポリイミド６１を塗布して保護した。ショットキー電極５９とガードリング領域５４の重なりは20μｍであり、ショットキー電極直径は２〜５ｍｍφである。これらのガードリング、電極パターン形成には、フォトリソグラフィ技術を用いた。
【００６５】
図１２に、作製したJBSダイオード５０（２ｍｍφ）の典型的な電流―電圧特性を示す。順方向特性は、結晶の面方位依存性は小さく、オン抵抗８〜９mΩcm²という良好な値が得られた。順方向特性の片対数プロットから求めた理想因子ｎ値は1.02〜1.05であり、障壁高さは4H-SiC(0001)面で1.68eV、4H-SiC(03-38)面で1.76eVとなった。ダイオードの逆方向特性では、いずれのダイオードも−1000V印加時のリーク電流が10^-7 A/cm²程度と非常に小さく、JBS構造にした効果が現れている。
【００６６】
また、100A/cm²の通電状態にあるダイオードのターンオフ特性を測定したところ、いずれも10ns以下の高速スイッチングと非常に小さい逆回復電流が観測され、少数キャリヤの注入がない理想的なスイッチング特性になっていることを確認した。しかしながら、４０個以上のダイオードを測定して求めた平均耐圧は、4H-SiC(03-38)基板上では2540V、4H-SiC(0001) 8度オフ基板上では2020Vとなり、明らかな差異が認められた。また、５ｍｍφの大きいダイオードでは、この差がより顕著になり、4H-SiC(03-38)ダイオードでは2310Vの平均耐圧を維持しているのに対し、4H-SiC(0001)8度オフ基板上では平均耐圧が1470Vまで低下した。これは、4H-SiC(03-38)面を用いることによって、基板からのマイクロパイプやらせん転位の貫通が抑制され、高品質SiC結晶が得られたからであると考えられる。また、4H-SiC(03-38)面を用いることによって成長表面、およびイオン注入により形成したp型ストライプやガードリング部の表面の平坦性がよくなり、ショットキー電極/SiC界面での電界集中が低減されるという効果も寄与していると思われる。この実施例ではAlイオン注入によってガードリングを形成したが、Bイオン注入を用いた場合でも同様の効果がある。
【００６７】
［第５実施形態］
次に、図１３を参照して、本発明の第５実施形態を説明する。本実施形態は、ショットキーダイオードの発展形であるｐｎ(pin)ダイオードに関するものである。実施例および比較例として、n型4H-SiC(03-38)、および4H-SiC(0001)8°オフ基板上にｎ型4H-SiC、p型4H-SiCを連続的にエピタキシャル成長させ、エピタキシャルｐｎ(pin)接合ダイオード７０を作製した。ｐ層とｉ層の主たる接合面、およびｉ層とｎ層の主たる接合面（図中水平方向に広がる面）は、｛03-38｝面となっている。
【００６８】
デバイス作製に用いた基板７１は、改良レーリー法によって成長したインゴットをスライスし、鏡面研磨することによって作製した。基板７１は全てn型で、ホール効果測定によって求めたキャリヤ密度は9x10¹⁸cm^-3、厚さは200μmである。この上に、CVD法によって窒素ドープn型SiC層とアルミドープp型SiC層を連続的にエピタキシャル成長した。ｎ型成長層はバッファ層７２とドリフト層７３からなり、バッファ層７２はドナー密度3~10x10¹⁷cm^-3、膜厚は4μm、ドリフト層７３はドナー密度約1x10¹⁵cm^-3、膜厚は88μmである。また、ｐ型成長層はｐ型接合層７４とｐ⁺型コンタクト層７５からなり、ｐ型接合層７４はアクセプタ密度3x10¹⁸cm^-3、膜厚は3μm、ｐ⁺型コンタクト層７５はアクセプタ密度約1x10²⁰cm^-3、膜厚は0.8μmである。主な成長条件は下記の通りである。
【００６９】

【００７０】

【００７１】

【００７２】

【００７３】
この実験では、高い耐圧を得るために高純度・厚膜成長層を短時間で成膜できるように、高温での高速成長を行った。このようにして作製したSiCエピタキシャルウェーハを用いて、図１３に示す構造のプレーナ型ｐｎダイオード７０を作製した。
【００７４】
まず、ダイオードの素子分離を行うために、反応性イオンエッチング(RIE)によりメサ構造に加工した。RIEのエッチングガスにはNF₃とO₂を用い、圧力0.05Torr、高周波電力260Wの条件で深さ約８μｍまでエッチングした。このときのマスク材料として、CVDによって堆積したSiO₂膜(厚さ10μｍ)を用いた。
【００７５】
次に、エッチングにより形成したメサ底部での電界集中を緩和させるために、メサ底部に幅300μｍ、深さ0.7μｍのp型ガードリング７６を設けた。ガードリング７６はAlイオン注入により形成した。Alイオン注入のエネルギーは20~720keVの７段階でトータルドーズ量は1.2x10¹³cm^-2である。ガードリング形成時には、注入層がボックスプロファイルとなるよう設計した。イオン注入は全て室温で行い、イオン注入のマスクには、Al(厚さ5μｍ)を用いた。注入イオン活性化のための熱処理はアルゴンガス雰囲気中1500℃、30分の条件で行った。アニールの後、1150℃、2時間のウェット酸化により熱酸化膜を形成し、さらにCVDによって厚さ800nmのSiO₂膜７７を堆積した。
【００７６】
次に、裏面にNi(厚さ200nm)、表面側にNi/Al(Ni: 200nm/Al: 2400nm)を蒸着し、1000℃、20分間の熱処理を行ってそれぞれオーミック電極７８，７９を形成した。オーミック電極７９は、Ni層７９ａとＡl層７９ｂから構成されている。ダイオードの表面はポリイミド８０を塗布して保護した。ｐｎ接合のサイズは3ｍｍ角（面積0.09cm²）である。なお、この実施例ではAlイオン注入によってガードリング７６を形成したが、Bイオン注入を用いた場合でも同様の効果がある。
【００７７】
また、ｐｎ(pin)接合ダイオード７０においては、各層７１〜７５の接合面（図中水平方向に広がる面）は、すべて｛03-38｝面となっている。
【００７８】
図１４に、作製したエピタキシャルｐｎダイオード（3ｍｍ角）の典型的な電流―電圧特性を示す。まず順方向特性に着目すると、4H-SiC(03-38)、(0001)面上に作製したダイオードはいずれも良好な特性が得られており、オン抵抗は2〜3mΩ・cm²と非常に小さく、約2.8Vの立ち上がり電圧より高い領域では急激に電流が増大する。30A(333A/cm²)という高い電流を3.78Vの電圧降下で達成することができた。
【００７９】
一方、逆方向特性では面方位による明確な差が見られた。4H-SiC(0001)ダイオードの耐圧が5840Vに留まっているのに対し、4H-SiC(03-38)ダイオードでは9820Vもの高耐圧を得ることができた。−5000V印加時のリーク電流は、4H-SiC(0001)ダイオードで6x10^-5A/cm²、4H-SiC(03-38)ダイオードで3x10^-8A/cm²となり、やはり大きな差が見られた。また、絶縁破壊時のアバランシェ電流に着目すると、4H-SiC(03-38)ダイオードでは絶縁破壊時に5A(55A/cm²)まで電流を増してもダイオードの物理的破壊に至らない安定な特性が得られた。しかし、4H-SiC(0001)ダイオードでは1A(11A/cm²)を超えると物理的破壊によって整流特性が著しく悪化するダイオードが大半を占めた。
【００８０】
図１５に、耐圧の温度依存性を０℃〜３００℃の間で評価した結果の一例を示す。4H-SiC(03-38)ダイオードでは８０％以上のダイオードが温度上昇と共に耐圧が増大する正の温度係数を示した。この特性は、ジュール熱による発熱が著しいパワーデバイスにおいて極めて重要であり、この特性が確保できない限り信頼性を保障できないと言っても過言ではない。したがって、4H-SiC(03-38)面上では高い歩留まりで優れたダイオードを作製できると言える。
【００８１】
一方、4H-SiC(0001)ダイオードでは耐圧が正の温度係数を示すものが全体の５０％に達せず、半数以上のダイオードでは温度が上昇すると耐圧が低下するという特性を示した。この耐圧の温度依存性を決定する本質的な要因はまだ明らかではないが、半導体固有の物性が発現されればアバランシェ破壊である限り正の温度係数を示すと考えられる。したがって、耐圧が負の温度係数を示すのは、結晶中に存在する構造欠陥（転位など）の影響と推測される。
【００８２】
以上のように、4H-SiC(03-38)面を用いることによって、大きい面積でも高い耐圧と耐圧の正の温度係数を有する優れたダイオードを作製することができるので、この面方位は大容量デバイスの作製に非常に有望であると言える。この主な理由は、基板からのマイクロパイプやらせん転位の貫通が抑制され、高品質SiC結晶が得られたからであると考えられる。
【００８３】
以上、本発明者らによってなされた発明を実施形態に基づき具体的に説明したが、本発明は上記各実施形態に限定されるものではない。
【００８４】
【発明の効果】
以上説明したように、本発明によれば、ダイオードのリーク電流を低減することができ、安定した動作を確実に実現できるとともに、大面積化においても歩留まりを高くすることができる。
【図面の簡単な説明】
【図１】第１実施形態のショットキーダイオードを示す断面図である。
【図２】（０３−３８）面の説明図である。
【図３】面方位を｛０３−３８｝とする種結晶上にＳｉＣ単結晶を成長させた場合のマイクロパイプおよび積層欠陥の状態を示す断面図である。
【図４】｛０３−３８｝面からオフ角α傾いた面を示す図である。
【図５】第１実施形態のショットキーダイオードの典型的な電流−電圧特性を示す図である。
【図６】第１実施形態のショットキーダイオードの耐圧の電極面積依存性を示すグラフである。
【図７】第２実施形態のショットキーダイオードを示す断面図である。
【図８】第３実施形態のpn接合ダイオードを示す断面図である。
【図９】第３実施形態のpn接合ダイオードの典型的な電流−電圧特性を示す図である。
【図１０】第３実施形態のpn接合ダイオードに順方向電流18A(200A/cm²)を流し続けたときの順方向電圧降下を示す図である。
【図１１】第４実施形態のJBS(Junction Barrier Schottky)ダイオードを示す図である。
【図１２】第４実施形態のJBSダイオードの典型的な電流―電圧特性を示す図である。
【図１３】第５実施形態のpn(pin)ダイオードを示す断面図である。
【図１４】第５実施形態のpn(pin)ダイオードの典型的な電流―電圧特性を示す図である。
【図１５】第５実施形態のダイオードの耐圧の温度依存性を０℃〜３００℃の間で評価した結果を示す図である。
【符号の説明】
１０…ショットキーダイオード、１１…n⁺型基板、１２…n型バッファ層、１３…n型ドリフト層、１４…ガードリング領域、１５…ショットキー電極、１８…オーミック電極、２０…pn接合ダイオード、２１…n⁺型基板、２２ａ…n型バッファ層、２２ｂ…n型ドリフト層、２３…ｐ型ガードリング、２４…ｐ型アノード、２５…高濃度層、３０…種結晶、４２…マイクロパイプ、４４…積層欠陥、５０…JBSダイオード、７０…pn(pin)接合ダイオード。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high breakdown voltage, low loss diode using silicon carbide (SiC) and a method for manufacturing the same.
[0002]
[Prior art]
In a conventional diode using silicon, for example, in order to have a withstand voltage of 1700 V or more, the concentration of the n-type active layer is 2 × 10 ¹⁴ cm ^-3 It is necessary to set the thickness to 170 μm or more, but such a diode has a practical problem because the forward voltage drop becomes large. Thus, attempts have been made to use silicon carbide (SiC), which is excellent in material pressure resistance, as a constituent material of the diode.
[0003]
On the other hand, with a conventional pn junction diode using silicon, it is relatively easy to obtain a high withstand voltage and low on-resistance, but it has a disadvantage that the switching speed is slow, so that a high-speed switching operation is required. In some cases, a Schottky diode is preferred. For example, a silicon pn junction diode can be used at a voltage of about 600 V, but there is a problem of noise due to accumulated charges because the response speed is slow.
[0004]
From the above points, diodes using silicon carbide have been studied. However, a diode using silicon carbide has the following design and manufacturing difficulties. That is, when a reverse bias is applied to the diode, there is a disadvantage that a current path can be formed in a non-uniform portion of the interface with the metal due to disorder of the semiconductor junction interface or crystal defects, resulting in an increase in leakage current. . In order to prevent this, it is necessary to form a homogeneous interface.
[0005]
[Problems to be solved by the invention]
As described above, a high breakdown voltage diode using silicon carbide is expected as a diode having excellent breakdown voltage characteristics and capable of high-speed switching. However, due to disorder of the junction interface and crystal defects, conventional silicon carbide diodes are There was a problem that the leakage current increased. In particular, in order to pass a large amount of current, it is necessary to increase the junction area. However, if the area is increased, the probability that an interface disorder or crystal defect will be included in the junction surface increases, resulting in an increase in leakage current. It was.
[0006]
So, for example, 100A / cm ² There has been a strong demand for the emergence of a technique capable of reliably obtaining a silicon carbide diode having a withstand voltage of 600 V or higher and capable of flowing a current of several tens of A or higher at the above forward current density.
[0007]
The present invention has been made to cope with such a problem, and it is possible to surely realize a stable operation without causing an increase in leakage current, and also in a large area. An object of the present invention is to provide a high breakdown voltage diode using silicon carbide.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present inventors first focused on micropipes and stacking faults (stacking faults) that are crystal defects in a SiC single crystal substrate. A micropipe is a defect extending in the <0001> axial direction. When a SiC single crystal is epitaxially grown on a SiC single crystal substrate having a plane orientation of [0001], the micropipe reaches the surface of the single crystal, which leaks. An increase in current was incurred. As a technique for solving this problem related to micropipes, for example, a method for growing a SiC single crystal disclosed in Japanese Patent No. 2804860 is known. This method uses, as a seed crystal, a SiC single crystal that exposes a crystal plane shifted by an angle α of 60 ° to 120 ° from the {0001} plane, and more preferably a {1-100} plane or An SiC single crystal having an exposed {11-20} plane is used. If such a seed crystal is used, the number of micropipes reaching the surface of the single crystal can be reduced.
[0009]
However, the SiC single crystal growth method described in Japanese Patent No. 2804860 has the following problems. That is, as described in the Physica Status Solid (b) (No. 202, pages 163 to 175, 1997) by the inventors of the invention described in the publication, {1-100} plane or {11-20} When using a SiC single crystal with an exposed surface as a seed crystal, it is possible to control the crystal polymorphism and suppress the arrival at the surface of the micropipe, but high-density stacking faults (stacking faults) There was a problem of exposure to the surface. This stacking fault spreads in a planar shape when a crystal is grown. When a diode is manufactured using a SiC single crystal with the stacking fault exposed on the surface, the SiC single crystal with the micropipe exposed on the surface is used. As in the case, a leak current is generated.
[0010]
Accordingly, the present inventors have focused on the fact that the leakage current of the diode can be reduced by reducing these micropipes and stacking faults, and have completed the present invention.
[0011]
(1) In the present invention, in a Schottky diode in which a Schottky electrode is joined to a 4H type SiC semiconductor, the plane orientation of the SiC semiconductor in contact with the Schottky electrode is the {03-38} plane, or this plane It is a surface which has an off angle within 10 degrees from.
[0012]
In the Schottky diode of the present invention, the plane orientation of the SiC semiconductor in contact with the Schottky electrode is the {03-38} plane or a plane having an off angle within 10 ° from this plane. Here, an SiC semiconductor having the {03-38} plane as an exposed surface will be described. When manufacturing such an SiC semiconductor, a seed crystal made of 4H type SiC with the {03-38} plane exposed is used, and a SiC single crystal is grown thereon to form a columnar SiC semiconductor. At this time, since the exposed surface of the seed crystal is inclined by about 35 ° with respect to the <0001> direction in which the micropipe extends, the micropipe can be obtained by growing a 4H type SiC single crystal on such a seed crystal. The situation where the side surface of the SiC single crystal is reached and the micropipe reaches the surface is suppressed. Further, the exposed surface ({03-38} plane) of the seed crystal has an inclination of about 55 ° with respect to the plane where stacking faults spread, that is, the plane perpendicular to the <0001> direction. If a 4H type SiC single crystal is grown on the surface, the stacking fault reaches the side surface of the SiC single crystal, and the situation where the stacking fault reaches the surface is suppressed.
[0013]
And, by forming the Schottky electrode on the 4H type SiC semiconductor with reduced micropipe and stacking faults in this way, the leakage current of the Schottky diode can be reduced, and stable operation can be realized reliably. Even when the area is increased, the yield can be increased.
[0014]
In addition, the following may be considered as the reason why the leakage current is reduced in the present invention. That is, the 4H type SiC [03-38] plane is different from the [0001] plane, and a 4H type periodic structure appears at the interface. Therefore, even if the effect of turbulence occurs in the interface atoms, the turbulence is minimized by the potential of the periodic structure appearing on the surface, and the generation of crystal defects is also suppressed. On the other hand, in the [0001] plane, only silicon atoms or carbon atoms appear on the surface, and since the potential force of the periodic structure of SiC does not work, the interface is likely to be disturbed. The fact that a high-performance interface can be obtained using the 4H-type SiC [03-38] plane among the planes deviated from the close-packed plane is a result of the study of various plane orientations by the present inventors. The reason why particularly good results were obtained with 4H-type SiC [03-38] is thought to be because the bonds of atoms appear on the surface relatively periodically despite being a surface away from the most dense surface. .
[0015]
Even if the exposed surface of the SiC semiconductor is not the {03-38} plane, but is a plane tilted by an off angle within about 10 ° with respect to the {03-38} plane, the same effect as described above can be obtained. it can.
[0016]
(2) The pn junction diode of the present invention is a pn junction diode formed by forming a pn junction on a 4H type SiC semiconductor, wherein the main junction surface between the p layer and the n layer is the {03-38} of the SiC semiconductor. It is formed in the surface or the surface which has an off angle within 10 degrees from this surface.
[0017]
In the pn junction diode of the present invention, since the pn junction is formed in the 4H type SiC semiconductor with few defects as described above, the p layer and the n layer are particularly joined with a smooth surface having few defects as an interface. Therefore, leakage current can be reduced, stable operation can be reliably realized, and yield can be increased even in a large area.
[0018]
(3) The pin junction diode of the present invention is a pin junction diode formed by forming a pin junction on a 4H type SiC semiconductor, wherein the main junction surface between the p layer and the i layer and the main junction surface between the i layer and the n layer are The SiC semiconductor is formed on a {03-38} plane or a plane having an off angle of 10 ° or less from this plane.
[0019]
In the pin junction diode of the present invention, since the pin junction is formed in the 4H type SiC semiconductor with few defects as described above, in particular, the p layer, the i layer, and the i layer with the smooth surface with few defects as the interface Since the n layers are bonded to each other, the leakage current can be reduced, stable operation can be realized with certainty, and the yield can be increased even when the area is increased.
[0020]
(4) A method for manufacturing a Schottky diode according to the present invention is a method for manufacturing a Schottky diode in which a Schottky electrode is joined to a 4H-type SiC semiconductor. The {03-38} plane or within 10 ° from this plane A step of growing a 4H type SiC single crystal on a seed crystal made of a SiC single crystal with an exposed surface having an off angle, and the {03-38} plane of the grown 4H type SiC single crystal, or Forming a Schottky electrode on a surface having an off angle of 10 ° or less from this surface.
[0021]
In the manufacturing method of the Schottky diode of the present invention, since the Schottky diode is manufactured by forming the Schottky electrode on the 4H type SiC semiconductor with few defects as described above, the leakage current can be reduced and stable. The operation can be realized with certainty, and the yield can be increased even when the area is increased.
[0022]
(5) A method for manufacturing a pn junction diode according to the present invention is a method for manufacturing a pn junction diode in which a pn junction is formed on a 4H type SiC semiconductor, and the {03-38} plane or within 10 ° from this plane. A step of growing a 4H type SiC single crystal on a seed crystal composed of a SiC single crystal with an exposed off-angle plane, and the {03-38} plane of the grown 4H type SiC single crystal, or Forming a pn junction so that a main junction surface of the p layer and the n layer is located on a plane having an off angle of 10 ° or less from this plane.
[0023]
In the method of manufacturing a pn junction diode according to the present invention, a pn junction diode is formed by forming a pn junction on a 4H type SiC semiconductor with few defects as described above. In particular, a smooth surface with few defects is used as an interface. Since the p-layer and the n-layer are joined, leakage current can be reduced, stable operation can be realized reliably, and the yield can be increased even when the area is increased.
[0024]
(6) A method for manufacturing a pin junction diode according to the present invention is a method for manufacturing a pin junction diode in which a pin junction is formed on a 4H type SiC semiconductor, and the {03-38} plane, or within 10 ° from this plane. A step of growing a 4H type SiC single crystal on a seed crystal composed of a SiC single crystal with an exposed off-angle plane, and the {03-38} plane of the grown 4H type SiC single crystal, or Forming a pin junction so that a main junction surface between the p-layer and the i-layer and a main junction surface between the i-layer and the n-layer are located on a plane having an off angle of 10 ° or less from this plane. It is characterized by.
[0025]
In the method of manufacturing a pin junction diode according to the present invention, a pin junction diode is formed by forming a pin junction on a 4H type SiC semiconductor with few defects as described above. In particular, a smooth surface with few defects is used as an interface. Since the p-layer and the i-layer, and the i-layer and the n-layer are joined to each other, the leakage current can be reduced, stable operation can be surely realized, and the yield can be increased even when the area is increased. it can.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of a Schottky diode, a pn junction diode, a pin junction diode, and a manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, the experimental results will be described together. In the following description, the crystal lattice direction and the lattice plane may be used. Here, the lattice direction and the lattice plane symbols will be described. The individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, as for the negative index, “−” (bar) is attached to the number in terms of crystallography, but a negative sign is attached before the number for the convenience of preparing the specification.
[0027]
[First Embodiment]
FIG. 1 is a cross-sectional view showing a Schottky diode 10 of this embodiment. n-type 4H-type SiC (hereinafter referred to as SiC) n-type on a substrate using the {03-38} plane and on a 4H-type SiC substrate whose plane orientation is 8 degrees off the {0001} plane A Schottky diode 10 was fabricated by forming a 4H type SiC epitaxial growth layer. Incidentally, “H” in the 4H type means a hexagonal crystal system, and “4” means a crystal structure in which the atomic stacking is four layers and one period.
[0028]
The substrate 11 used for device fabrication was fabricated by slicing and mirror polishing an ingot grown by the improved Rayleigh method. The substrate 11 is all n-type, and the carrier concentration determined by Hall effect measurement is 8 to 9 × 10 ¹⁸ cm ^-3 The thickness is 160-210 μm. In this device, since current flows in the vertical direction, it is effective to reduce the resistance of the substrate and use a thin substrate. An n-type SiC layer using nitrogen as a dopant was epitaxially grown thereon by chemical vapor deposition (hereinafter referred to as CVD). The growth layer is composed of a buffer layer 12 and a drift layer 13, and the buffer layer 12 has a donor concentration of 1 to 5x10. ¹⁷ cm ^-3 The film thickness is 2 μm and the drift layer 13 has a donor concentration of 6 to 8 × 10 ¹⁵ cm ^-3 The film thickness is 12 μm. Further, the surface of each of the buffer layer 12 and the drift layer 13 is a {03-38} plane. The main growth conditions are as follows. In the following, the flow rate is indicated by sccm, but when 1 sccm is converted to the SI unit system, it is 1 × 10 in the standard state. ^-3 l / min.
[0029]

[0030]

[0031]
A Schottky diode 10 having the structure shown in FIG. 1 was produced using the SiC epitaxial wafer thus produced. First, a p-type guard ring 14 having a width of 150 μm and a depth of 0.5 μm was provided around the Schottky electrode in order to suppress electric field concentration and dielectric breakdown at the end of the Schottky electrode. The guard ring 14 was formed by ion implantation of boron (hereinafter referred to as B). B ion implantation energy is 30 ~ 280keV and total dose is 1.1x10 ¹³ cm ^-2 It is. For the ion implantation mask, a 4 μm thick aluminum (hereinafter referred to as Al) film or a 5 μm thick silicon oxide (SiO 2) film formed by a CVD method is used. ₂ ) A membrane was used. The heat treatment for activating the implanted ions was performed in an Ar gas atmosphere at 1500 ° C. for 30 minutes. After the heat treatment, a thermal oxide film 19 was formed by wet oxidation at 1150 ° C. for 2 hours, and an 800 nm thick silicon nitride (SiN) film 18 was further deposited by CVD. Next, nickel (thickness: 200 nm; hereinafter referred to as Ni) was vapor-deposited on the back surface, and heat treatment was performed at 1000 ° C. for 20 minutes to form an ohmic electrode 18. Next, titanium / aluminum (titanium: 200 nm / aluminum: 850 nm; hereinafter, titanium is referred to as Ti) was deposited on the surface side to form the Schottky electrode 15. The Schottky electrode 15 includes a Ti layer 15a and an Al layer 15b. The Schottky electrode 15 was stabilized by heat treatment at 500 ° C. for 30 minutes. The surface of the diode was protected by applying polyimide 17. The overlap between the Schottky electrode 15 and the guard ring region 14 is 20 μm, and a large number of diodes were manufactured by changing the Schottky electrode diameter between 300 μmφ and 3 mmφ.
[0032]
Here, the (03-38) plane of the SiC single crystal will be described with reference to FIG. As shown in the figure, the (03-38) plane has an inclination of about 35 ° (35.26 °) with respect to the [0001] direction and about 55 with respect to a plane perpendicular to the [0001] direction. It is tilted by ゜ (54.74 °).
[0033]
Next, a manufacturing process of the substrate 11 will be described with reference to FIG. Usually, when a SiC single crystal is grown, a micropipe extending in the <0001> direction or a stacking fault extending in a plane perpendicular to the <0001> direction is often included in the SiC single crystal. If a device is fabricated using a SiC single crystal having a large number of micropipes and stacking faults exposed on the surface, a leakage current or the like may occur.
[0034]
In the present embodiment, the seed crystal 30 with the {03-38} plane exposed is used in the production of the substrate 11. Then, the surface 30u of the seed crystal 30 has an inclination of about 35 ° with respect to the <0001> direction in which the micropipe 42 (indicated by a one-dot chain line in the figure) extends. For this reason, when the SiC single crystal 40 is grown to some extent, the micropipe 42 reaches the side surface 40s of the SiC single crystal 40, and the situation where the micropipe 42 reaches the surface 40u can be suppressed. Further, the surface 30u of the seed crystal 30 has an inclination of about 55 ° with respect to the surface where the stacking fault 44 (shown by a broken line in the figure) spreads, that is, the surface perpendicular to the <0001> direction. For this reason, when the SiC single crystal 40 is grown to some extent, the stacking fault 44 reaches the side surface 40s of the SiC single crystal 40, and the stacking fault 44 can be prevented from reaching the surface 40u.
[0035]
Then, the substrate 11 is obtained by slicing the SiC single crystal 40 in which the micropipes 42 and the stacking faults 44 hardly exist in this way. The surface of the substrate 11 is a {03-38} plane following the seed crystal 30. The buffer layer 12 and the drift layer 13 grown on the substrate 11 both have very few crystal defects following the substrate 11.
[0036]
Further, as shown in FIG. 4, the surface 30u of the seed crystal 30 is not a {03-38} plane as in this embodiment, but only an off angle α within about 10 ° with respect to this {03-38} plane. Similarly, with respect to the inclined surface, the situation where the micropipe 42 and the stacking fault 44 reach the surface 40u of the grown SiC single crystal 40 can be suppressed. Further, the off angle α is preferably within 5 °, and more preferably within 3 °. That is, the closer the surface of the seed crystal is to the {03-38} plane, the more reliably the situation where the micropipe 42 and the stacking fault 44 reach the surface 40 u of the SiC single crystal 40. In addition, when the surface 30u of the seed crystal 30 is inclined by an off angle α within about 10 ° with respect to the {03-38} plane in this way, the buffer layer 12 and the drift layer 13 grown on the substrate 11 are used. As for the surface, the surface is inclined by an off angle α with respect to the {03-38} plane.
[0037]
Next, a typical current-voltage characteristic of the manufactured Schottky diode (1 mmφ) is shown with reference to FIG. The forward characteristics are less dependent on the crystal plane orientation and have an on-resistance of 3-4 mΩ · cm. ² A good value was obtained. The ideal factor n value obtained from the semilogarithmic plot of the forward characteristics is 1.02 to 1.05, and the barrier height is 1.08 eV for the 4H SiC {0001} surface and 1.16 eV for the 4H SiC {03-38} surface. It was. With reverse characteristics, a withstand voltage of 1500V or higher is achieved, and the leakage current when 1000V is applied is 10 ^-Four A / cm ^-2 The degree was small.
[0038]
With a small diode with a Schottky electrode of about 300 μmφ to 1 mmφ, the same diode characteristics were obtained even on a 4H type SiC substrate having an off-angle of 8 degrees from the {0001} plane. A big difference was seen between.
[0039]
FIG. 6 shows the breakdown voltage (average) of a Schottky diode fabricated using a growth layer on a 4H type SiC {03-38} substrate and on a 4H type SiC substrate having an off angle of 8 degrees from the {0001} plane. It is a graph which shows the electrode area dependence of (value). For each electrode area, at least 20 diodes were measured and the average value of the breakdown voltage was obtained. A Schottky diode fabricated using a growth layer on a 4H-type SiC substrate having an off-angle of 8 degrees from the {0001} plane has an electrode area of 7.9x10 ^-3 cm ² If it exceeds (1mmφ), the withstand voltage will drop rapidly. In contrast, a diode fabricated on a 4H-type SiC {03-38} substrate is 7x10 ^-2 cm ² High breakdown voltage is maintained even with an electrode area of (3mmφ). With this 3 mmφ diode, the yield was calculated based on a withstand voltage of 1200 V. The yield was 13% for the 4H SiC {0001} diode and 72% for the 4H SiC {03-38} diode.
[0040]
In addition, when comparing the average value of the leakage current density when applying 1000V in the reverse direction with a diode with an electrode diameter of 3mmφ, not only withstand voltage, but on a 4H type SiC substrate with an off angle of 8 degrees from the {0001} plane 9x10 for the fabricated diode ^-2 A / cm ^-2 , 3x10 for the diode on the {03-38} plane ^-Four A / cm ² A difference of more than two digits was recognized. This is presumably because the use of the 4H-type SiC {03-38} surface suppresses the penetration of micropipes and screw dislocations from the substrate, resulting in a high-quality SiC crystal. In addition, the flatness of the growth surface and the surface of the guard ring formed by ion implantation is improved by using the 4H type SiC {03-38} surface, and the electric field concentration at the Schottky electrode / SiC interface is reduced. It seems that this effect also contributes. In this example, the guard ring was formed by B ion implantation, but the same effect was obtained even when Al ion implantation was used.
[0041]
As described above, according to the present embodiment, the leakage current of the Schottky diode can be reduced, stable operation can be reliably realized, and the yield can be increased even when the area is increased.
[0042]
[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment relates to a Schottky diode. As an example, n as an intermediate layer ^- A 4H type SiC Schottky diode having a {03-38} plane and a {0001} plane in which the mold layers were laminated was fabricated.
[0043]
On the n-type SiC substrate 34 having a high impurity concentration, n having a low impurity concentration is formed. ^- Type epitaxial layer 36 is grown, and n of low impurity concentration is further grown. ^- A type epitaxial layer 38 was grown. Then, a Ti / Al Schottky electrode 37 and a Ni ohmic electrode 35 were formed on the top and bottom of the laminate to complete the diode. The impurity concentration of the SiC substrate 34 is 1 × 10 ¹⁹ cm ^-3 , 330 μm thickness, n ^- The impurity concentration of the type epitaxial layer 38 is 3 × 10 ¹⁵ cm ^-3 The thickness was 5 nm and 10 nm. Also for comparison n ^- A diode without a mold layer was also produced.
[0044]
N as above ^- It is known that the leakage current can be suppressed by forming the mold layer. ^- When the mold layer is formed, the on-resistance increases. In the present embodiment, in a diode having a plane orientation {03-38} on which a Schottky electrode is formed, n ^- Even in the case where the thickness of the mold layer is 5 nm, in the diode whose plane orientation on which the Schottky electrode is formed is {0001}, n ^- The same leakage current suppressing effect as that obtained when the mold layer thickness was 10 nm was obtained. The reason for this is that by using the 4H type {03-38} surface, penetration of micropipes and spiral transitions from the substrate is suppressed, and n ^- Type epitaxial layer and n ^- It is considered that the flatness of the type epitaxial layer and the Schottky interface has been improved.
[0045]
[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. The present embodiment relates to a pn junction diode. As an example and a comparative example, an n-type 4H-type SiC (03-38) substrate 21 and an n-type 4H-type SiC epitaxial growth layer 22 formed on a 4H-type SiC (0001) 8 ° off substrate (comparative example), respectively. A planar type pn junction diode 20 was fabricated by implanting Al ions. The main bonding surface (surface extending in the horizontal direction in the figure) of the p-type SiC layer and the n-type SiC layer is a {03-38} plane.
[0046]
The substrate 21 used for device fabrication was fabricated by slicing an ingot grown by the modified Rayleigh method and mirror polishing. The substrate 21 is all n-type, and the carrier concentration obtained by measuring the Hall effect is 8 to 9 × 10 ¹⁸ cm ^-3 The thickness is 160-210 μm. A nitrogen-doped n-type SiC layer 22 was epitaxially grown thereon by CVD. The growth layer 22 includes a buffer layer 22a and a drift layer 22b, and the buffer layer 22a has a donor concentration of 1 to 5 × 10. ¹⁷ cm ^-3 The film thickness is 4 μm and the drift layer 22b has a donor concentration of 1 to 2 × 10 ¹⁵ cm ^-3 The film thickness is 75 μm. The main growth conditions are as follows.
[0047]

[0048]

[0049]
In this experiment, high-speed growth was performed at a high temperature so that a high purity / thick film growth layer could be formed in a short time in order to obtain a high breakdown voltage. A planar pn junction diode having the structure shown in FIG. 8 was produced using the SiC epitaxial wafer thus produced. First, in order to form the p-type anode 24, Al ions were implanted in seven stages of 720 keV, 400 keV, 280 keV, 160 keV, 80 keV, 40 keV, and 20 keV. Total dose is 4x10 ¹⁵ cm ^-2 It is. 2.7x10 dose amount for each implantation energy ¹³ cm ^-2 (720keV), 1.8x10 ¹³ cm ^-2 (400keV), 1.2x10 ¹³ cm ^-2 (280keV), 1.0x10 ¹³ cm ^-2 (160keV), 7.2x10 ¹⁴ cm ^-2 (80keV), 4.2x10 ¹⁴ cm ^-2 (40keV), 1.3x10 ¹⁴ cm ^-2 By setting (20 keV), about 0.2 μm of the surface of the p-type layer with a depth of about 0.7 μm is 10 ²⁰ cm ^-3 A doping profile to be the high concentration layer 25 was formed.
[0050]
Next, in order to suppress electric field concentration and dielectric breakdown at the end of the p-type anode region, a p-type guard ring 23 having a width of 300 μm and a depth of 0.7 μm was provided around the periphery. The guard ring 23 was also formed by Al ion implantation. The energy of Al ion implantation is also 7 steps from 20 to 720keV, and the total dose is 1.0x10. ¹³ cm ^-2 It is. When forming the guard ring, the injection layer was designed to have a box profile. All ion implantation is performed at room temperature, and the mask for ion implantation is Al (thickness 5 μm) or SiO formed by CVD. ₂ A membrane (thickness 6 μm) was used. The heat treatment for activating the implanted ions was performed in an Ar gas atmosphere at 1500 ° C. for 30 minutes. After the heat treatment, a thermal oxide film was formed by wet oxidation at 1150 ° C. for 2 hours, and an SiO 2 film 31 having a thickness of 800 nm was further deposited by CVD. Next, Ni (thickness: 200 nm) is vapor-deposited on the back surface and Ni / Al (Ni: 200 nm / Al: 1200 nm) is vapor-deposited on the front surface, and heat treatment is performed at 1000 ° C. for 20 minutes in an Ar atmosphere to form ohmic electrodes 26 and 27. Formed. The surface of the diode was protected by applying polyimide 28. The size of the p-type anode is 3mm square (area 0.09cm) ² ).
[0051]
FIG. 9 shows typical current-voltage characteristics of the fabricated planar pn diode (3 mm square). A clear orientation dependence was observed for both forward and reverse characteristics.
[0052]
First, focusing on the forward characteristics, diodes fabricated on 4H-type SiC {0001} surfaces have a relatively low current flow, and at about 5 A or more, about 12 mΩ · cm ² The electrical conduction is governed by the series resistance (ON resistance). On the other hand, in a diode fabricated on a 4H type SiC {03-38} surface, the on-resistance is 2 to 3 mΩ · cm. ² The current increases abruptly in a region that is very small and higher than the rising voltage of about 2.8V. 30 A (333 A / cm for diodes fabricated on 4H SiC {03-38} surfaces ² ) Was able to be achieved with a voltage drop of 3.9V. This is because when the 4H-type SiC {0001} plane is used, the high-concentration p-type layer formed on the surface portion of the p-type anode has a low electrical activation rate, and the p-type has a high resistance. This is considered to be due to the high contact resistance of the electrode to the layer. If a 4H type SiC {03-38} plane is used, a low-resistance and high-concentration p-type layer can be formed even at room temperature implantation, and the resistance and contact resistance of this portion can be greatly reduced.
[0053]
In reverse characteristics, the withstand voltage of the diode using the 4H type SiC {0001} surface remains at 5210V, while the diode using the 4H type SiC {03-38} surface can obtain a high withstand voltage of 8860V. I was able to. When 4500V is applied during reverse bias, the leakage current is 3x10 for a diode using a 4H SiC {0001} surface. ^-Five A / cm ² 5x10 diodes using 4H type SiC {03-38} surface ^-8 A / cm ² After all, a clear difference was seen.
[0054]
Focusing on the avalanche current at the time of dielectric breakdown, a diode using a 4H type SiC {03-38} surface is 5 A (55 A / cm at the time of dielectric breakdown). ² ) Stable characteristics were obtained even when the current was increased until the physical breakdown of the diode. However, in the diode using 4H type SiC {0001}, 1A (11A / cm ² ) Exceeded the majority of diodes whose rectification characteristics deteriorated significantly due to physical breakdown. This is presumably because the use of the 4H-type SiC {03-38} surface suppresses the penetration of micropipes and screw dislocations from the substrate, resulting in a high-quality SiC crystal.
[0055]
The diode produced in this way did not show any dependence on the plane orientation in the long-term reliability of the switching characteristics between + 4V and -1000V and the off characteristics (-3000V) at high temperature (300 ℃) ON characteristics (200A / cm ² The long-term reliability of) showed a difference depending on the plane orientation.
[0056]
FIG. 10 shows a forward current of 18 A (for a pn diode fabricated using a growth layer on a substrate using a 4H type SiC {03-38} plane or on a substrate off by 8 degrees from the 4H type SiC {0001} plane. 200A / cm ² ) Is a plot of the forward voltage drop when the flow is continued for a long time. In the diode using the 4H type SiC {0001} surface, the voltage drop started to increase from around 3000 sec. After 10,000 sec, it increased from the initial 3.6 V to 4.7 V. However, in the diode using the 4H type SiC {03-38} surface, the voltage drop is 3.7 V even after 10,000 seconds, and there is almost no deterioration. In order to investigate this cause, a diode subjected to a long-term reliability test was observed with a transmission electron microscope (TEM). In a diode using a deteriorated 4H SiC {0001} surface, many stacking faults were found on the [0001] surface. It has been found that such a stacking fault is not observed in a diode using a 4H type SiC {03-38} surface.
[0057]
The generation mechanism of this stacking fault is not clear at present, but in a III-V semiconductor light emitting diode, the energy radiated by carrier recombination during forward bias generates partial dislocations in a portion where the crystal distortion is large. It is known that stacking faults are formed by partial dislocations extending into the closest packing surface. In the case of the 4H-type SiC {0001} plane, the same phenomenon occurs during forward bias, and it is presumed that stacking faults have occurred on the [0001] plane corresponding to the closest packed surface. It is considered that the minority carrier lifetime is reduced by the influence of the stacking fault and the forward voltage drop is increased. The reason why such stacking faults are suppressed in the case of a diode using a 4H type SiC {03-38} surface is that Si and C atoms are mixed appropriately on this surface. It is very small, and it seems that defects such as partial dislocations and stacking faults are unlikely to occur. Further, since the damage can be almost completely removed by the annealing heat treatment after the ion implantation, the fact that there are very few strains and aggregates of point defects that trigger the generation of defects contributes. In this embodiment, the guard ring is formed by Al ion implantation, but the same effect can be obtained even when B ion implantation is used.
[0058]
[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The present embodiment relates to a high breakdown voltage JBS (Junction Barrier Schottky) diode, which is an advanced form of a Schottky diode.
[0059]
As Examples and Comparative Examples, JBS diodes were fabricated using n-type 4H—SiC (03-38) and n-type 4H—SiC epitaxial growth layers formed on a 4H—SiC (0001) 8 ° off substrate, respectively. The substrate 51 used for device fabrication was fabricated by slicing and mirror polishing an ingot grown by the improved Rayleigh method. The substrate 51 is all n-type, and the carrier density determined by Hall effect measurement is 8 × 10 ¹⁸ cm ^-3 The thickness is 180 μm. On this, nitrogen-doped n-type SiC layers 52 and 53 were epitaxially grown by CVD. The growth layer is composed of a buffer layer 52 and a drift layer 53, and the buffer layer 52 has a donor density of 2 to 5x10. ¹⁷ cm ^-3 The film thickness is 2 μm and the drift layer 53 has a donor density of 4 × 10 ¹⁵ cm ^-3 The film thickness is 18 μm. The main growth conditions are as follows.
[0060]

[0061]

[0062]
A JBS diode 50 having the structure shown in FIG. 11 was produced using the SiC epitaxial wafer thus produced. In a normal Schottky diode, there is a problem that a high electric field is applied near the interface of the Schottky barrier at the time of reverse bias, resulting in an increase in leakage current. However, in the JBS diode, since a depletion layer of a pn junction spreads between the p-type region 55 and the n-type drift layer 53 formed in a stripe shape, the Schottky interface is shielded by the depletion layer if appropriately designed. The electric field at the interface of the Schottky barrier is greatly reduced, and as a result, the leakage current is reduced.
[0063]
In this embodiment, the p-type stripe region 55 for JBS and the guard ring 54 for relaxing the electric field concentration at the end of the Schottky electrode are formed by the same process of aluminum (Al) ion implantation. The p-type stripe region 55 for JBS has a width of 8 μm and an interval of 12 μm, and the p-type guard ring 54 has a width of 150 μm. Both depths are about 0.5 μm. The energy of Al ion implantation when forming the p-type stripe 55 or guard ring 54 is 40 to 560 keV, and the total dose is 1.0 × 10 ¹³ cm ^-2 It is. For the mask of ion implantation, SiO formed by CVD ₂ A membrane (thickness 5 μm) was used. Ion implantation was all performed at room temperature, and heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1500 ° C. for 30 minutes. After annealing, a thermal oxide film 56 was formed by wet oxidation at 1150 ° C. for 2 hours, and a 1 μm thick SiN film 57 was further deposited by CVD.
[0064]
Next, Ni (thickness 200 nm) was vapor-deposited on the back surface, and heat treatment was performed at 1000 ° C. for 20 minutes to form an ohmic electrode 58. Next, Ni / Al (Ni: 200 nm / Al: 900 nm) was deposited on the surface side to form a Schottky electrode 59. The Schottky electrode 59 includes a Ni layer 59a and an Al layer 59b. The Schottky electrode was stabilized by heat treatment at 500 ° C. for 30 minutes. The surface of the diode was protected by applying polyimide 61. The overlap between the Schottky electrode 59 and the guard ring region 54 is 20 μm, and the Schottky electrode diameter is 2 to 5 mmφ. Photolithography technology was used to form these guard rings and electrode patterns.
[0065]
FIG. 12 shows a typical current-voltage characteristic of the manufactured JBS diode 50 (2 mmφ). The forward characteristics are less dependent on crystal plane orientation and have an on-resistance of 8-9 mΩcm. ² A good value was obtained. The ideal factor n obtained from the semilogarithmic plot of the forward characteristics is 1.02 to 1.05, and the barrier height is 1.68 eV on the 4H-SiC (0001) plane and 1.76 eV on the 4H-SiC (03-38) plane. It was. With respect to the reverse characteristics of the diodes, all diodes have a leakage current of 10 when -1000V is applied. ^-7 A / cm ² The effect of the JBS structure appears very small.
[0066]
Also 100A / cm ² When the turn-off characteristics of the diodes in the current-carrying state were measured, high-speed switching of 10 ns or less and very small reverse recovery current were observed, and it was confirmed that the switching characteristics were ideal with no minority carrier injection. did. However, the average withstand voltage obtained by measuring 40 or more diodes is 2540V on the 4H-SiC (03-38) substrate and 2020V on the 4H-SiC (0001) 8 degree off substrate. It was. In addition, this difference becomes more noticeable for large diodes with a diameter of 5 mmφ, while 4H-SiC (03-38) diodes maintain an average breakdown voltage of 2310 V, whereas 4H-SiC (0001) 8 degrees on the off-substrate Then the average withstand voltage dropped to 1470V. This is presumably because the use of the 4H—SiC (03-38) plane suppressed the penetration of micropipes and screw dislocations from the substrate, and a high-quality SiC crystal was obtained. Also, the use of 4H-SiC (03-38) surface improves the flatness of the growth surface and the surface of the p-type stripe and guard ring formed by ion implantation, and the electric field concentration at the Schottky electrode / SiC interface. It seems that the effect of reducing is also contributing. In this embodiment, the guard ring is formed by Al ion implantation, but the same effect can be obtained even when B ion implantation is used.
[0067]
[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to FIG. The present embodiment relates to a pn (pin) diode, which is an advanced form of a Schottky diode. As an example and a comparative example, n-type 4H-SiC (03-38) and 4H-SiC (0001) n-type 4H-SiC and p-type 4H-SiC were epitaxially grown on an 8 ° off-substrate, and epitaxially grown. A pn (pin) junction diode 70 was produced. The main joint surfaces of the p layer and the i layer and the main joint surfaces of the i layer and the n layer (surfaces extending in the horizontal direction in the figure) are {03-38} planes.
[0068]
The substrate 71 used for device fabrication was fabricated by slicing and mirror polishing an ingot grown by the improved Rayleigh method. The substrate 71 is all n-type, and the carrier density obtained by Hall effect measurement is 9 × 10 ¹⁸ cm ^-3 The thickness is 200 μm. On this, a nitrogen-doped n-type SiC layer and an aluminum-doped p-type SiC layer were continuously epitaxially grown by CVD. The n-type growth layer includes a buffer layer 72 and a drift layer 73, and the buffer layer 72 has a donor density of 3 to 10 × 10 ¹⁷ cm ^-3 The film thickness is 4 μm and the drift layer 73 has a donor density of about 1 × 10 ¹⁵ cm ^-3 The film thickness is 88 μm. In addition, the p-type growth layer is composed of the p-type junction layer 74 and p. ⁺ Type contact layer 75, and p-type junction layer 74 has an acceptor density of 3 × 10 ¹⁸ cm ^-3 , Film thickness is 3μm, p ⁺ Type contact layer 75 has an acceptor density of about 1 × 10 ²⁰ cm ^-3 The film thickness is 0.8 μm. The main growth conditions are as follows.
[0069]

[0070]

[0071]

[0072]

[0073]
In this experiment, high-speed growth was performed at a high temperature so that a high purity / thick film growth layer could be formed in a short time in order to obtain a high breakdown voltage. A planar pn diode 70 having the structure shown in FIG. 13 was produced using the SiC epitaxial wafer thus produced.
[0074]
First, a mesa structure was processed by reactive ion etching (RIE) in order to isolate the diode element. RIE etching gas is NF _Three And O ₂ Was etched to a depth of about 8 μm under the conditions of pressure 0.05 Torr and high frequency power 260 W. As a mask material at this time, SiO deposited by CVD ₂ A membrane (thickness 10 μm) was used.
[0075]
Next, in order to alleviate electric field concentration at the bottom of the mesa formed by etching, a p-type guard ring 76 having a width of 300 μm and a depth of 0.7 μm was provided at the mesa bottom. The guard ring 76 was formed by Al ion implantation. Al ion implantation energy ranges from 20 to 720keV with a total dose of 1.2x10 ¹³ cm ^-2 It is. When forming the guard ring, the injection layer was designed to have a box profile. Ion implantation was all performed at room temperature, and Al (thickness 5 μm) was used as a mask for ion implantation. The heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1500 ° C. for 30 minutes. After annealing, a thermal oxide film is formed by wet oxidation at 1150 ° C for 2 hours, and further, 800 nm thick SiO by CVD. ₂ A film 77 was deposited.
[0076]
Next, Ni (thickness: 200 nm) is deposited on the back surface and Ni / Al (Ni: 200 nm / Al: 2400 nm) is deposited on the front surface side, and heat treatment is performed at 1000 ° C. for 20 minutes to form ohmic electrodes 78 and 79, respectively. . The ohmic electrode 79 is composed of a Ni layer 79a and an Al layer 79b. The surface of the diode was protected by applying polyimide 80. The size of the pn junction is 3mm square (area 0.09cm ² ). In this embodiment, the guard ring 76 is formed by Al ion implantation, but the same effect can be obtained even when B ion implantation is used.
[0077]
Further, in the pn (pin) junction diode 70, all the junction surfaces (surfaces extending in the horizontal direction in the figure) of the layers 71 to 75 are {03-38} planes.
[0078]
FIG. 14 shows a typical current-voltage characteristic of the manufactured epitaxial pn diode (3 mm square). First, focusing on forward characteristics, all diodes fabricated on 4H-SiC (03-38) and (0001) planes have good characteristics, with an on-resistance of 2 to 3 mΩ · cm. ² The current increases abruptly in a region that is very small and higher than the rising voltage of about 2.8V. 30A (333A / cm ² ) Was able to be achieved with a voltage drop of 3.78V.
[0079]
On the other hand, in the reverse characteristics, a clear difference depending on the plane orientation was observed. The 4H-SiC (0001) diode has a breakdown voltage of only 5840V, while the 4H-SiC (03-38) diode has a breakdown voltage as high as 9820V. Leakage current when applying −5000V is 6x10 with 4H-SiC (0001) diode ^-Five A / cm ² 3x10 with 4H-SiC (03-38) diode ^-8 A / cm ² After all, a big difference was seen. Also, focusing on the avalanche current at the time of dielectric breakdown, 4H-SiC (03-38) diodes have 5 A (55 A / cm ² ) Stable characteristics were obtained even when the current was increased until the physical breakdown of the diode. However, with 4H-SiC (0001) diode, 1A (11A / cm ² ) Exceeded the majority of diodes whose rectification characteristics deteriorated significantly due to physical breakdown.
[0080]
In FIG. 15, an example of the result of having evaluated the temperature dependence of a proof pressure between 0 degreeC-300 degreeC is shown. Among the 4H-SiC (03-38) diodes, more than 80% of the diodes showed a positive temperature coefficient with which the withstand voltage increased with increasing temperature. This characteristic is extremely important in power devices that generate significant heat due to Joule heat, and it is no exaggeration to say that reliability cannot be guaranteed unless this characteristic can be ensured. Therefore, it can be said that an excellent diode can be manufactured with a high yield on the 4H-SiC (03-38) surface.
[0081]
On the other hand, 4H-SiC (0001) diodes with a withstand voltage having a positive temperature coefficient did not reach 50% of the total, and more than half of the diodes showed a withstand voltage drop with increasing temperature. Although the essential factor that determines the temperature dependence of the breakdown voltage is not yet clear, it is considered that a positive temperature coefficient is exhibited as long as the avalanche breakdown occurs if a physical property unique to the semiconductor is expressed. Therefore, it is presumed that the negative pressure coefficient of the withstand voltage is due to the influence of structural defects (dislocations, etc.) present in the crystal.
[0082]
As described above, by using the 4H-SiC (03-38) surface, an excellent diode having a high withstand voltage and a positive temperature coefficient of withstand voltage can be manufactured even in a large area. It can be said that it is very promising for device fabrication. The main reason for this is thought to be that high-quality SiC crystals were obtained by suppressing the penetration of micropipes and screw dislocations from the substrate.
[0083]
As mentioned above, although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above embodiments.
[0084]
【Effect of the invention】
As described above, according to the present invention, the leakage current of the diode can be reduced, stable operation can be realized with certainty, and the yield can be increased even when the area is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a Schottky diode of a first embodiment.
FIG. 2 is an explanatory diagram of a (03-38) plane.
FIG. 3 is a cross-sectional view showing the state of micropipes and stacking faults when a SiC single crystal is grown on a seed crystal with a plane orientation of {03-38}.
FIG. 4 is a diagram showing a surface inclined by an off angle α from the {03-38} plane.
FIG. 5 is a diagram showing a typical current-voltage characteristic of the Schottky diode of the first embodiment.
FIG. 6 is a graph showing the electrode area dependence of the breakdown voltage of the Schottky diode of the first embodiment.
FIG. 7 is a cross-sectional view showing a Schottky diode according to a second embodiment.
FIG. 8 is a cross-sectional view showing a pn junction diode according to a third embodiment.
FIG. 9 is a diagram showing typical current-voltage characteristics of the pn junction diode of the third embodiment.
FIG. 10 shows a forward current of 18 A (200 A / cm) in the pn junction diode of the third embodiment. ² ) Is a diagram showing a forward voltage drop when the current is kept flowing.
FIG. 11 is a diagram showing a JBS (Junction Barrier Schottky) diode according to a fourth embodiment.
FIG. 12 is a diagram showing a typical current-voltage characteristic of the JBS diode of the fourth embodiment.
FIG. 13 is a cross-sectional view showing a pn (pin) diode according to a fifth embodiment.
FIG. 14 is a diagram showing a typical current-voltage characteristic of a pn (pin) diode according to a fifth embodiment.
FIG. 15 is a graph showing the results of evaluating the temperature dependence of the breakdown voltage of the diode of the fifth embodiment between 0 ° C. and 300 ° C. FIG.
[Explanation of symbols]
10 ... Schottky diode, 11 ... n ⁺ Type substrate, 12 ... n-type buffer layer, 13 ... n-type drift layer, 14 ... guard ring region, 15 ... Schottky electrode, 18 ... ohmic electrode, 20 ... pn junction diode, 21 ... n ⁺ Type substrate, 22a ... n-type buffer layer, 22b ... n-type drift layer, 23 ... p-type guard ring, 24 ... p-type anode, 25 ... high concentration layer, 30 ... seed crystal, 42 ... micropipe, 44 ... stacking fault 50 ... JBS diode, 70 ... pn (pin) junction diode.

Claims (6)

In a Schottky diode in which a Schottky electrode is joined to a 4H type SiC semiconductor,
The Schottky diode, wherein a plane orientation of the SiC semiconductor in contact with the Schottky electrode is a {03-38} plane or a plane having an off angle within 10 ° from this plane. In a pn junction diode formed by forming a pn junction in a 4H type SiC semiconductor,
A pn junction diode, wherein a main junction plane between the p layer and the n layer is formed on the {03-38} plane of the SiC semiconductor or a plane having an off angle within 10 ° from this plane. In a pin junction diode formed by forming a pin junction in a 4H type SiC semiconductor,
The main junction surface between the p layer and the i layer and the main junction surface between the i layer and the n layer are formed on the {03-38} plane of the SiC semiconductor, or a plane having an off angle within 10 ° from this plane. A pin junction diode. In a method for manufacturing a Schottky diode in which a Schottky electrode is joined to a 4H type SiC semiconductor,
Growing a 4H-type SiC single crystal on a {03-38} plane or a seed crystal composed of an SiC single crystal exposing a plane having an off angle within 10 ° from the plane;
Forming a Schottky electrode on the {03-38} plane of the grown 4H type SiC single crystal, or a plane having an off angle within 10 ° from this plane;
A method for manufacturing a Schottky diode, comprising: In a method of manufacturing a pn junction diode formed by forming a pn junction in a 4H type SiC semiconductor,
Growing a 4H-type SiC single crystal on a {03-38} plane or a seed crystal composed of an SiC single crystal exposing a plane having an off angle within 10 ° from the plane;
A pn junction such that a main junction surface of the p layer and the n layer is located on the {03-38} plane of the grown 4H type SiC single crystal or a plane having an off angle within 10 ° from this plane. Forming a step;
The manufacturing method of the pn junction diode characterized by the above-mentioned. In a manufacturing method of a pin junction diode formed by forming a pin junction on a 4H type SiC semiconductor,
Growing a 4H-type SiC single crystal on a {03-38} plane or a seed crystal composed of an SiC single crystal exposing a plane having an off angle within 10 ° from the plane;
On the {03-38} plane of the grown 4H type SiC single crystal, or a plane having an off angle within 10 ° from this plane, the main junction plane between the p layer and the i layer and the i layer and the n layer Forming a pin junction such that the main joining surface of
The manufacturing method of the pin junction diode characterized by the above-mentioned.

Images