JP2002132577A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput of data processing accompanied with memory access in a data processing system. SOLUTION: The system comprises a memory 22 and a data processor 11 for performing access control of the memory. The memory comprises a plurality of memory banks (200A, 200B). An address input, data input-output and control signal input are enabled in synchronism with clock signals (CLK). There is provided a burst-mode that is accessed while updating the address being preset in an address counter (207). An address active command is acceptable which sets an access address in another memory bank in parallel with operation of the memory bank being activated by the burst-mode. The data processor issues the active address command for use in the memory bank which is not activated, thereby presetting the access address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system for processing image data or the like allocated on a memory in the field of information terminal equipment such as a personal computer and a workstation, and more particularly to an image processing system. The present invention relates to a technology effective when applied to a high-speed image processing system that accesses a memory at a high speed in synchronization with the image processing.

[0002]

2. Description of the Related Art In an image processing system, a drawing display processor executes drawing processing in a frame buffer in accordance with drawing commands and parameters transferred from a CPU. The drawing display processor may execute a drawing process in accordance with a drawing command and parameters previously arranged in a frame buffer or a dedicated local memory. The rendering display processor also reads necessary display data from the frame buffer in accordance with the horizontal and vertical synchronization timings and dot rate of the monitor,
Display on the monitor via the dot shifter. The clock generator creates a basic clock and a dot clock based on the reference frequency of the crystal oscillator, and supplies them to the drawing display processor and the dot shifter. As a frame buffer of such an image processing system, a DRAM (Dynamic Random Access Memory) or a multi-port DRAM having a large storage capacity can be adopted because it is necessary to arrange display data in a bit map.

[0003] Image processing systems conventionally used in facsimile machines, printers, and graphics devices include:
High-speed SRAM for local processing referring to peripheral pixels as described in JP-A-61-261969
(Static random access memory), large-capacity memory for storing code data and font data
Uses RAM.

[0004]

The trend of image processing systems in the field of information terminal equipment such as business personal computers and workstations in recent years has been to improve image quality, high-speed processing, and increase in capacity. In the case of a conventional DRAM, the configuration in which the data bus width is increased is increasing, and the multiport DRA
A configuration in which the drawing processing efficiency is improved by configuring with M is also employed. Accordingly, there has been a problem that the cost of the apparatus increases.

On the other hand, a synchronous DRAM has begun to attract attention as a high-speed, large-capacity memory. This synchronous DRAM can input and output data, addresses, and control signals in synchronization with a clock, as compared with a conventional DRAM. This is a memory capable of realizing high-speed operation and realizing high-speed access and large-capacity at a low price more than conventional DRAM. In this synchronous DRAM, the number of data to be accessed for one selected word line can be specified by, for example, a burst length. When the burst length is N, a built-in column address counter is used. Thus, the selection state of the column system is sequentially switched so that N data can be continuously read or written. An example of a document describing application of a synchronous DRAM to a main memory or graphics is Electronic Technology (1993-10).
On page 24 to page 28, "Application of High Speed DRAM to Main Memory, Graphics, etc."

The present inventor has studied to provide an image processing system that integrates a high-speed processing memory and a large-capacity memory and realizes a large-capacity and high-speed memory access at low cost. Specifically, a case where a system is configured using a synchronous DRAM as a memory having a function of latching an address, data, and a control signal in synchronization with a clock was examined, and the following points were typically clarified.

First, due to the nature of a synchronous DRAM that inputs and outputs data, addresses, and control signals in synchronization with a clock, a circuit module outputs a signal to maintain the reliability of the access operation and achieve high-speed access. The skew between data, address, control signals and clock signals must be reduced.

Secondly, in linear drawing in an arbitrary direction, a memory address is a drawing process in which memory addresses are not continuous within the same row address, and the burst length is desirably 1. On the other hand, in a rectangular solid drawing such as a memory clear, a memory address is not drawn. Since continuous drawing processing is performed within the same row address, the burst length is desirably N (N> 1), and it is desirable that the processing of changing the burst length in accordance with the contents of the drawing processing be performed on the display control system side.

Thirdly, a case in which a system is configured using a synchronous DRAM (synchronous DRAM) is being studied. By using the synchronous DRAM, the address to be accessed can be issued, and then, for example, the clock timing at which the read data is output can be specified, so that the next address can be issued before the read processing is completed. However, when issuing addresses successively, the address is limited to within the same row address, and in order to access a different row address in the same bank, a mishit process such as a precharge process is required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems which occur when a clock synchronous type memory having a high speed operation and a large capacity, such as a synchronous DRAM, is applied to an image processing system or the like. An object of the present invention is to provide a technique for realizing a high-performance image processing system, a data processing system, and a data processor therefor.

More specifically, the present invention relates to a synchronous D
It is an object of the present invention to realize a process of changing a burst length according to processing contents, which is a problem in configuring a system in which memories are integrated using a RAM. Another object is to improve the bus throughput of the memory at low cost in accordance with the burst length. It is another object of the present invention to realize the mishit processing at low cost and at high speed. It is another object of the present invention to provide a data processor which is optimal for controlling access to a clock synchronous memory having a high speed operation and a large capacity, such as a synchronous DRAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the present invention provides a synchronous D
It is roughly divided into supply of a clock signal to a memory such as a RAM, setting of a mode register for designating an operation mode thereof, and processing related to a mishit.

<< Supply of Clock >> Synchronous D enabling address input, data input / output and control signal input in synchronization with a clock signal (CLK) supplied from the outside
A bus control means (14) interfaced to a memory (22) such as a RAM; and a plurality of data processing modules coupled to the bus control means for respectively generating data and addresses for accessing the memory ( 1
2, 13) and supplying a unique operation clock signal to the data processing module and supplying a clock signal for accessing the memory to the outside in synchronization with the operation of the data processing module operated thereby. And a clock supply means for configuring the data processor.

In order to easily cope with the case where the operating speeds of the plurality of data processing modules are different, the clock supply means is provided for each of the operating speeds of the plurality of data processing modules. A plurality of clock drivers (16c, 16s); a clock selector (25) for selecting an output corresponding to the data processing module to be accessed from the outputs of the respective clock drivers and supplying the selected one to the outside; Can be composed of

To avoid clock signal contention when a plurality of data processors share a memory,
A clock buffer (160) that outputs the clock signal from the clock supply means to the outside and can be selectively controlled to a high output impedance state can be employed.

In order to use a ROM or the like storing parameters for data processing commonly connected to the memory bus, the bus control means has a lower access speed than the memory coupled thereto. Access to another memory such as a ROM is determined from the access address, and the memory cycle is extended as compared with the above memory.

The bus control means receives a command to access the memory from the data processing module and outputs a command for determining an operation mode of the memory as a control signal (143, 144, 1495).
c) can be provided.

The above data processor can be formed on one semiconductor substrate. Further, the data processor is configured to enable address input, data input / output, and control signal input in synchronization with a clock signal and to be coupled to a bus interface unit of the data processor and to a clock supply unit of the data processor. The data processing system can be configured together with the clock generation means.

<< Mode register setting >> Clock signal (C
LK), address input, data input / output and control signal input are possible, and a built-in address counter (2
07) is updated the number of times corresponding to the set value of the mode register (30) by the number of times corresponding to the set value of the mode register (30), and the rewritable memory in which the data can be read and written, and the data and the address for accessing the memory. A data processor (11) for generating and executing image data processing using at least the memory as a frame buffer, and issuing a command for setting the mode register and a register setting value in accordance with the data processing condition;
And a data processing system can be configured.

In this system, the data processor (11) is provided with an external signal (1) for defining a command issue timing for setting the mode register.
35) An input terminal can be provided. Instruction control means (51-57) capable of executing an instruction assigned to issue a command for setting the mode register.
Can be adopted. Furthermore, an address decoder (14) for detecting an internal access to an address assigned to the issuance of a command for setting the mode register.
81), and a sequencer (143) for issuing the mode register setting command according to the detection result of the address decoder and outputting the data to be accessed internally as a set value for the command register to the outside. Can be adopted.

A data processing system which focuses on the point that the throughput of data processing involving memory access can be improved includes a memory ((22)) and a data processor (11) which accesses this memory and performs image data processing. The memory includes a plurality of memory banks (200
A, 200B), enabling address input, data input / output, and control signal input in synchronization with a clock signal (CLK), and accessing while updating a preset address in a built-in address counter (207). An address active command for setting an access address to another memory bank in parallel with the operation of the memory bank operating in the burst mode. A data processing module (12, 13) for generating data and addresses for accessing the memory and performing image data processing using at least the memory as a frame buffer; and a memory bank performing an access operation in a burst mode. Data processing for different memory banks Comprising a said active address issues commands bus control unit for the access address allows pre Ji because setting (14) for the memory bank for instruction accesses from Joules.

<< Processing of Mishit >> A system that performs data processing in a pipeline while reading / writing a plurality of memories in parallel, latches a row address, and stores a row address of the same row address as the once latched row address. The access is continuously made possible by updating the column address, and an address input, a data input / output and a control signal input are made possible in synchronization with a clock signal.
And second memories (82a, 82b), and first and second memories (82a, 82b).
Memory buses (821)
a, 822a, 821b, 822b) and bus control means (74a, 7a) respectively assigned to the memory bus.
4b) generating data and an address for accessing the first and second memories, which are coupled to the respective bus control means, wherein the data and the data read from the first memory are The first and second processing for performing the processing and storing the data processing result in the second memory.
The data processing module (71), which is capable of generating and outputting an access address of the memory in parallel, and the access address for the second memory output from the data processing module corresponds to the time of the data processing. Delay means (73) for transmitting a delay time to the second memory;
1,732). In short, information is exchanged in parallel through the individualized memory bus to each of the first and second memories. For this purpose, the access addresses for both memories are output in parallel by the data processing module, The timing at which both of the access addresses that are temporarily output are input to the corresponding memory is uniquely determined by the delay means.

In this system, in order to prevent disturbance of pipelined data processing, the row address of each access address output in parallel from the data processing module to the first and second memories is determined by the previous A mishit detecting means for detecting whether or not the supplied row address does not match at substantially the same timing; Means for stopping the operation of the data processing module during the address update period. More specifically, a data processing system that focuses on pipeline disturbance prevention realized by reading and writing a plurality of memories in parallel, latches a row address and uses the same as the once latched row address. The first and second memories (82a) are configured such that row address access is continuously made possible by updating a column address, and address input, data input / output, and control signal input are made possible in synchronization with a clock signal. , 82b) and memory buses (821a, 822) individually allocated to the first and second memories.
a, 821b, 822b,) and bus control means (74a, 74b) respectively assigned to the memory bus.
The first and second bus control means are coupled to the respective bus control means.
Generating data and an address for accessing the first memory, performing data processing on the data read from the first memory, and transmitting the data processing result to the second memory.
A data processing module (71), which is capable of generating and outputting access addresses of the first and second memories in parallel for storing in the memory of the first memory and the second memory output from the data processing module. Means for transmitting an access address to the second memory with a delay time corresponding to the data processing time (731, 73)
2) and first mishit detecting means provided for detecting whether a row address output from the data processing module to the first memory does not match a previously supplied row address. (72b) is provided to detect whether a row address output from the data processing module to the second memory does not match the previously supplied row address, and the detection timing is the first. The second mishit detecting means (72) which is substantially simultaneous with the detection timing by the mishit detecting means (72)
a) and means for stopping the operation of the data processing module during the row address update period when the mismatch is detected by one of the first and second mishit detecting means (76) ).

A data processing system which focuses on improving the reliability of processing at the time of a mishit due to a change in a memory access subject latches a row address, and accesses to the same row address as the once latched row address are performed in columns. A memory (18) that is made continuously accessible by updating an address, and that enables address input, data input / output, and control signal input in synchronization with a clock signal
2a) and a plurality of data processing modules (7) for generating data and addresses for accessing the memory.
1, 75), and a mishit detecting means (72a) provided for detecting whether or not the row address output from each of the data processing modules to the memory does not match the previously supplied row address. ), Means (725) for detecting a change in the data processing module accessing the memory, and detection of a mismatch by the mishit detection means and detection of a change in the access subject by the detection means. And a bus control means (74a) for instructing the memory to update the row address.

[0026]

According to the above-mentioned means, since it is necessary to input and output data, addresses and control signals to the memory, for example, the synchronous DRAM, in synchronization with the clock, the same clock as the data processor accessing the synchronous DRAM is used. , A multiplied clock or a divided clock must be supplied. However, when the output of the clock generator is supplied to the data processor and the synchronous DRAM in parallel, the clock skew and internal delay of the processor may cause data, address, control signal setup, hold time, etc. for the clock. Margins cannot be taken. To solve this problem, a synchronous clock signal is supplied from the data processor to the synchronous DRAM. As a result, the clock supplied to the synchronous DRAM and the delay of data, address, and control signal can be matched, and a design with a margin can be realized.

If there is a data processing module operating at a different frequency inside the data processor, the clock of the data processing module to be a bus master is selected inside the data processor, and the synchronous DRAM is selected.
Is adopted to supply the clock to the clock. As a result, the clock supplied to the synchronous DRAM and the delay of the data, address, and control signal can be adjusted in units of the data processing module serving as the bus master, and a design with a margin can be realized.

Synchronous DRAM for external system
Is controlled so that the data terminal, the address, the control signal for the synchronous DRAM of the data processor and the clock terminal to be supplied are set to high impedance. Therefore, when an external system directly accesses the synchronous DRAM, a design having a margin can be realized.

The mode register built in the synchronous DRAM is a register for designating the operation mode of the synchronous DRAM. An optimal mode register can be set by adopting a mode register setting method according to the internal architecture and processing contents of the processor. For example, in straight line drawing in an arbitrary direction, the memory address is a drawing process that is not continuous within the same row address,
The burst length set in the mode register is desirably 1. On the other hand, in the case of a rectangular solid drawing such as a memory clear, a drawing process in which memory addresses are consecutive within the same row address is performed, and the burst length is desirably N (N> 1). Processing for changing the burst length according to the contents of the drawing processing is required. For this reason, in the present invention, processing for dynamically changing the mode register according to various processing contents is performed. The bus throughput of the memory is improved at a low cost according to the burst length.

The conditions under which high-speed transfer is possible are limited to the same row address. When moving to a different row address, it is necessary to issue a precharge command and a row address activation command. For this reason, in the present invention, as a mapping between a physical memory address and a logical coordinate,
For example, different bank addresses are always arranged as addresses adjacent to the same row address in the X direction. When the burst length is set to N (N> 1), it is possible to generate a precharge command and an active command for a bank different from the bank being accessed while data is currently being accessed to the synchronous DRAM. Improve bus throughput. A means for calculating an address in advance and a means for determining row address switching are provided in the drawing processing module, the display processing module, or the bus control unit. When a change in the row address is detected, a precharge command, a row An address activation command is issued, and then a column address is issued. As a result, the speed of the read / write operation is increased.

When the address range used as a line memory in the synchronous DRAM is referred to at a high speed and the result of the image processing is written in the address range used as a page buffer in the synchronous DRAM,
If a mishit occurs independently in reading and writing, the pipeline in the image processing unit is broken, and the processing is not continued. Therefore, if a mishit occurs in both reading and writing, it is regarded that both mishits have occurred, thereby realizing synchronization between memory read and write in the pipeline. For this reason, a write address miss hit detection means capable of detecting the write side miss at substantially the same timing as the read side miss is employed.

Forcibly causing a mishit when the access subject to the memory is changed is the uncertainty of the mishit determination at the time of resuming the operation of the data processing module whose operation has been stopped due to the change of the memory access subject. To improve the reliability of the processing at the time of a mishit.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << Synchronous DRAM >> FIG. 2 is a block diagram showing an example of a synchronous DRAM. Although the synchronous DRAM 22 shown in FIG.
It is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The synchronous DRAM 22 includes a memory array 200A and a memory bank B (BANKA) which constitute a memory bank A (BANKA).
KB). Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column have corresponding word lines (not shown) for each column. , And the data input / output terminals of the memory cells arranged in the same row are connected to corresponding complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with a result of decoding a row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line 204. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201 is provided on the memory array 200B side.
B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. Input buffer 210
And the output terminal of the output buffer 211 are connected to 16-bit data input / output terminals I / O0 to I / O15. Note that a predetermined one bit of the row address signal is a signal for selecting one of the memory banks 200A and 200B.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 receives a refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or its column address in accordance with an operation mode specified by a command described later. A value obtained by sequentially incrementing the signal is output to the column decoders 203A and 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (symbol * means that the signal attached thereto is a row enable signal), column address strobe signal CAS *, row address strobe signal RAS *, write enable signal WE *, etc. External control signal and address input terminal A
And control data from A0 to A9, and forms an internal timing signal for controlling the operation mode of the synchronous DRAM and the operation of the circuit block based on the level of the signal and the timing of the change. A control logic (not shown) for this and a mode register 30 are provided.

The clock signal CLK is synchronous DRA
The master clock is M and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK. The chip select signal CS * indicates the start of a command input cycle by its low level. When the chip select signal CS * is at a high level (chip unselected state), other inputs have no meaning. However, an internal operation such as a memory bank selection state and a burst operation, which will be described later, is not affected by the change to the chip non-selection state. RAS *, CAS * and WE * signals are normal DR
Its function is different from that of the corresponding signal in AM, and it is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
If E is at a high level, the next rising edge of the clock signal CLK is valid, and if it is at a low level, it is invalid. Further, although not shown, an external control signal for controlling output enable for the output buffer 211 in the read mode is also supplied to the controller 30,
When the signal is at a high level, for example, the output buffer 21
1 is set to a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a memory bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at the low level, the memory bank 200A is selected,
When at the high level, the memory bank 200B is selected.
The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. It can be performed by processing such as connection to 211.

The input of A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that the precharge target is both memory banks 200A and 200B. , The low level indicates that one of the memory banks indicated by A9 is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

Next, the main operation modes of the synchronous DRAM specified by the command will be described. (1) Mode register set command (Mo) This command is for setting the mode register 30. The command is designated by CS *, RAS *, CAS *, WE * = low level, and the data to be set (register set) Data) are provided via A0-A9. Although the register set data is not particularly limited,
The burst length, CAS latency, write mode, and the like are set. Although not particularly limited, the burst length that can be set is 1, 2, 4, 8, full page (256).
The configurable CAS latencies are 1, 2, and 3, and the configurable write modes are burst write and single write. The CAS latency specifies how many cycles of the clock signal CLK are spent from the fall of CAS * to the output operation of the output buffer 211 in a read operation specified by a column address read command described later. Until the read data is determined, an internal operation time for reading the data is required, which is set in accordance with the operating frequency of the clock signal CLK. In other words,
When using a high frequency clock signal CLK, CA
The S latency is set to a relatively large value, and the CAS latency is set to a relatively small value when a clock signal CLK having a low frequency is used.

(2) Row address strobe / bank active command (Ac) This is a command for validating a row address strobe instruction and selecting a memory bank by A9.
*, RAS * = low level, CAS *, WE * = high level. At this time, the address supplied to A0 to A8 is taken as a row address signal, and the signal supplied to A9 is taken as a memory bank selection signal. It is.
The fetch operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe. CS *, CAS *,
= Low level, RAS *, WE * = high level. At this time, the addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. Are sequentially selected in accordance with the address signal output from the column address counter 207 and read out continuously. The number of data read continuously is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register 30 as a mode of the write operation, this is a command necessary to start the burst write operation. As a mode, when the single write is set in the mode register 30, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is CS
*, CAS *, WE *, = low level, RAS * = high level, and at this time, the addresses supplied to A0 to A7 are taken in as column address signals. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed by this is performed in the same manner as the burst read operation. However, C for write operation
There is no AS latency, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A8 and A9, and
*, RAS *, WE *, = low level, CAS * = high level.

(6) Auto refresh command This command is a command required to start auto refresh, and includes CS *, RAS *, and CAS.
* = Low level, WE *, CKE = High level.

(7) Burst stop in full page command This is a command required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is used when CAS *, WE * = low level, RAS *, CA
Indicated by S * = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed. CS * = low level, RAS *, CAS *, W
Indicated by E * = high level.

In the synchronous DRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation, and when a row address strobe / bank active command is supplied, the execution is stopped. The operation of the row address system in the other memory bank is enabled without affecting the operation in one of the memory banks. For example, a synchronous DRAM has a means for internally holding data, an address, and a control signal supplied from the outside.
Particularly, the address and control signal are not particularly limited, but are held for each memory bank. Alternatively, data of one word line in a memory block selected by a row address strobe / bank active command cycle may be latched in advance by a latch circuit (not shown) for reading before a column-related operation. I have. Therefore, data input / output terminals I / O0-I /
Unless data collision occurs in O15, during execution of a command whose processing has not been completed, a precharge command and a row address strobe / bank active command for a memory bank different from the memory bank to be processed by the command being executed are issued. It can be issued to start the internal operation in advance.

As described above, since the synchronous DRAM 22 can input and output data, addresses, and control signals in synchronization with the clock signal CLK, a large-capacity memory similar to a DRAM can be operated at a high speed comparable to an SRAM. Also, by specifying how many data to access to the selected one word line by the burst length, the built-in column address counter 207 is designated.
It can be understood that a plurality of data can be continuously read or written by sequentially switching the selection state of the column system.

<< Drawing / Display Processing Processor >> FIG. 1 is a block diagram showing a drawing / display processing processor 11 according to an embodiment of the present invention and an image processing system to which the drawing / display processing processor 11 is applied.
The image processing system shown in FIG. 1 includes a CPU (central processing unit) 15 that controls the entire system, a system memory 151 used as a work area for the CPU 15 and a temporary storage area for data, and a drawing display processor (data processor). 11, the synchronous D whose access is controlled by the clock generation unit 18 and the drawing / display processing processor 11.
It comprises a RAM 22 and a monitor 20 that is display-controlled by the drawing display processor 11.

Although not particularly limited, in the system of FIG. 1, the SDARM 22 is a storage area for commands and parameters for the drawing processing module 12 and the display processing module 13. Although they are not particularly limited, they are transferred from the CPU 15 in advance. Further synchronous DR
The AM 22 is also used as a frame buffer or a temporary data storage area or a work area for drawing processing.

The drawing processing module 12 in the drawing display processor 11 includes a synchronous DRAM 22
From the synchronous DRA according to the instruction of the command.
A drawing process is executed in M22. The display processing module 13 in the drawing display processing processor 11 has an internal horizontal
The vertical address counter is updated in accordance with the horizontal and vertical synchronization timings of the monitor 20, necessary display data is read out from the synchronous DRAM 22 via the bus control unit 14, and output in accordance with the display speed of the monitor 20, that is, the dot rate. . The monitor 20 displays the display data output from the display processing module 13 in synchronization with vertical and horizontal synchronization signals.

The clock driver 16 includes the clock generator 1
8 receives the basic clock 181 and supplies it to the drawing processing module 12, the display processing module 13, and the bus control unit 14, and also supplies a clock signal to the external synchronous DRAM 22. The clock signal supplied from the clock driver 16 to the synchronous DRAM 22 is the clock signal CLK described in FIG.

The rendering / display processor 11 of this embodiment, in terms of controlling access to the synchronous DRAM 22, includes (1) clock supply, (2) mode register setting, (3) data access pipeline, and (4)
It is configured in consideration of measures such as bus contention from a plurality of modules. Next, each content will be described sequentially.

<< Clock supply to synchronous DRAM >>
When accessing the synchronous DRAM 22 operated in synchronization with K, data and data are supplied to the synchronous DRAM 22 at a timing synchronized with the clock signal CLK.
It is necessary to input and output an address and a control signal. Therefore, the same clock, multiplied clock, or frequency-divided clock as that of the graphic display processor 11 that controls access to the synchronous DRAM 22 is used for the synchronous DRAM 22.
22. At this time, the crystal oscillator 1
When the clock signal 181 generated by the clock generator 18 using an oscillator such as 7 is supplied in parallel to the drawing display processor 11 and the synchronous DRAM 22 on the mounting board, the load and delay component of the clock wiring If the clock skew occurs due to the deviation of the clock or an operation delay occurs inside the processor 11, required operation margins such as data, address and control signal setup and hold time are guaranteed for the clock signal cycle. It may not be possible. To solve this problem, the rendering display processor 11, which mainly accesses the synchronous DRAM 22, uses the synchronous
A configuration for supplying a clock signal to the RAM 22 is employed. For this reason, the delay of the clock signal CLK to be supplied to the synchronous DRAM 22 and the data, address, and control signal can be matched at the design stage of the drawing / display processing processor. Compared with this, the cost is low and a sufficient margin can be easily secured.

As typically shown in FIG. 21,
When there are modules operating at different frequencies inside the drawing / display processing processor 11c, for example, the drawing processing module 12c and the display processing module 13c, the clock signals of the modules 12c and 13c which are respectively bus masters are separated and sent to the synchronous DRAM 22. The bus control unit 14c of the drawing display processor 11c also controls the clock signal of the clock selector 2 according to the access subject.
5 and the operation of the access subject and the synchronous DRA
The operation of M22 can be configured to be completely synchronized as described above. For this reason, the delay of the clock signal supplied to the synchronous DRAM 22 and the data, address, and control signal can be adjusted in units of the module that becomes the bus master, and in such a case, a sufficient operation margin can be easily secured. become.

The structure of FIG. 21 will be further described. Clock generators 18c and 18s of a plurality of frequencies, clock drivers 16c and 16s, a plurality of modules 12c and 13c operating according to the frequencies, and a plurality of A bus controller 14c for arbitrating module access to the memory; and a clock selector 25 for selecting a clock to the memory in accordance with an arbitration signal 251.
1 shows an image processing system configuration for directly supplying clocks CLK of a plurality of frequencies from one. The CPU interface is not shown in FIG. For example, when a certain display is repeatedly performed, the rendering display processor 11c is operated stand-alone and does not require a CPU interface. Naturally, it is also possible to provide a CPU interface as in FIG.

The configuration shown in FIG.
The difference from the configuration of FIG. 21 is that the clock selector 25d for the AM 22 is arranged outside the drawing display processor 11d. That is, the clock generators 18d, 1
From 8t, a clock signal is supplied to the clock selector 25d via a different system from the clock signal supplied to the drawing display processor 11d, and the synchronous DR
The bus control unit 14d according to whether the access subject of the AM 22 is the drawing processing module 12d or the display processing module 13d
Causes the clock selector 25d to select the output clock signal frequency. The control signal therefor is shown as 252. 16d and 16t are clock drivers, 25t
Is a clock selector.

Note that, as shown in FIG.
Even when the module inside 1i is a single module 13i (display processing module), a configuration in which the clock signal CLK is supplied from the processor 11i to the synchronous DRAM 22 is applicable. In FIG. 22, 14i is a bus control unit, 16i is a clock driver, and 18i is a clock generation unit. Further, as shown in FIG. 24, a processor having a built-in clock selector 25k for selecting clock signals of a plurality of frequencies in a single module (display processing module) 13k is also used.
k can directly supply a clock signal to the synchronous DRAM 22. Reference numerals 18k and 18L denote a clock generator, 16k a clock driver, and 14k a bus controller.

<< Countermeasures for Bus Contention from Plurality of Modules >> FIG.
An example system in which 1-1 and 11-2 share the synchronous DRAM 22 is shown. In this system, the output of the clock driver 16 incorporated in each of the drawing / display processing processors for supplying the clock signal CLK to the synchronous DRAM 22 is supplied to the clock buffer 1.
60 are wired-OR coupled through synchronous D
It is coupled to the clock input terminal of the RAM 22. At this time, one of the drawing / display processors is operated by the synchronous DRAM 22 for the other of the drawing / display processors.
In this case, the terminal for supplying the clock signal CLK as well as the data, address, and control signals for the synchronous DRAM 22 is controlled to have a high impedance. According to the present embodiment, the output of the clock driver 16, that is, the clock buffer 160 is controlled to a high impedance state. Thereby, even when another drawing / display processing processor directly accesses the synchronous DRAM 22, the other drawing / display processing processor similarly secures a sufficient operation margin, in other words, the other drawing / display processing processor. Access to the synchronous DRAM 22 can be controlled in accordance with the operating speed of the synchronous DRAM 22.

FIGS. 18 and 19 show an example of a circuit for coping with bus contention from a plurality of modules. In the example shown in FIG. 18, a three-state control bit 149 is provided in an internal register of the drawing processor 11, and its value is set by, for example, the CPU 15. The output 1491 of the three-state control bit 149
Bus buffers 1495A and 1495 for addresses, data, and control signals in the bus control unit 14.
D, 1495C and the clock terminal are made high impedance. The high impedance of the clock terminal is realized by the clock driver 160. In the example shown in FIG. 19, bus buffers 1495a, 1495D, and 1495C for addresses, data, and control signals and a clock driver depend on the level or change timing of a control signal 105 supplied from an external terminal of the rendering display processor 11. 16 clock terminals (clock buffer 16
0 output terminal) is made high impedance.

<< Setting of mode register >> Synchronous D
The mode register 30 incorporated in the RAM 22 is a register for designating the operation mode of the synchronous DRAM 22. The existing standard memory does not have a register for designating the static operation mode like the mode register 30, and the corresponding access entity issues a special command in addition to the memory read, write and refresh access cycles. There was no need. In the present invention, the rendering display processor 11 sets the mode register 30 according to its internal architecture and processing contents. As a mode register setting method, various methods described below can be appropriately adopted.

FIG. 3 is a block diagram showing an example of the bus control unit 14. The arbiter 141 includes each module 12,
A bus request signal 1411 to the synchronous DRAM 22 which is output from the module as a command execution result at 13 is received, bus arbitration is performed, and one module is permitted to operate by a bus acknowledge signal 1412. At the same time, the selector 142 is supplied with the module select signal 1413. Selector 142
Selects the control information 1421 from each module according to the select signal 1413 and supplies it to the sequencer 143. Control information 1 for synchronous DRAM 22
Reference numeral 421 is a control code for instructing, for example, data reading, data writing, refreshing, setting of the mode register 30, and the like. This control code is output as a result of executing the command fetched from the outside by the module. The mishit detector 147 compares the row address of the address bus 148 with the currently active row address and provides the mishit information 1471 to the sequencer 143. The sequencer 143 includes the control information 1421 and the mishit information 14
A series of information for executing the bus control process specified by the control information 1421 is given to the decoder 144 based on the state transition diagram of FIG. The decoder 144 decodes various kinds of information given from the sequencer 143, and outputs a command 14 to the synchronous DRAM 22.
41, a control signal 1442 for the bus buffer 1495D, a control signal 1443 for the arbiter 141, and the like. When the command 1441 issued to the synchronous DRAM 22 is a command for setting the mode register 30 (mode register set command Mo), the value to be set in the mode register 30 is not particularly limited. The signal is selected and output according to the output 1445 of the decoder 144. Since the command register value of the synchronous DRAM 22 is supplied via the address bus, the control signal 1 output from the decoder 144 at that time is output.
At 444, the address selector 145 sets the literal generation unit 1
Select the output of command register 3
The value set to 0 is supplied from the bus buffer 1495A to the synchronous DRAM 22 via the address bus.
Note that the literal generation unit 146 outputs the output 14 of the decoder 144.
45, a logic circuit or a storage circuit that outputs a predetermined value.

The timing of issuing the mode register set command Mo can be synchronized with an external signal. For example, as shown in FIG. 26, display blanking information 135 is input from an external terminal. For example, the display blanking information is a vertical blanking period in a vertical synchronizing signal. At this timing, the display processing module 13 sends a mode register set command to the bus control unit 14 in order to fetch the next display data from the synchronous DRAM 22. , For example, to change the burst length.

The set value for the mode register 30 can be included in the command itself or the parameters of the command. Such a command is one of the commands executed by the various drawing processing modules 12 and the display processing module 13 described above. FIG. 27 schematically shows a command execution flow by such a processing module. That is, a command fetch (M1) is performed,
The command is interpreted (M2), and it is determined whether the result of the interpretation is a setting command of the mode register 30 (M2).
3) If the command is a mode register set command, the command is executed (M1), and for other commands, the processing specified by the command is executed (M1).
4) Then, the next command fetch is performed (M6)
The same processing as described above is repeated. M5 in the figure is a step equivalent to M1 in the next command fetch cycle. FIG. 28 shows a format example of such various commands. FIG. 28A shows a case where one command has a command format including a command designation field COMC and an attribute code field COMD. In this case, the set value of the mode register 30 in the mode register set command is stored in the attribute code field COMD. Be placed. FIG. 28B shows a format in which one command is composed of a command designation field COMC, and the following parameter PAR includes various attributes. In this case, the set value of the mode register 30 in the mode register set command is the parameter PA.
R.

The configuration shown in FIG.
9 is a configuration example of a bus control unit when a set value for 0 is attached to a command to be executed by the modules 12 and 13. The difference is that the value of the data bus is connected to one input of the address selector 145 instead of the literal generator 146 of FIG. It should be understood that the selection control of the address selector 145 is the same as in the case of FIG. Address selector 14
5, the data bus can be selected as an input to the synchronous DRAM 22, so that the set value of the mode register 30 to be supplied to the address input terminal of the synchronous DRAM 22 can be directly input from the internal data bus to which the drawing processing module 12 and the display processing module are coupled. Can be specified. For example, when the drawing processing module 12 or the display processing module 13 recognizes the setting processing of the mode register 30 by a command of a command format as shown in FIG. 28, it supplies control information 1421 for the processing to the bus control unit 14, The set value of the mode register 30 is output to the internal data bus. As a result, the setting of the mode register for the synchronous DRAM 22 is performed.

The setting processing of the mode register 30 is performed according to I
It can also be realized by the / O mapping technique. In the case of FIG. 30 showing one example, a specific register 1482 is mapped to an internal I / O space accessible by the drawing processing module 12 and the display processing module 13. That is, the address decoder 1481 detects the access of the register 1482 from the internal address bus information, and notifies the register 1482 and the sequencer 143 with the control signal 1483. This allows register 14
82 latches the mode register setting value supplied to the data bus at that time, and the sequencer 143 recognizes the notification as an instruction for setting the command register. The sequencer 143 issues a mode register set command to the synchronous DRAM 22 via the bus buffer 1495C, and causes the address selector 145 to select the set value latched in the register 1482, thereby causing the synchronous DRAM 2 to be selected from the bus buffer 1495A.
Feed to 2. Although not specifically shown, in the I / O mapping method, a physical register can be omitted, and only the specific address can be secured and the decoder 1481 can detect access to the address.

FIG. 31 is a block diagram of a control system when the built-in module 13 such as a display processing module uses microprogram control. Macro RO
M51 describes a predetermined microprogram.
The micro address register 56 holds the access address corresponding to the instruction. The micro instruction read from the micro ROM 51 is stored in the macro instruction register 52. Is supplied to the execution unit 58. The microinstruction includes next address information, which is supplied to the microaddress controller 55 to sequentially update the value of the microaddress register 56. The head micro address of the micro instruction sequence is given by the command fetched into the micro register 57. The fetched command basically determines the operation of the drawing processing module 12 and the display processing module 13. The micro address controller 55 also controls the micro address for the micro branch. For example, when a command for setting the mode register 30 is fetched into the micro register 57, the micro instruction typically shown as the memory control information 53 is latched in the micro instruction register 52. By decoding this microinstruction, for example, as shown in FIGS.
9 and a control operation for setting the mode register 30 in the mode of FIG. 30 is started.

<< Dynamic setting of mode register >>
The rendering display processor 11 of the present embodiment can dynamically set the mode register 30 which can be set by the above-described various methods according to the processing content. For example, in a straight line drawing in an arbitrary direction, a memory address is a drawing process that is not continuous within the same row address, and the burst length set in the mode register 30 is desirably 1.
On the other hand, in the case of rectangular solid drawing such as memory clear, a memory address is a continuous drawing process within the same row address, and the burst length is desirably N (N> 1). Is required. Therefore, in the present invention, the process of dynamically changing the mode register 30 according to various processing contents is performed, so that the bus throughput of the synchronous DRAM 22 can be improved at low cost in accordance with the burst length. I have.

FIG. 4 shows a state transition of the sequencer 143 of the bus control unit 14 in FIG. When the power is turned on, a precharge S3, a mode register setting S7, and a NOP (non-operation) S2 are executed from the idle S1 to initialize the synchronous DRAM 22.
In addition, the refresh sequence S8 is repeated twice as a dummy cycle. The refresh process is performed from the idle S1 to the precharge S3, the refresh S8,
It is configured by the processing of NOPS2. Data reading when the burst length is 1 as in straight line drawing is as follows.
The processing is performed by the idle S1 to the precharge S3, the row address activation (instructed by a row address strobe / bank active command) S4, and the reading (indicated by a column address / read command) S6. If the same row address follows, the data read is executed one after another by continuously issuing the read S6 (burst read operation). Data is written from idle S1 to precharge S3, row address activation S
4. Write (instructed by a column address / write command) S5. Subsequently, if the row address is the same, the data write is executed one after another by continuously issuing the write S5 (burst write operation). If the row address changes during continuous reading or continuous writing, NOPS2, precharge S
3. Reading and writing are performed again through the state of row address activation S4. When the CAS latency is 1, the read-modify-write operation returns from the above-mentioned read S6 to N
The OPS2 and the write S5 can be executed as one cycle. When a bus request is issued from the display processing module 13 to the arbiter 141, when the bus acknowledgment 1421 is returned, the display processing module 13 provides control information for setting the mode register 30 to the sequencer 143, and thereby the precharge S3, Mode register setting (instructed by mode register set command) S7, NOPS2 is executed, and burst length becomes 8
Is set to Thereafter, a read S6 is issued every eight words. During that period, the precharge S3 and the next adjacent row address activation S4, which are obtained in advance, can be executed for the bank that is not currently accessed. The display processing module 13 gives a setting instruction of the mode register 30 to the sequencer 143 at a point of time when necessary display data is read out.
3. The mode register setting S7 and NOPS2 are executed, and the burst length is set to 1. Thereafter, the bus request signal is negated and the bus is released.

FIGS. 5 to 13 show synchronous DRAMs.
An example of an access timing in a display / drawing cycle for the display 22 is shown. Here, the read data is output to the data bus after a predetermined clock elapses (latency). This latency is variable and is set in the mode register 30 of the synchronous DRAM 22.
In the examples of FIGS. 5 to 13, the latency is all set to 1, but is not particularly limited.

FIG. 5 shows an example of one-dot read-modify-write in the drawing process. This example is a case of drawing one dot at a time for random pixels. At T1, the burst length is set to 1 in the mode register 30 (Mo). At T3, the drawing processing module 12 issues control information 1421 for one-dot read-modify-write. Mishit detection unit 1
47 detects that the access address at that time is not at the same position as the previous row address. Accordingly, the sequencer 143 operates the precharge S3 (Pr-a of T3).
b), row address activation S4 (Ac-a of T4), read S6 (Re-a of T5), NOPS2 (No of T6)
p), the command for the write S5 (Wr-a of T7) is synchronized with the clock signal CLK to synchronize with the synchronous DRA.
M22. Since the CAS latency at the time of reading is 1, data is read at T6, and data writing is performed at T7. Subsequent one-dot drawing is performed in the memory bank B. At T8, control information 1421 for that is issued, and the precharge S3 (T8
Pr-b), row address activation S4 (Ac-
b), reading S6 (Re-b of T10), NOPS2
(No in T11), write S5 (Wr− in T12)
Each command for b) is supplied to the synchronous DRAM 22 in synchronization with the clock signal CLK.

FIGS. 6 and 7 show the display processing module 13.
6 is a timing chart showing an interrupt process from the server. In the figure, the synchronous DRAM 22 reads one dot for a random column address until T10.
One dot write is performed and the object is drawn. At this time, it is assumed that there is a bus request interrupt from the display processing module 13. FIG. 7 shows an example in which 16 words are collectively read as display data in response to such a bus request. When there is a bus request from the display processing module 13, the arbiter 141 performs bus arbitration and releases the bus to the display processing module 13. The display processing module 13 performs control information 142 for reading such 16 words.
1 is supplied to the sequencer 143. As a result, the burst length of the mode register 30 is set to 8 (T
11 Mo). The read command is issued every eight words (Re-a of T15, Re-b of T23). T1
5 before the read command is issued, the precharge S3 (T1
3 (Pr-ab) and a row address (row address) activation S4 (Ac-a of T14) are issued to the synchronous DRAM 22. Reading of the first one word is started in synchronization with T16. During that period, precharge S3 is performed on the bank that is not currently accessed.
(Pr-b of T21), a command of the next adjacent row address activation S4 (Ac-b of T22), which is obtained in advance, is issued to the synchronous DRAM 22, and the processing is performed in advance in the memory bank B (b). ) Side. Thus, data processing can be pipelined, and the bus throughput can be improved. In other words,
Data can be read without interruption even at the switching of the memory bank to be accessed. When the display processing module 13 reads out the necessary display data,
The setting instruction of the mode register 30 is given, and the precharge S
3 (Pr-ab of T32), mode register setting S7
(Mo of T33), NOPS2 (Nop of T34) is executed to set the burst length to 1, then the bus request signal is negated and the bus is released.

FIGS. 8 and 9 show an example of a burst read operation of display data. In order to shorten the ratio of the display access cycle of the synchronous DRAM 22, it is preferable to continuously read out as much display data as possible. Therefore, it is desirable to set the burst length to a full page and read continuously. . However, the display processing module 13 requires a FIFO or a RAM for temporarily storing display data read in advance, and the number of words to be continuously read is determined according to the relationship with the storage capacity of such a FIFO or the like. Although not particularly limited, the burst stop command (Stop) can control the generation timing based on the coincidence of the comparison result between the counter output value of the number of words to be read in the display processing module 13 and the number of data words to be read. In FIG. 8, the command register 30 is set so that the full length is set to the full length at T1 (Mo), and the precharge (Pr-) is set at T3.
ab), row address activation at T4 (Ac-a), T5
, Each command of read (Re-a) is issued, and T6
, Data is sequentially read out.

FIGS. 10 and 11 show B in the drawing process.
An example of itBLT (bit block transfer) is shown. Also in this case, the burst length is set to a full page, and reading and writing are continuously performed. The access addresses at this time are the same row address. According to this example, the read and write data numbers are each set to 12, and the burst read and burst write are terminated by the burst stop command (T17, T30 Stop). The display processing module 13 is BitBLT
Has means for accumulating therein the read data which is the transfer source data in.

FIGS. 12 and 13 show an operation example in the case where the display processing module 13 has no means for temporarily accumulating the display data from the synchronous DRAM 22. At this time, a method of interleaving the display processing and the drawing processing is adopted. In this case, it is necessary to read out the display data at a cycle determined in accordance with the dot rate.
An example of the times is shown. In order to enable reading once every four cycles of the clock signal CLK, the memory banks of the display area and the drawing area are divided, and the memory bank of the display area and the drawing area are switched at the timing of switching the frame of the monitor 20. Further, at the timing when the display row address is switched, the precharge S3 and the next row address activation S4 are executed prior to the drawing process. 12 and 13, the memory mat A (a) is a display area, and the memory mat B (b) is a drawing area. The precharge for the memory ttA (a) is T3 (Pr
-Ab), and a row address is specified at T4 (Ac-a). The read operation for display shown in FIG. 11 is performed for the same row address specified by T4. At this time, in the drawing for the memory bank B (b), the row addresses selected in T14 (Pr-b) and T15 (Ac-b) are T24 (Pr-b) and T26 (Ac
-Changed in b) and done randomly.

FIG. 14 shows an embodiment of a drawing processing method of BitBLT (bit block transfer). Although not particularly limited, the drawing processing module 12 includes a block for calculating the number of words to be transferred for addresses and data according to a drawing algorithm, a block for performing one-dot color calculation, and the like. The drawing process of BitBLT (bit block transfer) can be realized by repeating the operation for one line in the X direction in the Y direction. In the operation for one line in the X direction, first, the address counter 121 is reset, and the number of transfer words of the transfer source is stored in the transfer word number register 12.
Set to 2. The burst length is set to a full page, the drawing processing module 12 outputs a transfer source start address to the bus control unit 14, and starts continuous reading. The address counter 121 is incremented by an acknowledgment signal 1412 from the bus control unit 14, and temporarily stores transfer source data in the source RAM 124. The value of the address counter 121 and the value of the transfer word number register 122 are compared by the comparator 123.
Issues burst stop control information. BitBLT
When the calculation with the base data is required in the drawing process of (bit block transfer), the base data is temporarily stored in the destination RAM 126 in advance like the transfer source data. Finally, the transfer source data is aligned by the shifter 125, and this is operated with the base data by the arithmetic unit 127, and the operation result data is continuously written to the synchronous DRAM 22 again.

<< Switching to ROM Access >> As shown in FIGS. 20 and 25, the bus control unit 14a can be configured to be able to access the ROM 26 as a slower memory together with the synchronous DRAM 22. According to FIG. 20, the ROM 26 is connected to the same bus as the synchronous DRAM 22. The address space of the ROM 26 is mapped to the frame buffer address space,
In other words, the rendering display processor 11 has an address decoder that generates a signal for selecting the address decoder.
When the drawing processing module 12a has the address decoder, access to the address space of the ROM 26 is as follows.
The bus control unit 14 is notified by the control information 1421.
The sequencer 143 reads from the idle S1 and executes S6, and executes NOP until the data from the ROM 26 is determined.
Execute S2. The number of times NOPS2 is executed
Can be fixed to a value determined in advance according to the operating speed of the ROM 26, but it is desirable that the value can be designated to a dedicated register in the sense that the range of choice of the applicable ROM 26 can be expanded. When an address decoder is arranged in the bus control unit 14 like the address decoder 1481 in FIG. 30, the output of the decoder is directly input to the sequencer 143, and the access of the ROM 26 is controlled. At this time, the number of insertions of NOPS2 can also be specified by the dedicated register.

The example of FIG. 25 differs from the example of FIG. 20 in that the connection between the modules 12 and 13 and the bus control unit 14 uses a dedicated bus. Even in the embodiment having no ROM 26, such connection by the dedicated bus can be adopted.

<< Pipelining of Data Access >> By using the synchronous DRAM 22, it is not always possible to realize high-speed transfer comparable to the conventional SRAM. That is, the conditions under which high-speed transfer is possible are limited to the same row address, and when moving to a different row address (mis-hit), a precharge command, a row address activation command (row address strobe / bank active command) ) Is required. Therefore, as a mapping of the physical memory address to the logical pixel coordinates of the frame buffer, for example, another row address mapped to another area adjacent to the area of the same row address is always a row address of a different memory bank. Such an arrangement is adopted. As a result, when the burst length is set to N (N> 1), as is clear from the description of the timing charts of FIGS.
It is possible to issue a precharge command and a row address strobe / bank active command to a memory bank different from the currently accessed memory bank while data is currently being accessed to M22, thereby improving the bus throughput. . A means for calculating an address in advance in the drawing processing module 12, the display processing module 13, or the bus control unit 14 and a means for determining switching of a row address (mishit detection unit 147)
When a change in the row address is detected, the sequencer 143 in the bus control unit 14 issues a precharge command and a row address activation command, and subsequently issues a column address. . This allows, for example, reading data up to every 10 nanoseconds,
And writing is also possible.

FIGS. 15 to 17 show examples of mapping between physical memory addresses of the synchronous DRAM 22 and logical coordinates (mapping on a display frame) in the system of this embodiment. In other words, the data arrangement for each row address of the synchronous DARM 22 in the bitmap coordinate area of the frame buffer is shown. In this embodiment, the same row address in the synchronous DRAM 22 corresponds to pixel data of 256 dots. In each figure, vertical x horizontal = 16 dots x
An area of 16 dots, an area of vertical × horizontal = 1 dot × 256 dots is an area of pixel data corresponding to one row address. FIG. 15 shows 16 dots × 16 having the same row address.
The rectangular areas of the dots are mapped such that the memory banks are different from those adjacent in the horizontal direction in the figure. In FIG. 16, rectangular areas of 1 dot × 256 dots are mapped such that memory banks are different from each other in the vertical direction in the figure. FIG. 17 shows 16 dots × 16 having the same row address.
A rectangular area of dots is mapped so that adjacent ones in both the vertical and horizontal directions in the figure have different memory banks.
The mapping in FIG. 15 allows the memory banks to be accessed to be alternately switched even in the drawing processing that proceeds in the horizontal and diagonal directions on the bitmap coordinates. The processing throughput such as pre-charging can be performed in advance for the memory banks. The mapping in FIG. 17 assumes an optimum mapping particularly when access to the frame buffer is concentrated in the vertical and horizontal directions. In the mapping of FIG. 16, the memory banks to be accessed are alternately switched in the process in which the drawing or display is advanced in the horizontal direction on the bitmap coordinates. On the other hand, processing such as precharge can be performed in advance to improve processing throughput. The mapping in FIG. 16 is a case where the scan address is changed in one direction and there is no inconvenience such as clearing a rectangular area.

For example, in the mapping of FIGS. 15 and 17, when memory access is performed in the horizontal direction of the frame buffer arrangement, the access mode at the boundary between memory banks A and B is the access mode at T24 in FIG. You. In FIG. 16, the mode of memory access for 256 dots in the horizontal direction corresponds to the access timing in FIGS.

<< Prevention of Pipeline Disturbance Due to Mishit Processing >> Mishit processing for further improving the throughput of data processing performed by accessing a synchronous DRAM will be described with reference to another embodiment. In the following description of the embodiment, a data processor according to another embodiment of the present invention and a facsimile image processing system to which the data processor is applied will be described as an example.

FIG. 33 is a block diagram showing an example of an image processing system having a data processor 70 according to another embodiment of the present invention. In the figure, a sensor 80 reads optical density information of a document, photoelectrically converts this, and outputs image data. Sensor 80 is C in current facsimile
Although a CD line sensor is often used, a contact sensor has begun to be used, and an area sensor and the like will be applied in the future. The image processing section 71 removes distortion included in the image data, improves the image quality, and further performs encoding and the like. In this embodiment, two synchronous DRAMs 82a,
82b are provided. These are stored as a line memory for reading and writing data at high speed in order to calculate a target pixel and peripheral pixels, and for transmitting image-processed and encoded data via the communication processing unit 79. It is used as a code page buffer. 2
The synchronous DRAMs 82a and 82b are interfaced with their own bus controllers 74a and 74b, respectively.
It is accessible in parallel. The CPU 75 controls the entire system, stores image-processed and encoded data in the page buffer areas of the synchronous DRAMs 82a and 82b, and controls transmission via the communication processing unit 79. The communication processing unit 79 executes a connection with a facsimile on the receiving side, a communication protocol procedure, and a CPU.
A conversion for transmitting the data from the communication line 75 through a communication path is performed. The clock generator 78 generates a basic clock 781 based on the reference frequency of the crystal oscillator 77,
It is supplied to the CPU 75 and the communication processing unit 79. At the time of reception, the communication processing unit 79, the CPU 75, and the image processing unit 71 follow the reverse of the transmission, and are recorded by the recording unit 81. As the recording unit 81, a thermal head, a laser printer using an ink jet, an electrophotographic technique, or the like has been put to practical use.

The synchronous DRAMs 82a and 82b are
Compared to the conventional DRAM, data, address, and control signals can be input / output in synchronization with the clock.
This is a memory that can realize a high-speed transfer comparable to that of the conventional DRAM and can realize a larger capacity than a conventional DRAM at a low price. That is, by using the synchronous DRAM, the bus speed of the memory can be improved, and the image processing SRAM can be used.
And the page buffer DRAM can be integrated.
Here, the synchronous DRAMs 82a and 82b correspond to FIG.
It should be understood that the circuit configuration has the same circuit configuration as that described in the above. Then, the synchronous DRAMs 82a and 82
The clock signal CLK for b is also output from the data processor 70 as in the above embodiment.

In FIG. 33, the image processing unit 71 includes the sensor 8
The image data read from 0 is subjected to distortion correction processing, image quality improvement processing, encoding processing, and the like. These processes are performed using the read address RD ADR and the bus control unit 74.
a, the synchronous DRAM 82a performs a read operation to output data 821a, and the data 751a obtained by the data 821a is taken in by the image processing unit 71.
Is realized by performing image processing on the fetched data 751a and writing data 751b after the image processing to the synchronous DRAM 82b using the write address WRADR.

Here, the synchronous DRAM 82a
Data is read out from the memory and processed by the image processing unit 71 such as correction, and the result is stored in the synchronous DRAM 82.
The process of writing to b is repeatedly performed on the entire display data and sequentially in synchronization with the operation clock of the image processing unit 71 with a plurality of processing steps as one unit. The pipeline of image processing is such that a plurality of such unit image processes consisting of a plurality of processing steps are performed in parallel while shifting each of the processing steps. It is a processing method that is performed. According to the present embodiment, the image processing unit 71
Outputs in parallel a read address RD ADR for certain data and a write address WRADR of data obtained by subjecting the read data to data processing. At this time, the data processing time from the time when the read data is subjected to the data processing to the time when the read data becomes writable is secured by the address transmission delay time by the two-stage latches 731 and 732 in FIG. Therefore, read address RDA
When the DR and the write address WRADR are output in parallel from the image processing unit 71, the read address RDAD
The data read by R is data-processed and written because the write address WRADR is
This is performed by the address signal WRADR3 which is made valid after waiting for the delay time passing through the lines 31 and 732.

When the configuration of the image processing unit 71 is set to enable pipeline processing, the clock is partially stopped if the time from the reading of the read data to the writing of the processed data is not constant. The waiting requires complicated processing in terms of timing. For example, when realizing an image processing pipeline by continuously reading data from the synchronous DRAM 82a and continuously writing the result of data processing to the synchronous DRAM 82b, reading or writing to or from the synchronous DRAM 82a is performed. If a mishit occurs in any of the above cases, the pipeline collapses and partial data corruption occurs. For this reason, when a mishit occurs, it is necessary to temporarily stop the image processing operation and hold the data by stopping the data in the pipeline. Further, since it is necessary to stop whether a mishit occurs on either the read side or the write side, the write side and the read side perform the miss hit determination at the same time. According to the present embodiment, a read address is issued to the synchronous DRAM 82a to read data,
On the other hand, in a series of processing in which data processing is performed, a write address is issued to the synchronous DRAM 82b, and the data is written into the synchronous DRAM 82b, the write row address of the write row address is not written until the last stage of data write is performed. If a mishit is found, then the data for the next data processing is read out one after another from the synchronous DRAM 82a at that time. If the write mishit processing is inserted at that stage, the pipeline is disturbed, and Restoration requires complicated processing.

Therefore, in the embodiment of FIG. 33, a mishit is detected for the read address RD ADR and the write address WRADR output from the image processing section 71. The mishit detector 72b for the read address RD ADR is arranged in the bus control unit 74a, whereas the mishit detector 72a for the write address WRADR is arranged in a stage preceding the latch circuit 731 and the write address WRA
Whether or not DR3 misses is determined by the read address R
The detection is performed at the time when the DADR is issued. That is, the write address WRADR is set as the internal address WRADR3 via the mishit detector 72a and the latches 731 and 732, and is connected to the bus controller 74b. The latches 731 and 732 store the read address R
Process and process the data read by DADR,
The processing delay time until write data is created is guaranteed. The bus controllers 74a and 74b are connected to the synchronous DRAMs 82a and 82b via independent address buses, data buses, and control buses. Basically, the bus control units 74a and 74b operate independently, but in the present embodiment, the mishit information generated at the write address is reflected in advance by referring to the mishit process of the read address. In other words,
A state of a miss at the write address WRADR3 is detected at the write address WRADR at the time of issuing the read address RD ADR, and a miss at the write address WRADR3 is detected at the read address RD.
Treat the ADR as if it were a miss. According to this embodiment, the mishit signal WRMHT detected by the mishit detector 72a is supplied to the bus control unit 74a, and the bus control unit 74a that receives the milit signal WRMHT supplies the mishit signal RDMHT to the clock driver 76 to perform image processing. The supply of the clock signal 760 to the unit 71 is stopped for a certain period. The suspension period is a processing period for precharging the synchronous DRAM and activating the row address in response to the mishit. When a mishit is detected by the read address RD ADR, the mishit signal RDMTH is directly output.
Is supplied to the clock driver 76 and operates similarly. By synchronizing such mishits, processing of invalid data due to mishits can be unified, and the pipeline of image processing can be simplified. That is, disturbance of the pipeline for image processing can be prevented as much as possible. Although all clock signals 760 from the clock driver 76 to the image processing unit 71 are illustrated here for simplicity, the present invention may be limited to those related to holding the pipeline of the image processing unit 71, Alternatively, if the clock system uses a non-overlapping multi-phase clock, the operation may be stopped in any one of the phases.

FIG. 35 is a timing chart showing an example of the operation of the system shown in FIG. 33 when a miss occurs during reading in the course of pipeline processing. Read address RDAD issued at T1 from image processing section 71
R is sent to the bus control unit 74a, and at T2, the bus control unit 74a checks the status R of the sequencer included in the bus control unit 74a.
Change DBST to first data read R1. As a result, the data DR1 is output from the synchronous DRAM 82a at T3. The data DR1 is stored in the image processing unit 71.
Is processed into write data DW1. The write address WRADR is delayed by the latch circuits 731 and 732 as delay means to become the internal write address WRADR3, and at T4, the status WRBST of the sequencer of the bus control unit 74b is changed to the first data write W1, and the data DW1 Is synchronous DR
The data is written to the AM 82b. At this time, if the row address of the read address RD ADR to be read next is different from the row address at the time of R1, a miss hit process for precharging the row address and activating the row address again is necessary. Is done. When R2 is issued from the image processing unit 71 as the read address RDADR at T2, the mishit detection unit 72b of the bus control unit 74a compares the row address of R1 with the row address of R1. RDM
TH is issued. Thereby, the clock driver 76
Stops the supply of the clock signal 760 to the image processing unit 71
Is stopped, and the updating of the addresses RDADR, WRADR3, and WRADR is stopped in the period from T4 to T6, and the address before the stop is retained for the period. During this time, the bus control unit 74a issues a precharge (Pre) command and a row address activation (Act) command corresponding to R2 to the synchronous DRAM 82a to perform a mishit process. During the period in which the mishit process is being performed, no new data is read, and in response to this, valid write data is interrupted.
Receives the mishit signal RDMTH and is in an idle state during a period from T5 to T7.

FIG. 36 is a timing chart showing an example of a case where a mishit occurs during writing. Write address WRAD issued at T2 from image processing section 71
Assume that R misses. Assuming that a mishit of the write address WRADR3 is detected in the bus control unit 74b, the mishit is found in the T4 state. Since the data and write address corresponding to another read address have already been issued, such information is lost during the mishit processing. In this embodiment, the read address RD ADDR
At the same timing as above, the write address WRADR is detected as a mishit, and when a write mishit is detected, image processing and address updating are idled from the time of reading to prevent data and addresses from being lost during the write mishit processing period. Is done.

In FIG. 36, the flow of the pipeline when a miss occurs at the write address W2 and the flow of the pipeline when a miss occurs at the read address R2 in FIG. 35 are made equal to each other. More specifically, in states T1 to T10 representatively shown in both FIG. 35 and FIG. 36, the output states of the read address RD ADR and the write address WRADR output by the image processing unit 71 are in the middle of a write error. Even if a hit occurs or a read-out mishit occurs, a fixed order can be maintained without being disturbed. In other words, even if a mishit process is interposed at the time of reading / writing from / to the synchronous DRAMs 82a and 82b, it is possible to completely prevent the pipeline of the image processing in one state and one cycle from being disturbed.

<< Competition between Mishit Processing and Interrupt Processing >> The synchronous DRAMs 82a and 82b can be accessed not only by the image processing section 71 but also by the CPU 75. Synchronous DRAM 82a,
This is because the command and parameters of the image processing unit 71 are also stored in 82b. CPU 75 is synchronous DRA
When accessing the M82a, 82b, the CPU 75
Issues an interrupt request signal SDCACK to the clock driver 76 and the bus control unit 74a in order to interrupt the processing of the image processing unit 71 and execute the mishit process as in the case of the mishit. Although not particularly limited, it is assumed that the interrupt request signal SDCACK is maintained at an active level such as a low level during an interrupt period.
The clock driver 76 receives the interrupt signal SDCACK
When the clock signal 760 is received, the supply of the clock signal 760 to the image processing unit 71 is stopped. At this time, the supply suspension period of the clock signal 760 can be an arbitrary period until the interrupt signal SDCACK is negated to an inactive level such as a high level. The mishit processing at the time of the interruption is performed by the synchronous DRAM 82a,
This is performed unambiguously by changing the access subject to 82b to the CPU 75. Forcibly by the output of a circuit that detects a level change of the interrupt signal SDCACK to the active level and generates a one-shot pulse. Mis-hits occur. CPU75
When the interrupt is terminated, the image processing unit 71 resumes the operation again. However, the mishit signal detected by the mishit detection unit 72a cannot guarantee correct operation while the image processing unit 71 is stopped. Therefore, when the interruption of the CPU 75 is terminated and the image processing section 71 is operated again, the level change of the interruption signal SDCACK to the inactive level is detected and the output of the circuit for generating the one-shot pulse is forcibly performed as described above. Mis-hits occur.

<< Detailed Example of Internal Circuit >> FIG. 39 is a block diagram showing an example of the image processing section 71. As shown in FIG. Graphic pipeline manager GPM is synchronous DRAM 82
a command is read out from the read address generating unit 3
01, write address generator 302, data generator 3
Set parameters to 03 and start. The read address generator 301, the write address generator 302, and the data generator 303 have a sequencer SEQ therein and have a read address DRADR and a write address WRA, respectively.
DR and data GDAT are generated. Input data 751a
Is combined with the data GDAT created by the data generation unit 303 by an arithmetic unit 308 such as an arithmetic logic unit, and processed into output data 751 b via a timing adjustment latch 309. The clock signal 760 supplied from the clock driver 76 is distributed to each part of the internal circuit by the clock driver 311, and each internal circuit is operated in synchronization with the distributed clock signal. Therefore, when the supply of the clock signal 760 is stopped, the operation of the image processing unit 71 is stopped.

FIG. 40 shows an example of the clock driver 76. The clock signal 781 input from the clock generator 78 drives the driver (DRV) 761 and is further distributed to the drivers (DRV) 762, 763, 764. The output of the driver 762 is the synchronous DRAM 82
a, 82b as the clock signal CLK. The OR gate (OR) 767 outputs a logical OR signal MTH of the interrupt signal SDCACK and the mishit signal RDMTH, which are each a low enable signal. An AND gate 766 receives the output clock signal of the driver 761 and the output of the OR gate 767, and supplies both AND signals to the driver (DRV) 765 to generate the clock signal 760. Therefore, the output of the AND gate 766 is fixed at a low level due to a mishit or a CPU interrupt, and the supply of the clock signal 760 to the image processing unit 71 is stopped. Clock signals Cb, Cc
Is an operation reference clock signal supplied to the bus control units 74a and 74b.

FIG. 41 is a block diagram showing an example of the bus control section 74a. The read address RD ADR from the image processing unit 71 and the address 752 from the CPU 75 are selected by the selector 900 and supplied to the mishit detection unit 72b and the multiplexer 903. Mishit detection unit 72
In b, a row address is extracted by the separation circuit 722. Which bit of the address bus corresponds to the row address depends on the mode at that time.
The determination is made based on the mode designation information 749 supplied from the CPU 75. The extracted row address is stored in the latch 721, and the row address accessed this time (separation circuit 722)
Output) and the previously accessed row address (latch 7
21 output) are compared by the comparator 723. Although not particularly limited, the coincidence output of the comparison result is at a high level.
The output of the comparator 723 is a two-input OR gate 724.
To one input. The output of the one-shot pulse generation circuit 725 is supplied to the other input. The one-shot pulse generation circuit 725 detects a change in level of the interrupt signal SDCACK from active to inactive and vice versa, and outputs a one-shot pulse that is kept high for a predetermined period. Therefore, if there is an interrupt request, a state similar to that of the mishit detection is forcibly created in any case when the interrupt request is released. The output signal 908 of the OR gate 724 is an OR gate (O
R) 907 and the sequencer 905. The other input of the OR gate 907 has the mishit detection circuit 72
The miss hit signal WRMTH from a is supplied. Therefore, if a mishit is detected in any of the mishit detection circuits 72a and 72b, the mishit signal RDMTH output from the OR gate 907 is activated. When the sequencer 905 is notified of the mismatch of the comparison result by the internal signal 908, the sequencer 905 executes a mishit process. The output of sequencer 144 passes through latch 906,
It is connected to a select terminal of a multiplexer 903 for selecting an address to the synchronous DRAM 82a, and is also connected to an input of a latch 904, so that the current status can be given to the sequencer 905 via the latch 904. . Multiplexer 903 determines which address bits are supplied to synchronous DR.
Whether to supply to AM is selected according to the output of the latch 906. The output of the multiplexer 903 is synchronous DRA.
Connected to the address bus to M82a. The data bus 751 of the CPU 75 and the data bus 75 to the image processing unit 71
1a is selectable by a selector 905, and is connected to a data bus of a synchronous DRAM 82a via a bus buffer 902. The selectors 900 and 901 output the instruction signal S
Controlled by EL. The instruction signal SEL is supplied to the delay circuit 92
Output from 0. The delay circuit 920 outputs the interrupt signal S
When the DCACK is changed, the instruction signal SEL (interrupt signal SDCA) changed at the timing when the change is reflected on the clock signal 760 of the clock driver 76.
CK delay signal). When the instruction signal SEL is at a low level, that is, when the CPU interrupt is activated, the selectors 900 and 901 select the connection with the CPU 75 side. The bus buffer 902 is controlled by the output of the sequencer 905. The bus control unit 74b
It should be understood that the circuit configuration of FIG. 41 is different from the bus control unit 74a in that the circuit configuration for detecting a mishit is omitted. It should be understood that the mishit detector 72a has the same configuration as the mishit detector 72b of FIG. 41 except that the input / output signals are different.

<< Image Processing System by Read / Write Time Division >> FIG. 34 shows an embodiment in which one synchronous DRAM 82 is read / written in a time division manner to perform the above-described image processing. Image data is read from the sensor 80, and the image processing unit 71 executes distortion correction processing, high image quality processing, encoding processing, and the like. These processes are input to the bus control unit 74 using the read address RD ADR, and data is transferred from the synchronous DRAM 82 to the bus 751.
And read the image-processed data using the same bus 75.
This is realized by writing at the write address WRADR by using No. 1. 821 and 822 are synchronous DRA
A data bus and an address bus connecting the M82 and the bus control unit 74.

FIG. 42 is a block diagram showing an example of the bus control section 74. The bus control unit 74 is different from the configuration of FIG. 41 in that the CPU 75 and the image processing unit 71 are connected by buses 752 and 751 common to both, and the mishit signal 908 is formed by a mishit detection circuit 72b included therein. Is different from Circuit elements having the same functions as those in FIG. 41 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Although not shown, the clock driver 76 of this embodiment is not shown.
The basic configuration of c is the same as that of the clock driver 76 in FIG. RDMHT in FIG. 40 is replaced by 908, and the clock signal Cb is not required. Therefore, as in the above embodiment, when a mishit occurs, the supply of the clock signal 760 to the image processing unit 71 is stopped, and the supply of the clock signal 760 to the image processing unit 71 is also forcibly interrupted by the CPU 75. And a forced mishit is created first, and a forced mishit is also created at the time of interrupt release.

FIGS. 37 and 38 are timing charts showing an example of operation in the system shown in FIG. 34 in which a single memory is used for read / write in a time-division manner. The read address R1 issued at T1 reads data DR1 from the synchronous DRAM 82 by the bus control unit 74. The data DW1 processed by the image processing unit 71 is written to the write address W1. Assuming that the CAS latency of the read data is 1 (the latency of the write data is 0), it is necessary to create an empty space for one cycle when transitioning from read to write. This is the NOP of the T3 status of the bus status RWBST. FIG.
Shows the mishit processing at the time of reading, and FIG. 38 shows the timing of the mishit processing at the time of writing. Since reading and writing are performed in a time-division manner, address updating and image processing are stopped when a mishit occurs in any of read and write. When reading / writing is performed in a time-division manner, it prevents the flow of image processing from being disturbed.

<< Application Example of Image Processing Unit >> FIG. 43 is a block diagram showing a case where the image processing unit 71 is adapted to facsimile. Synchronous DR at data control unit 1110
The signal serially extracted from the AM 82 is separated and divided into data for each line. In the edge enhancement unit 112,
The surrounding pixels are referred to using the data from the sensor 80 and the output from the control unit 1110 to emphasize the density difference between the point of interest and the surrounding pixels. The latches 1121 to 1129 are registers that store the value of the target point and the pixels around it. By calculating the outputs of these registers, the edge emphasis output 113 is calculated.
0 is formed. The error diffusion unit 113 distributes error data for binarizing the pixel of interest 1135 to peripheral pixels 1131 to 1134 in order to binarize the multi-value data with high image quality. The error data for the next line is the selector 11
5, the error data of the current line is supplied from the data control unit 1110 to the memory bus 752. Since the output of the error diffusion unit 113 is binary data, the output is packed by the pack processing unit 114 and supplied to the memory bus 751 via the selector 115, which outputs the data to the synchronous DRA.
M82 is written. The selector 115 can be selected so that data that is currently being input can also be written as data for the next line processing.

On the other hand, the read and write addresses are generated by the read counter 116 and the write counter 117. The counter is controlled by the clock driver 76.
, And is controlled so as to stop by a mishit or an interrupt from the CPU 75. When the clock signal 761 from the clock driver 76 is suddenly stopped today, the operation of the internal latch and register is also stopped, and the processing is controlled so as not to proceed.

FIG. 44A shows a synchronous DRAM.
An example of using the time slot 82 in a time slot system is shown. This is because when the synchronous DRAM 82 and the data processor 70a have one data bus, it is necessary to perform the processing in a time-division manner. In this example, the read L1R of the previous line, the read L2R of the line before the previous line, and the error data read L of the current line
ER, pre-charge processing PRE at the time of mishit, row address activation ACT, write LO of current line data
The synchronous DRAM 82 is accessed in the order of W, the error data writing LEW of the current line, and the writing LKW of the packed binarization result data.

FIG. 44 (b) shows an example of the address map. L0 is the current line, L1 previous line, L2
The data of the line two lines before, LE is error data, and LK is each area of result data. These are synchronous DRAM
The area of the line memory area 82 is mapped on the same memory address as the page buffer area of the synchronous DRAM 82.

FIG. 45 is a block diagram when the image processing unit is applied to graphics processing. Compared with the application example to the facsimile, the edge emphasizing unit and the error diffusion unit are changed to the combined data creating unit 118 to combine the source data with other values 1186 to create output data, and to output the result as the delay element 1183 , 1184, 1185 to perform phase guarantee and output to the bus 752.

FIG. 46 is a block diagram showing an example in which the image processing section is applied to a printer. Synchronous DRAM 8
2 is supplied to the coordinate calculation unit 1191, the calculated data is calculated by the straight line generation unit 1192, and finally the vector calculation is performed by the vector drawing unit 1193, and the calculation result is transmitted via the bus 752 to the synchronous DR.
AM82 is written. The basic operation is the same as the example applied to the facsimile.

The invention made by the present inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited thereto, and various changes can be made without departing from the gist of the invention. No.

For example, image data is not limited to image data to be displayed on a monitor, but may be image data to be printed by a page printer. Further, it goes without saying that the present invention can be applied not only to an image display device but also to various data processing systems that must process a large amount of data using a memory.

[0111]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by supplying the clock to the memory from the processing means, the skew of the clock, address, data, and control signal is minimized, and the command (control signal) from the data processor is reliably transmitted to the memory such as the synchronous DRAM. In other words, the synchronous DRAM can be accessed reliably in synchronization with the clock signal.

When accessing the same memory from a plurality of data processing modules having different operating frequencies, a means for selecting a clock signal having a frequency corresponding to the data processing module for which the bus access right has been granted is provided. The skew with the data processing module can be minimized, and the command from the data processing module can be reliably executed.

By providing means for setting the clock terminal to high impedance together with the address, data, and control signal to the memory, when the memory is opened to an external bus, the memory such as the synchronous DRAM by another data processor can be used. It is permissible to supply the optimal clock signal from the another data processor,
As a result, even when a memory such as a synchronous DRAM is shared by a plurality of data processors, access to the memory is minimized in accordance with the operation speed of the data processor, minimizing the skew of addresses, data, and control signals. can do.

A processing means for issuing a mode register setting command to the memory in accordance with the data processing condition is provided, and by setting a burst length optimal for the content of image data processing, efficient memory access can be realized.

By providing a bus control unit for generating a precharge command and an active command to a memory bank different from the memory bank currently accessing the memory while the data is currently being accessed, the pipeline of the memory can be pipelined. And can improve the memory access throughput.

By comparing the previous row address with the current row address, it is determined whether or not there is a mishit, and the precharge and the activation of the row address are executed, so that a desired address can be accessed.

By providing a means for stopping the image processing operation for a predetermined period upon detection of a read / write address mishit, data in the image processing pipeline can be held without being destroyed.

By detecting the mishit of the write address at substantially the same timing as the mishit of the read address, the mishit at the time of writing can be
Feedback can be provided to mishits at the time of reading, and it is possible to prevent pipeline disruption due to mishits without performing complicated processing by providing a buffer etc. to prevent data overflow at the time of write mishits. it can.

When there are a plurality of access entities to a memory such as a synchronous DRAM, a means for detecting, for example, a write miss by uniquely generating a mishit in response to a change in the access entity is included. Including a means for detecting a write mishit after another data processing module accesses the synchronous DRAM in place of the operation of the data processing module (the operation of the write mishit detecting means during that time is uncertain) Even if the data processing module starts operating, it is possible to reliably prevent the miss-hit processing that may occur if the operation depends on the operation of the write-miss hit detecting means. In other words, forcibly causing a mishit at the time of changing the access subject to the memory, the indetermination of the miss hit determination at the time of resuming the operation of the data processing module whose operation has been stopped due to the change of the memory access subject, etc. And the reliability of the processing at the time of a mishit can be improved.

With the above effects, the synchronous DRAM
By realizing at low cost the mishit processing that occurs when applying to the image processing system, it is possible to integrate the memories and provide a low-cost, high-performance device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a synchronous DRAM.

FIG. 3 is an example block diagram of a bus control unit.

FIG. 4 is an explanatory diagram showing a state transition of a sequencer of a bus control unit.

FIG. 5 is a timing chart showing an example of one-dot read-modify-write in a drawing process.

FIG. 6 is a first half timing chart showing interrupt processing of the display processing module.

FIG. 7 is a second half timing chart following FIG. 6;

FIG. 8 is a first half timing chart showing burst read of display data.

FIG. 9 is a second half timing chart following FIG. 8;

FIG. 10 is a first half timing chart showing bit block transfer in a drawing process.

FIG. 11 is a second half timing chart following FIG. 10;

FIG. 12 is a first half timing chart showing an access operation in a form of interleaving display and drawing processing.

FIG. 13 is a second half timing chart following FIG. 12;

FIG. 14 is a block diagram showing an embodiment for drawing control by bit block transfer.

FIG. 15 is an example mapping diagram of physical memory addresses and logical coordinates in the system of the present embodiment.

FIG. 16 is a mapping diagram showing another example of physical memory addresses and logical coordinates in the system of the present embodiment.

FIG. 17 is a mapping diagram showing another example of physical memory addresses and logical coordinates in the system of the present embodiment.

FIG. 18 is a block diagram of an embodiment for setting addresses, addresses, data, control signals and clock terminals to a synchronous DRAM to high impedance.

FIG. 19 is a block diagram of another embodiment for setting addresses, data, control signals, and clock terminals to a synchronous DRAM to high impedance.

FIG. 20 shows that R is connected to the same data bus as the synchronous DRAM.
It is a block diagram of the image processing system to which OM was connected.

FIG. 21 is a block diagram of an image processing system that supplies a plurality of frequency clocks directly from a rendering display processor to a synchronous DRAM.

FIG. 22 is a block diagram of an image processing system in which clocks of a plurality of frequencies supplied to a synchronous DRAM are supplied from the outside.

FIG. 23 is a block diagram of an embodiment of an image processing system configured to include a single module as in the case where the rendering display processing processor does not include a rendering processing module.

FIG. 24 is a block diagram of an embodiment of an image processing system having a clock selector for selecting clocks of a plurality of frequencies with a single module.

FIG. 25 is a block diagram of an embodiment in which an address bus or a data bus between a module and a bus control unit is set to a dedicated bus.

FIG. 26 is a block diagram of an embodiment in which a mode register setting command is issued to a memory at an input timing from an external terminal.

FIG. 27 is a flowchart showing an execution sequence by a dedicated instruction for issuing a mode register setting command.

FIG. 28 is an explanatory diagram showing a format of a dedicated instruction for issuing a mode register setting command.

FIG. 29 is a block diagram of an embodiment in which a set value of a mode register of a synchronous DRAM can be directly specified from an internal data bus.

FIG. 30 is a block diagram showing an embodiment in which a mode register setting command of a synchronous DRAM is issued in synchronization with rewriting of an internal register exclusively mapped by an address decoder.

FIG. 31: SDARM by microprogram control
FIG. 7 is a block diagram of an embodiment for issuing a mode register setting command.

FIG. 32 is a block diagram illustrating an example of a system in which a plurality of rendering display processors share a single synchronous DRAM.

FIG. 33 is an example block diagram of an image processing system including a data processor according to another embodiment of the present invention.

FIG. 34 is a system block diagram of an embodiment in the case of performing image processing by reading / writing one synchronous DRAM in a time-division manner.

FIG. 35 is an example operation timing chart when a mishit occurs at the time of reading in the middle of pipeline processing in the system of FIG. 33;

FIG. 36 is a timing chart illustrating an example of a case where a mishit occurs during writing in the system of FIG. 33;

FIG. 37 is an example operation timing chart when a mishit occurs at the time of reading in the system of FIG. 34;

38 is an example operation timing chart in a case where a mishit occurs at the time of writing in the system of FIG. 34;

FIG. 39 is a block diagram illustrating an example of an image processing unit in the data processor of FIG. 33;

FIG. 40 is a block diagram illustrating an example of a clock driver in the data processor of FIG. 33;

FIG. 41 is a block diagram illustrating an example of a bus control unit in the data processor of FIG. 33;

FIG. 42 is a block diagram illustrating an example of a bus control unit in the data processor of FIG. 34;

FIG. 43 is a block diagram when the image processing unit is adapted to facsimile.

FIG. 44 is an operation explanatory diagram in the case where a synchronous DRAM is used in a time slot system.

FIG. 45 is a block diagram illustrating an example in which the image processing unit is applied to graphics processing.

FIG. 46 is a block diagram illustrating an example in which the image processing unit is applied to a printer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Drawing display processing processor 12 Drawing processing module 13 Display processing module 14 Bus control unit 16 Clock driver 160 Clock buffer 17 Clock generation unit 22 Synchronous DRAM CLK Clock signal 22a, 22b Synchronous DRAM 30 Mode register BANKA, BANKB Memory bank 121 Address Counter 122 Transfer word number counter 123 Comparator 124 Source RAM 126 Destination RAM 127 Arithmetic unit 141 Arbiter 142 Selector 143 Sequencer 145 Address selector 149 Three-state control bit 1495 Bus buffer 70 Data processor 71 Image processing unit 72a, 72b Mishit detection unit WRMTH , RDMTH mishit signal 74a, 74b Scan control unit 75 CPU SDCACK interrupt signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/407 G11C 11/34 362S (72) Inventor Keisuke Nakajima 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Akihiro Katsura 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Takashi Miyamoto Kamisumihoncho, Kodaira, Tokyo 5-20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Kenichiro Omura 5-20-1, Kamimizu Honcho, Kodaira City, Tokyo Incorporated Hitachi Semiconductor Co., Ltd. (72) Inventor Mitsuru Watanabe Ibaraki 7-1-1, Omika-cho, Hitachi City, Hitachi Prefecture F-term in Hitachi Research Laboratory, Hitachi Ltd. (Reference) 5B060 AB19 CA15 5M024 AA49 BB27 BB34 CC99 DD83 DD92 DD97 JJ02 JJ26 JJ43 JJ54 KK24 KK35 KK40 PP01 PP07 PP10

Claims (2)

[Claims] 1. A data processing system having a data processing device and a storage device, wherein the storage device has a plurality of storage areas and an address counter, and receives an address signal input and data in synchronization with a clock. A signal input / output and a control signal input are performed, and a burst mode for accessing one storage area while updating an address preset in the address counter is provided. For the operation of the one storage area operating in the burst mode, In parallel, an address active command for setting an access address in another storage area can be received. The data processing device includes a data processing unit and a bus control unit, and the data processing unit includes the storage device By generating data and addresses for accessing the memory, and using the storage device at least as a frame buffer, Performs data processing, and the bus control unit issues an address active command according to an access instruction from the data processing unit to a storage area different from the storage area being accessed in the burst mode, and can set an access address in advance. A data processing system, characterized in that: 2. A data processing system comprising a first storage device, a second storage device, a memory bus, a bus control unit, a data processing unit, and a delay circuit unit, wherein the first storage device, the second storage device, In the memory, an address signal input, a data signal input / output, and a control signal input are performed in synchronization with a clock, a row address is latched, and the same row address can be accessed continuously by updating a column address. A bus is assigned to each of the first storage device and the second storage device; the bus control unit is assigned to each memory bus; the data processing unit is connected to the bus control unit; And a data and an address for accessing the second storage device are generated, and the data read from the first storage device is processed. The access addresses of the first storage device and the second storage device for storing the result of the processing are generated in parallel, and the delay circuit unit converts the access address of the second storage device output by the data processing unit into data. A data processing system, wherein the data is transmitted to the second storage device with a delay corresponding to a processing time.