JPH03183097A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To utilize a semiconductor memory device for the frame buffer of a graphic display device and to enable high-speed drawing by generating a write mask by one part of an address signal and a data width control signal and executing write to a memory cell array with arbitrary data width. CONSTITUTION:When executing write with the data width narrower than the data width of a word, a write mask generating circuit 3 generates the write mask from the control signal, which comes from a data width control signal input terminals 5, and one part of a column address from an address signal input terminals 6. A write mask selecting circuit 4 selects any one of the write mask from a W/IO terminal 7 and the output of the circuit 3 according to a signal from a mask control signal input terminal 10 and applies selected one to a data memory part 1. When the mask from the terminal 7 is selected, write is executed at conventional operation timing. When the output of the circuit 4 is selected, write can be executed at an arbitrary position with the arbitrary data width and a high-speed page mode can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for application to an image memory.

2. Description of the Related Art In an image display device that displays image data such as figures and characters on a CRT screen, a memory for storing display image data called a frame buffer is required. A dual port memory is generally used for this frame buffer, which has a random port for writing (drawing) image data and a serial port for reading data necessary for display on a CRT.

This dual port memory is described in, for example, "Nikkei Electronics JP" published by Nikkei McGraw-Hill on May 20, 1985.
195-219, and has the configuration shown in FIG. In FIG. 3, 100 is a data storage unit including a memory cell array for storing image data corresponding to a display screen, and 101 is a serial shift register for serial readout. In order to draw image data such as figures and characters and display it on the CRT, the image data is first written from a random port to the data storage unit 100. One row of data is transferred to serial shift register 1.
This is done by transferring the data to CRT 01 and then supplying the data that continues successively from this serial shift register 101 to the CRT. In this way, when reading data necessary for display on a CRT, one row of data can be read with one access to the data storage unit 100 from the random port, so the number of memory accesses required for reading can be reduced. The drawing speed is improved by increasing the time available for writing from random ports.

102 to 107 are random port signal terminals, 108.
109 is a signal terminal of the serial port. 102 is an address signal input terminal. 103 is a write mask and data input/output signal W/10 signal terminal, which provides a write mask and write data when writing data;
Output data when reading. 104 is RAS (Row
105 is a CAS (Column AddreSs 5trobe) signal input terminal that controls the timing of giving a column address.
probe) signal input terminal. When writing from a random port, a write mask is used to control whether each bit of input data is written to each bit of the write data, and whether this write mask is enabled or disabled. A write mask control signal can be provided. A write mask control signal and write enable signal We/WE input terminal 106 provides a control signal for validating or invalidating a write mask, and also provides a signal for controlling write timing during writing.

Reference numeral 107 denotes a serial data transfer control signal and output enable signal DT10E input terminal, which provides a signal for controlling serial data transfer and also provides an output control signal for read data when reading data. 108 is a serial clock input terminal, and data in the serial shift register 101 is continuously read out using this clock. 109 is a serial data output terminal.

As shown in FIG.
It is constructed by using a plurality of planes with the same capacity as the number of pixels on the display screen. FIG. 4 shows an example in which eight planes, indicated by 201 to 208, are used to express 256 colors.

Here, each of the planes 201 to 208 is composed of a number of memory chips corresponding to the number of pixels of the display screen, and the data width of a word selected in one access is fixed.

When drawing on this 7-frame buffer, the access method differs depending on the drawing mode.

For example, if this frame buffer is accessed with 8-bit data and the data width of the word selected in one access in each plane is 8 bits, when writing data in pixel units, the 4th IN As shown in (a), data is written one bit at a time to each plane along the plane direction. When writing data at high speed for each plane, 8-bit data is written along the plane surface as shown in FIG. 4(b).

Problems to be Solved by the Invention As mentioned above, in conventional image memory, the data width of a word selected in one access is fixed, and data is written in pixel units as shown in FIG. 4(a). In this case, since only one bit is written to the selected word in each plane, it is necessary to provide a write mask for the other bits. A timing chart for writing in this case is shown in FIG. 5 (written on the same page as FIG. 2). FIG. 5 shows a write operation for two pixels (two cycles).

The address signal input terminal 102 receives the row address A1 at the falling timing tl and t3 of the RAS signal 104.
is the falling timing t2. of the CAS signal 105.
At t4, RAM addresses A2 and A3 are given to specify the word to be written. The W/10 signal terminal 103 has
The write mask is applied at timings tl and t3, and the write mask is applied at timings t2 and t3. t
Give write data at timing 4. WB/WE
A write mask control signal is applied to the input terminal 106 at timings tl and t3, and a write enable signal is applied during a write operation.

In this way, when writing, the W/IO terminal 10
Since the write mask and write data are given for each cycle from 3, one write cycle is always tc.
It becomes ycl.

In image data drawing, there is a high probability that after a certain pixel is drawn, the next time the vicinity of that pixel will be drawn. Therefore, when writing multiple cycles to the frame buffer, it is often the case that only the column address is changed without changing the row address, but in the write cycle as described above, the write mask and write Since data must be supplied from the same terminal, it is not possible to use a high-speed operation function called high-speed page mode, in which only the RAM address is changed to perform high-speed access when the row address is fixed.

The present invention is intended to solve these conventional problems, and aims to provide a semiconductor memory device that can be used in a 7-frame buffer of a graphic display device to perform high-speed drawing.

Means for Solving the Problems In order to achieve the above object, the present invention provides means for inputting a data width control signal, a part of an address signal, and a data width control signal in a semiconductor memory device that performs data input/output of multiple bits. The memory cell array includes means for generating a write mask using a method of generating a write mask, and is configured to be able to write to a memory cell array with an arbitrary data width.

Effect of the Invention With the above configuration, the present invention allows the data width to be written to be set for the data width of a selected word in a write operation from a random port without applying a write mask externally. Even in the required write operation, if the row address is fixed, a high-speed page mode can be used in which writing is performed by changing only the column address, and this can be used in image display devices to realize semiconductor memory devices that can perform high-speed drawing. can do.

Embodiment FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, 1 is a data storage section including a memory cell array for storing image data corresponding to a display screen, and 2 is a serial shift register for serial readout. 3 is a write mask generation circuit, and 4 is a write mask selection circuit.

Reference numeral 5 denotes a data width control signal input terminal for controlling the value of the data width to be written, and the data width control signal is applied from an external means (not shown). 6 to 11 are random port signal terminals, and 12.13 are serial port signal terminals.

Among the signal terminals 6 to 11, 6 is an address signal input terminal. Reference numeral 7 denotes a write mask input/output signal W/10 signal terminal, which provides a write mask and write data during writing, and outputs data during reading. Reference numeral 8 denotes a RAS signal input terminal that controls the timing of providing a row address, and 9 a CAS signal input terminal that controls the timing of providing a column address. Reference numeral 10 denotes a write mask control signal and write enable signal WB/WE input terminal, which controls whether the write mask is valid or invalid and controls the write timing. Reference numeral 11 denotes a serial data transfer control signal and output enable signal DT10E input terminal, which controls serial data transfer and output of read data. Reference numeral 12 denotes a serial clock input terminal, which continuously reads data from the serial shift register 2. 13 is a serial data output signal terminal.

When writing with a data width smaller than the data width of a word selected in one access, the write mask generation circuit 3 generates a control signal from a data width control signal input terminal 5 and an address. Signal input terminal 6
Generate a write mask from part of the column address from . For example, if the data width of the word selected in one access is 8 bits, and the data width to be written is 1 bit, the data width control signal input is applied to the selected 8 bits. 1 by the control signal from terminal 5
It is controlled to generate a write mask in which only bits are writable. By using the lower three bits of the address input signal to control the position of the write mask that makes writing impossible, it is possible to write any one bit.

The write mask selection circuit 4 selects either the write mask applied from the W/10 terminal 7 or the output of the write mask generation circuit 3 according to the signal from the mask control signal input terminal 10, and selects either the write mask applied from the W/10 terminal 7 or the output of the write mask generation circuit 3 to select the write mask from the data storage section 1. give to When this write mask selection circuit 4 selects the write mask given from the W/I O terminal 7,
A write operation is performed at the write operation timing in the conventional example shown in FIG.

The write mask selection circuit 4 is the write mask generation circuit 3.
If the output is selected, the write operation is performed at the write operation timing as shown in FIG. That is, the row address A1 is input to the address signal input terminal 6 at the falling timing t1 of the RAS signal 8.
Column address A2 is given at timing t2 of the falling edge of S signal 6 to designate the word to be written. W
Write data is applied to the /10 signal terminal 7 at timing t2. A mask control signal for selecting the output of the mask generation circuit 3 is applied to the WB/WE input terminal 10 at timing tl, and a write enable signal is applied during a write operation. A data width control signal is applied to the data width control signal input terminal 5 at the timing tl. Using these signals, writing can be performed at any position with any data width using the mask generated by the write mask generation circuit 4. In this case, the cycle time is tcyc
It becomes l.

If you want to continue writing without changing the row address A1 or by changing only the RAM address, you can apply the column address A3 at timing t3, and write the write data and write enable signal to the address A.
3, the position of the write mask is controlled and writing is performed at an arbitrary position. In this way, when writing cycles are continued without changing the row address, the writing cycle time from the second time onwards is tcyc2.

In this way, in writing that requires a write mask, when writing to a position where only the column address changes without changing the row address, by generating a write mask using the address signal and data width control signal, Fast page mode can be used.

As described in detail, according to the present invention, with respect to the data width of a word selected in one access, such as when accessing a frame buffer pixel by pixel, the data width is smaller than this data width. Even in the writing mode, writing can be performed using the high-speed page mode, and a semiconductor memory device capable of high-speed drawing can be realized especially when used in an image display device.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a timing chart showing write operation timing in the device, and FIG. 3 is a schematic block diagram of a conventional semiconductor memory device. FIG. 4 is a diagram illustrating the structure of the frame buffer and the access method based on the drawing mode, and FIG. 5 is a timing chart showing the timing of the write operation of the conventional device. DESCRIPTION OF SYMBOLS 1... Data storage part, 2... Serial shift register, 3... Write mask generation circuit, 4... Write mask selection circuit, 5... Data width control signal input terminal, 6... Address Signal input terminal, 7...W/I O
Signal input/output terminal, 8...RAS signal input terminal, 9...
- CAs signal input terminal, 10... WB/WE signal input terminal, 11... DT10E signal input terminal, 12...
Serial clock signal input terminal, 13... serial data output terminal.

Claims (1)

[Claims] a data storage means including a memory cell array for storing a plurality of bits of data; an output means for continuously reading and outputting the data written in the data storage means; a means for inputting a data width control signal from the outside; A semiconductor memory device comprising mask generating means for generating a write mask based on a data width control signal and a part of an address signal and applying it to the data storage means.