JPH1050055A - Semiconductor memory and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly write various data by enabling revising the write-in data at every block write. SOLUTION: This device is provided with a decoding means 12 decoding a block write command specifying the simultaneous write of the data related to plural column addresses and input data control means 13, 14 fetching the data imparted to an external terminal whenever the block write command is imparted based on the decoded result of the decoding means as the write-in data to a memory cell array. The write-in data is capable of revising at every block write by fetching the data imparted to the external terminal whenever the block write command is imparted based on the decoded result of the decoding means as the write-in data to the memory cell array.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Furthermore, the present invention relates to a technique for improving a block write function in the technique, and for example, to a technique effective when applied to an image memory.

[0002]

2. Description of the Related Art DRAM as an example of a semiconductor memory device
As described in the "LSI Handbook (pages 486 to)" issued by Ohm Co., Ltd. on November 30, 1984, random access is mainly performed, and a row address, Memory cells are selected by sequentially reading column addresses.
A normal DRAM is mounted on a system and performs a read / write operation asynchronously with a system clock. On the other hand, as a semiconductor memory device operated in synchronization with the system clock, an SDRAM (synchronous dynamic memory) is used.・ Random access memory). Since the SDRAM can input and output data, addresses, and control signals in synchronization with a clock, it is possible to operate a large-capacity memory similar to a DRAM at a high speed comparable to that of an SRAM. By specifying the number of data to be accessed for the word line by the burst length, a plurality of data can be read or written continuously by sequentially switching the selection state of the column system by the built-in column address counter.

An SGRAM (synchronous graphic random access memory) has a function equivalent to that of the SDRAM and a function of simultaneously writing a plurality of Y addresses (column addresses) (referred to as a block write function). Memory). This SGRA
In M, drawing processing such as painting a simple rectangular area such as a window of a display screen in a computer system with the same color can be performed at high speed by a block write function.

In a general block write function, write data for block write is set before block write. At this time, the number of columns (number of addresses) of simultaneous writing is fixed, and the number of writing columns cannot be changed in the same block write cycle.

[0005] As an example of a document describing the block write function, there is "8M bit synchronous graphic RAM (8MSGRAM) of Hitachi Memory IC Data Book ('95 .8), HM5283206 series".

[0006]

In a general block write function, write data for block write is set before block write. At this time, the number of columns for simultaneous writing is fixed. However, according to the study by the present inventor, the number of columns that can be simultaneously written is fixed, and the write data cannot be changed for each block write, so that the block write target is a simple rectangular area such as a window on a display screen. It has been found that it takes a long time to draw because a complex shape cannot be block-written.

An object of the present invention is to make it possible to write more various data at high speed by making it possible to change write data for each block write.

Another object of the present invention is to improve the data write speed by enabling the number of simultaneously writable columns to be changed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a decoding means (301) for decoding a block write command instructing simultaneous writing of data for a plurality of column addresses, and an external terminal each time a block write command is given based on a decoding result of the decoding means. And input data control means (13, 14) for taking in the data given to the memory cell array as write data into the memory cell array to constitute a semiconductor memory device. The input data control means (13, 14)
Each time a block write command is applied, data applied to an external terminal is fetched as write data to a memory cell array based on a decoding result of the decoding means.
This makes it possible to change the contents of the write data for each block write, thereby achieving high-speed writing of more diverse data.

A decoding means (30) for decoding a column number setting command designating the number of write columns in simultaneous writing of data for a plurality of column addresses.
1) and based on the decoding result of this decoding means,
A semiconductor memory device is constituted by providing a column number control means (27) for controlling the number of write columns. The column number control means controls the number of write columns based on a decoding result of the decoding means. This makes it possible to change the number of simultaneously writable columns, thereby achieving an improvement in the data write speed.

Further, when the data processing device is configured to include an image memory (330) capable of storing image data for display and a means (370) capable of outputting the data stored in the image memory, the image processing device may include The above semiconductor storage device can be applied as a memory.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate understanding of the present invention, the principle of the present invention will be described here.

FIG. 4 shows main operation timings of the semiconductor memory device according to the present invention.

Write column number setting command A (SMR
By S), the number of columns to be simultaneously written by the block write is set. The number of columns is specified by an address N externally supplied at the same time as the write column number setting command A. For example, the relationship between the address N and the number of columns n specified by the address N can be determined as follows.

That is, the number of columns n = 8 is specified by the address N = 0, and the number of columns n = 16 is specified by the address N = 1. ACTVM is an active command, and the row address X is taken in by the active command ACTVM.

The NOP command does not affect the operation, but is inserted for a predetermined timing adjustment. BW is a block write command. Each time the block write command BW is given, a block write of input data is performed. For example, the first block write command BW
, A block write is performed on the input data D1.
Block writing is performed for No. 2. Address N = 0
Is specified, the number of columns is n = 8. Therefore, in the block write for the input data D1, the input data D1 is written to an area corresponding to the column addresses Y0 to Y0 + n-1. Further, the input data D2 is written in an area corresponding to the column addresses Y0 + n to Y0 + 2n-1. Each time the block write command BW is given, input data is taken in and block writing is performed. Therefore, if the content of the input data is changed each time the block write command BW is given, it is possible to perform block write of different input data for each block write command. Also, a write column number setting command A
At the same time, the number of columns n required for simultaneous writing can be specified by the address N given at the same time. Therefore, each time the write column number setting command A is given, the number of write columns can be changed. The fact that the contents of the input data can be changed for each block write command and that the number of write columns can be changed each time the write column number setting command is given is different from the case where the method shown in FIG. 5 is adopted. It is advantageous.

That is, in the method shown in FIG. 5, the write data is composed of the SMRS command and the address A6 = 1, A5
= 0, and data D1 given at the same time as this command is written by a block write command BW. The number of columns written simultaneously is fixed,
For example, Y1 = Y0 + Y0 + 7, Y2 = Y0 + 8-Y0 +
As shown by 15, there are eight addresses. Further, the content of the data D1 cannot be changed when the block write command BW is input. If it is necessary to change the contents of the write data, it is necessary to issue the SMRS command again. Therefore, compared with the method of FIG. 4 in which the contents of the input data can be changed every time the block write command BW is input, the time is longer. Take it.

Next, the case where the present invention is applied to a display system of a data processing device will be specifically described.

FIG. 2 shows a computer system which is an example of a data processing apparatus according to the present invention.

This computer system includes a CPU (Central Processing Unit) 310, R via a system bus BUS.
AM (random access memory) 320, ROM
(Read only memory) 340, peripheral device control unit 3
50, a display control unit 360, and the like are connected to each other so as to be able to exchange signals, and are configured as a computer system that performs predetermined data processing according to a predetermined program. The CPU 310 is a logical core of the present system, and mainly includes address designation, information reading and writing, data operation, instruction sequence, acceptance of interrupt, activation of information exchange between a storage device and an input / output device, and the like. And has an arithmetic control unit, a bus control unit, a memory access control unit, and the like. RAM 320 and RO
M340 is positioned as an internal storage device. R
The AM 320 is a main memory into which programs and data required for calculation and control by the CPU 310 are loaded.
The RAM 340 stores programs necessary for calculation and control by the CPU 310 in a read-only state. The peripheral device control unit 350 controls the operation of the external storage device 380 and controls information input from the keyboard 390 and the like. The display control unit 360 controls information display on the CRT display 370. Display control section 360 includes an image memory 330 for storing image data displayed on CRT display 370. The image memory 330 is an SGRAM.

FIG. 3 shows the overall structure of the image memory 330.

The image memory 330 shown in FIG. 3 is not particularly limited, but is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, and forms a memory array 200A forming a memory bank A.
And a memory array 200B forming a memory bank B. Each memory array 200A, 200B
According to the figure, select terminals of memory cells arranged in the same column are coupled to a word line (not shown) for each column, and memory cells arranged in the same row are provided. The data input / output terminals of the cells are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding of a row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data lines. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201B,
A sense amplifier and column selection circuit 202B and a column decoder 203B are provided. The complementary common data line 20
4 is a data input / output terminal I / O via the input / output unit 210
0 to I / O15.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or a value obtained by sequentially incrementing the column address signal according to an operation mode. , To the column decoders 203A and 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (symbol * means row enable or signal inversion), row address strobe signal RAS *, column address strobe signal CAS
*, A write enable signal WE *, and data mask signals DQM0 to DQM3.
Among them, the clock enable signal CKE, the chip select signal CS *, the row address strobe signal RAS
*, Column address strobe signal CAS *, write enable signal WE *, and data mask signal DQM0
An external control signal such as DQM3 and an address input terminal A0
, And an internal timing signal for controlling the operation mode of the SGRAM and the operation of the circuit block based on the level of the signal and the timing of change. Logic (not shown) and mode register 30
0 is provided. Various control signals such as the clock signal CLK, the clock enable signal CKE, and the chip select signal CS * are transmitted from the CPU 310 via the system bus BUS.

Each signal of RAS *, CAS * and WE * is
It is a significant signal when defining a command cycle. The clock enable signal CKE is a signal for indicating the validity of the next clock signal. If the signal CKE is at a high level, the rising edge of the next clock signal CLK is valid, and if it is at a low level, it is invalid. .
The row address signal is defined by the levels of the terminals A0 to A9 in a row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CLK.

The input from the terminal A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at a low level, the memory bank A is selected, and when it is at a high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the non-selected memory bank are not selected, and the input / output unit 210 only for the selected memory bank is supplied to the input / output unit 210. It can be performed by processing such as connection.

The input of the terminal A8 in the precharge command cycle indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that the precharge target is both memory banks and its low level. Indicates that one of the memory banks indicated by A9 is to be precharged. The column address signal is defined by the levels of the terminals A0 to A7 in a read or write command cycle synchronized with the rising edge of the clock signal CLK. The column address defined in this way is used as a start address for burst access.

FIG. 1 shows a detailed configuration example of a main part of the SGRAM 330.

Clock enable signal CKE, chip select signal CS *, row address strobe signal RAS
*, Column address strobe signal CAS *, write enable signal WE *, and data mask signal DQM0
DQM3 is input. Among them, the clock enable signal CKE and the chip select signal CS
*, Command input is performed using signal input terminals such as a row address strobe signal RAS *, a column address strobe signal CAS *, a write enable signal WE *, and data mask signals DQM0 to DQM3.

CKE, CS *, RAS *, CAS *, W
When a command given by a combination of E *, DQM3 to DQM0 is given to the command decoder 301,
The command decoder 301 interprets the command and generates an operation control signal for each unit. The command decoder 301 includes, but is not limited to, a command decoding unit 11 for interpreting various input commands,
A block write operation setting command decoding unit 12 for interpreting the block write operation setting command.
According to the block write operation setting command interpretation by the block write operation setting command decoding unit 12, the block write column number control signal CNT3 and the input switching signal C
NT4 and an input switching signal CNT5 are generated. The block write operation setting command is an SMRS (special mode register set command), and various modes can be specified by a combination of the SMRS and the addresses A4 to A0. In the write data variable operation mode, input data can be changed for each block write command, and in the column mask variable operation mode, column mask data can be changed for each block write command.

The column decoder 203A includes a column decoder 26 for decoding an input column address,
A block write column number control circuit 27 for controlling the number of block write columns based on the block write column number control signal from the block write operation setting command decode unit 12;

Further, an input data control circuit 1 for controlling input data based on an input switching signal CNT4 from the block write operation setting command decode unit 12
3 and an input data control circuit 14 for controlling input data based on an input switching signal CNT5 from the block write operation setting command decode unit 12.

The operation will be described.

For example, by extending the function of the SMRS command used in the 8-Mbit SGRAM, the present invention can be implemented while maintaining the existing function.

The SMRS command enables selection of the write data variable mode and the column mask variable mode and the setting of the number of write columns by an address input simultaneously with the command.

FIG. 6 shows the timing of the write data variable mode, FIG. 7 shows the timing of the column mask variable mode, and FIG. 8 shows the relationship between the operation setting and the address setting.

First, the write data variable mode will be described.

As is apparent from FIG. 8, a specific bit of the address at the time of issuing the SMRS command, for example, A4 is "1",
When A3 is “1”, the write data variable mode is set. In the variable write data mode, every time a block write command BW is input, the input data of the block write is fetched, so that the content of the input data can be changed for each block write command BW (see FIG. 6). .

The SMRS command and the addresses A4 to A0 at that time are interpreted by the block write operation setting command decoding unit 12, so that the block write column number control signal CN for setting the write data variable mode is set.
T3, input switching signals CNT4 and CNT5 are formed, and thereby control of the number of write columns and input data are performed.

The number of write columns is controlled as follows.

Address A4 to SMRS command input
When A0 is “1,1,0,0,0”, the number of write columns in the write data variable mode is set to “2”. That is, each time the block write command BW is given, the block write of the input data D1 and D2 is performed simultaneously for two column addresses. Also, S
Addresses A4 to A0 at the time of inputting the MRS command are “1,
In the case of "1, 0, 0, 1", the number of write columns in the write data variable mode is set to "4", and each time the block write command BW is given, the input data D1, D
In the block write of 2, simultaneous writing is performed for 4 column addresses. Similarly, the combination of the addresses A4 to A0 at the time of inputting the SMRS command allows the number of write columns to be designated as 8, 16, 32, 64, 128, 256, and simultaneously writes data with the set number of columns. Is performed.

Each time a block write command BW is applied, input data is fetched and a block write is performed. Therefore, if the contents of the input data are changed each time the block write command BW is applied, the block write command differs. Block writing of input data can be performed. Also, the number n of columns required for simultaneous writing can be designated by the address N given at the same time as the SMRS command, so that the number of write columns can be changed every time the SMRS command is given.

In the variable write data mode, when the SMRS command is input, the column mask data M1 is fetched. Column mask data M
1 is used to mask a part of the column address when it is desired to avoid updating a part of the image data.

The data transfer path will be described.

The column mask data M1 contains the command A
This is performed when (SMRS) is input. That is, by the signal transmission path switching of the input data control circuit 13 based on the input switching signal CNT4, the column mask data M1 input via I / O0 to I / O31 is taken into the color register 213. Also, input data D1, D2
Is transmitted to the sense amplifier and column selection circuit 202A (or 202B) via the input data control circuits 13 and 14 when the block write command BW is executed, and the block writing of the input data D1 and D2 is enabled. At this time, the column mask data is stored in the color register 213.
From the column decoder 2 via the input data control circuit 14
03A (or 203B), the corresponding column address is masked.

Next, the column mask variable mode will be described.

As is apparent from FIG. 8, a specific bit of the address at the time of issuing the SMRS command, for example, A4 is "1".
When A3 is “0”, the column mask variable mode is set. In the column mask variable mode, the data D1 for block write is fetched when the SMRS command is input, and the column mask data is fetched every time the block write command BW is input. The contents of the column mask data can be changed (see FIG. 7).

The SMRS command and the addresses A4 to A0 at that time are interpreted by the block write operation setting command decoding unit 12, so that the block write column number control signal CN for setting the column mask variable mode.
T3, input switching signals CNT4 and CNT5 are formed, and thereby control of the number of write columns and control of column mask data are performed.

The control of the number of write columns is performed in the same manner as in the write data variable mode.

That is, when the addresses A4 to A0 at the time of inputting the SMRS command are “1, 0, 0, 0, 0”, the number of write columns in the column mask variable mode is
Set to “2”. That is, each time the block write command BW is given, the block write of the column mask data M1 and M2 is performed simultaneously for two column addresses. When the addresses A4 to A0 at the time of inputting the SMRS command are “1, 0, 0, 0, 1”, the number of write columns in the column mask variable mode is “4”.
And the block write of the column mask data M1 and M2 is performed simultaneously for four column addresses each time the block write command BW is given.
Similarly, addresses A4 to A0 when the SMRS command is input
, The number of write columns is 8, 16, 3
2, 64, 128, and 256 can be specified, and data is simultaneously written with the set number of columns.

The data transfer path will be described.

The write data is taken into the color register 213 via the input control circuit 13 when the SMRS command is executed. Then, the data is transmitted from the color register 213 to the sense amplifier and column selection circuit 202A (202B) via the input data control circuit 14, and written into the memory cell array 200A (or 200B).

On the other hand, the column mask data M1 and M2 are supplied to the column decoder 203A via the input data control circuit 13.
(Or 203B) to perform column masking of the column address.

By setting the addresses A4 to A0 input simultaneously with the SMRS command to “0, 0, 0, 00”,
The block write by the method shown in FIG. 5 can be performed without using the extended functions including the column mask variable mode and the write data variable mode.

In this embodiment, the speed of the block write can be increased as follows.

As shown in FIG. 9, when performing block write by the method 91 of FIG.
While it takes 40 ns (= tBWC + tSBW = 20 + 20) from the input of W to the input of the next block write command BW, the number of SMRS command inputs is reduced to 20 ns in the method 92 in FIG.
It is twice as fast.

According to the above example, the following functions and effects can be obtained.

(1) A command decoder 301 for decoding a block write command instructing simultaneous writing of data for a plurality of column addresses, and an external terminal each time a block write command is given based on the decoding result of the command decoder 301 (I / O0-I /
Input data control circuits 13 and 14 for taking in the data given to O31) as write data to the memory cell array.
The semiconductor memory device is provided with the configuration described above, so that the data applied to the external terminal can be fetched as write data to the memory cell array every time a block write command is applied, based on the decoding result of the decoding unit 12. Since the write data can be changed for each block write, various data such as complicated graphic data can be written at high speed.

(2) A block write operation setting command decoding unit 12 for decoding a column number setting command indicating the number of write columns in simultaneous writing of data for a plurality of column addresses, and a decoding result of the decoding unit 12 Since the semiconductor memory device is provided with the block write column number control circuit 202A for controlling the number of write columns, the number of write columns can be controlled based on the result of decoding by the decoding unit 12, so that simultaneous writing is possible. Since the number of columns can be changed easily, the data writing speed can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

In the above description, the invention made mainly by the inventor has been described in the field of application SGR
Although the case where the present invention is applied to AM has been described, the present invention is not limited to this, and can be widely applied to various semiconductor memory devices and data processing devices including the same.
In such a case, the data processing device does not necessarily need to include a display device such as a CRT display, and may include a unit for outputting data stored in the semiconductor storage device.

The present invention can be applied on condition that at least block writing is performed.

[0066]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, decoding means for decoding a block write command instructing simultaneous writing of data for a plurality of column addresses, and based on the decoding result of the decoding means, are applied to an external terminal every time a block write command is applied. And input data control means for taking in the read data as write data to the memory cell array to form a semiconductor memory device, so that the block write command is applied to an external terminal every time a block write command is applied based on the decoding result of the decoding means. The obtained data can be taken in as write data to the memory cell array, so that the write data can be changed for each block write, so that more various data can be written at high speed.

A decoding means for decoding a column number setting command designating the number of write columns in the simultaneous writing of data for a plurality of column addresses, and a column number for controlling the number of write columns based on the decoding result of the decode means By providing the control means and the semiconductor memory device, the number of write columns can be controlled based on the decoding result of the decode means, so that the number of simultaneously writable columns can be changed. The data writing speed can be improved.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor memory device according to the present invention;
FIG. 3 is a block diagram illustrating a configuration example of a main part of a GRAM.

FIG. 2 is a block diagram of an overall configuration example of a computer system including the above-described SGRAM.

FIG. 3 is a block diagram showing an overall configuration example of the SGRAM.

FIG. 4 is a main operation timing chart of the SGRAM.

FIG. 5 is a timing chart of a method to be compared with the block write method shown in FIG. 4;

FIG. 6 is a timing chart of a write data variable mode in the SGRAM.

FIG. 7 is a timing chart of a column mask variable mode in the SGRAM.

FIG. 8 is an explanatory diagram of operation setting and address setting in the SGRAM.

FIG. 9 is a timing chart for explaining the effect of the SGRAM.

[Explanation of symbols]

 11 Command Decode Unit 12 Block Write Operation Setting Command Decode Unit 13, 14 Input Data Control Circuit 26 Column Decode Unit 27 Block Write Column Number Control Circuit 200A, 200B Memory Cell Array 205 Column Address Buffer 206 Row Address Buffer 207 Column Address Counter 208 Refresh Counter 201A, 201B Row decoder 202A, 202B Sense amplifier and column selection circuit 203A, 203B Column decoder 210 Input unit 211 Output unit 212 Controller 213 Color register 300 Mode register 301 Command decoder 310 CPU 320 RAM 330 Image memory 340 ROM 350 Peripheral device control Unit 360 display control unit 370 CRT display 380 external description Device 390 timing scheme of the timing 92 Figure 6 method of the keyboard 91 5

Claims (4)

[Claims] An external terminal for taking in data from the outside, and a memory cell array capable of storing data input via the external terminal, enabling simultaneous writing of data for a plurality of column addresses. In the semiconductor memory device, decoding means for decoding a block write command instructing simultaneous writing of data for the plurality of column addresses, and the external terminal each time the block write command is given based on a decoding result of the decoding means Input data control means for taking in data given to the memory cell array as write data to the memory cell array. 2. An external terminal for taking in data from the outside, and a memory cell array capable of storing data input via the external terminal, enabling simultaneous writing of data for a plurality of column addresses. In the semiconductor memory device, decoding means for decoding a column number setting command designating the number of write columns in simultaneous writing of data for a plurality of column addresses, and a column for controlling the number of write columns based on a decoding result of the decode means And a number control means. 3. An external terminal for taking in data from the outside, and a memory cell array capable of storing data input via the external terminal, enabling simultaneous writing of data for a plurality of column addresses. In the semiconductor memory device, first decoding means for decoding a column number setting command indicating the number of write columns in simultaneous writing of data for a plurality of column addresses, and the number of write columns based on a decoding result of the first decode means A number-of-columns control means for controlling a plurality of column addresses;
Decoding means; and input data control means for taking in data given to the external terminal as write data to the memory cell array each time the block write command is given, based on a decoding result of the second decoding means, A semiconductor memory device comprising: 4. An image memory capable of storing image data,
4. A data processing device comprising: a unit capable of outputting data stored in the image memory; a data processing device including the semiconductor memory device according to claim 1 as the image memory.