JPH09251773A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device which can change reading quantity of block-write as required. SOLUTION: This device 100 is provided with block-write circuits 119, 120 in which a burst block-write operation mode and desired burst length are set to a mode register 106, a column address signal externally supplied is made an initial value, an initial value and a column selection signal equipment to burst length succeeding to the initial value are generated en bloc according to burst length information set to the mode register 106. And the same data can be supplied en bloc to data lines selected by plural column selection signals generated en bloc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device effective when applied to data processing of image data.

[0002]

2. Description of the Related Art A synchronous DRAM is used as a memory for efficiently processing a large amount of data such as image data.
(SDRAM). The SDRAM enables a high-speed memory access process for performing a read / write operation in synchronization with a clock signal and is effectively used when a huge amount of data is required to be processed. The column address drive system of the SDRAM is equipped with a column address counter that sequentially generates continuous column addresses based on one column address information supplied from the outside, and column address information for burst length is a column address counter. Sequentially generated and used for memory access. For example, in the case of a read operation, when the burst length is 1, only the read access corresponding to the column address information supplied from the outside is executed. When the burst length is 2, after the read access to the column address information (initial value) supplied from the outside is completed, the initial value is incremented by the column address counter while the selected state of the word line is maintained and generated. Read access is continuously executed according to the column address information. A synchronous graphic RAM (SGRAM) having a block write operation to further improve the access processing efficiency of such an SDRAM
There is. The memory area of the SGRAM is composed of a memory cell array composed of a plurality of DRAMs. The SGRAM has a normal SDRAM operation and a block write function that collectively generates a plurality of data line selection information (for example, column selection signals) that can be generated by using supplied column address information as an initial value. To be The block write function uses the supplied column address information as the initial value, sets the initial value and a plurality of data line selection information that continues to the initial value into the selected state at the same time, and writes the same data to the selected memory cell. This is a write operation in batch. SGR
As a publicly known document of AM, published by Hitachi Ltd. (19
Published on August 31, 1995) HM5283206Srie
s Manual Rev. 0.2 is mentioned.

[0003]

However, the conventional SGR
In the AM method, the number of data line selection information selected at the time of block write is set to a preset fixed value, and the number of data line selection information selected at the time of block write is changed as necessary in consideration of the write data amount. It was impossible to do. Also, an SGRAM having a plurality of memory banks
The block write processing is limited to one selected memory bank. In order to efficiently perform block writing according to the block write data amount, the present inventor variably sets the number of data line selection information items selected at the time of block writing, and a plurality of memory bank selection units to be block write targets. Found the need for.

An object of the present invention is to make it possible to change the number of pieces of data line selection information selected at the time of block writing at any time, to enable block write processing to a plurality of storage areas (memory banks), and to improve block write efficiency. Especially.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a semiconductor memory device having a function of inputting address information in synchronization with a clock signal, inputting / outputting data and control signals, and including a mode register for setting an access mode and a burst length of input / output data. In the first memory access mode designated by the access mode set in the mode register, the column address information supplied from the outside is used as the initial value and continues to the initial value while maintaining the selected state of the word line. In the second memory access mode designated by the access mode set in the mode register, the address generation means for sequentially generating address information for selecting the number of data lines designated by the burst length The column address information supplied from The number of data lines designated by the burst length to a data line selection information generating means for generating information for selecting collectively constituting the semiconductor memory device. The address generating means presets the column address signal output from the column address buffer, sequentially generates the number of column address signals designated by the burst length with the preset value as an initial value, and generates the generated address signal. A counter may be provided to the column address decoder. The data line selection information generation means collectively sets the number of column selection signals designated by the burst length to the selection level, and supplies the column selection signal to the column switch circuit, starting from the selection level column selection signal output from the column address decoder. It is possible to provide a collective selection logic circuit for When assuming a so-called multiple memory bank configuration, the semiconductor memory device includes a plurality of memory areas each having a large number of memory cells whose select terminals are coupled to word lines and data terminals to data lines. A row address decoder selects a word line and a column address decoder selects a data line with respect to a memory area, and a common address signal supply path to each row address decoder is provided. And generating a control signal for controlling activation of the column address decoder in units of the storage area, and
In the memory access mode, a control circuit for collectively activating the row address decoder and the column address decoder corresponding to a plurality of storage areas is provided.

An access mode and a burst length are set in the mode register of the semiconductor memory device. When the first memory access mode is set, the address generating means sets the supplied column address information as an initial value, and an address for selecting a number of data lines designated by a burst length continuous to the initial value. Information is generated sequentially.
In other words, the semiconductor memory device can continuously read or write using the initial value and the address information sequentially generated successively with the initial value while keeping the word line in the selected state. . Further, when the second memory access mode is set, the data line selection information generating means sets the supplied column address information as an initial value, and the initial value and the number of bursts consecutive to the initial value are specified. Information for collectively selecting the data lines is generated. In other words, the semiconductor memory device can perform the write operation by collectively selecting a plurality of data lines. In the semiconductor memory device having the plurality of storage areas, in the second memory access mode, row address decoders and column address decoders of the plurality of storage areas are collectively activated, so that the number specified by the burst length is increased. The efficiency of burst write processing is improved by batch selection of the data lines.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a synchronous graphic RAM (SG) which is an example of a semiconductor memory device of the present invention.
A block diagram of RAM) is shown. The SGRAM10
0 is not particularly limited, but a memory bank (B0) 101, (B1) 10 which is synonymous with a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix.
2 is provided. In each of the memory banks 101 and 102, the selection terminal of the dynamic memory cell is connected to the word line and the data input terminal is connected to the data line. Although not particularly limited, the SGRAM 100 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. SGRAM1
00 is the clock signal C as in the synchronous DRAM.
The operation control is performed according to the states of various control signals supplied in synchronization with LK. In particular, the SGRAM 100 includes a burst operation for sequentially generating a plurality of column address signals for reading or writing and a burst block write operation for collectively generating a plurality of column selection signals for writing. In order to realize the above burst operation, SGR
AM100 has a column address buffer (YAB) 1
07 and column address decoder (YD0) 109, (Y
D1) 110 and a column address counter (YA
C) 108 is provided. In order to realize the burst block write operation, the column address decoders 109 and 110 and the column switch (CS0) 111,
(CS1) 112 and block write circuit (BW
0) 119 and (BW1) 120 are provided.

First, access information for designating the burst operation, burst block write operation, etc. is supplied to the SGRAM 100 by address signals A0 to A9. The address signals A0 to A9 are transmitted to the mode register (M) via the row address buffer (XAB) 103.
R) 106. The access information set in the mode register 106 is the mode decoder (MD) 117.
Is supplied to the controller (CNT) 115 via.

FIG. 2 shows an example of access information set in the mode register 106. Mode register 1
06 is composed of a plurality of registers corresponding to the address signals A0 to A9 fetched through the row address buffer 103. All of the plurality of registers have the same configuration. Bits A0 to A9 of the mode register 106
, The information of the address signals A0 to A9 fetched through the row address buffer 103 is supplied in parallel. The instruction to set the access information to the mode register 106 is given by the control signal output from the controller 115 which receives the control signal in a predetermined state. As the information set in the mode register 106, for example, the burst length is set in bits A0 to A3. The burst length is not particularly limited, but is, for example, 1 to 8 and full page (256). The burst length is used as the number of step operations in the burst operation, and as the number of column selection signals collectively selected in the burst block write operation (full page is not applied in this embodiment).
The burst type is set in bit A4. The burst type indicates a memory bank access method for burst write and burst read operations, and is classified into a case where one memory bank is sequentially accessed and an interleave where two memory banks are sequentially accessed. The CAS latency is set by bits A5 to A6. The CAS latency is information indicating in which cycle of the clock signal CLK data output is performed after the column address strobe signal CAS * is asserted, and for example, 1 of the clock signal CLK,
Two or three cycles can be selected. A read / write operation mode is set in bits A8 and A9. As this operation mode, a burst operation for instructing burst read and burst write and a burst block write operation can be set. In the present embodiment, the bits A0 to A9 have a part where the information is not set, but it can be effectively used when the setting information is extended.

After the access information is set, the first address signals A0 to A9 are supplied in the address multiplexer format. The address signals A0 to A7 are supplied as row address information to the row address decoders (XD0) 104 and (XD1) 105 via the row address buffer 103, and are decoded therein to the respective row address decoders 104 and 105. Corresponding memory bank 1
A signal for selectively driving the word lines 01 and 102 is generated. Further, the address signals A8 and A9 are supplied as memory bank selection information to the controller 115 via the row address buffer 103. The controller 115 forms the control signals φ1 and φ2 according to the supplied address signals A8 and A9 to generate the column address decoder 1
09, 110 and row address decoders 104, 105
Control activation. For example, if the address signal A8 is'
When 0'and A9 are '0', the high-level control signal φ1 is formed, and the column address decoder 109 and the row address decoder 104 are activated. When the address signal A8 is "0" and A9 is "1", the high level control signal φ2 is generated, and the column address decoder 11
0 and the row address decoder 105 are activated. In this way, when one memory bank is selected, the burst operation or burst block write operation is performed.
When the address signal A8 is "1", the address signal A9
Irrespective of the above, the high level control signals φ1 and φ2 are formed, and the column address decoders 109 and 110 and the row address decoders 104 and 105 are activated. As described above, when all the memory banks 101 and 102 are selected, the burst block write operation is performed.

After the word line / memory block selection operation, the second address signals A0 to A7 are supplied in the address multiplexer format to select the data line. In the above burst operation mode, address signals A0 to A7
Is supplied as a column address signal to the column address counter 108 via the column address buffer 107. The column address counter 108 is provided with a burst counter that generates a column address signal and a burst end counter that limits the number of generated column address signals, and the column address signal supplied from the outside is set to the burst counter as an initial value. To be done. The burst length set in the mode register 106 is supplied from the controller 115 to the burst end counter as burst length information BB. The burst end counter is
It is preset by the burst length information BB, and outputs an underflow signal by down counting or decrementing operation. The burst counter increments the initial value and sequentially generates column address signals until the burst end counter underflows. The generated column address signal is applied to the column decoders 109 and 110 activated by the memory bank selection information.
The decoded signal passes through the block write circuits 119 and 120 and is supplied to the column switches 111 and 112 as a column selection signal to select the data line. The selected data line is the memory bank 10
1 and 102 are connected to a common data line CDL provided in common, and data writing to a selected memory cell and data reading from a memory cell can be performed. The input data is amplified by a write amplifier (not shown) via the activated input buffer (IB) 114, then transmitted to the common data line CDL, and written in the selected memory cell. The output data is transmitted to the common data line CDL, amplified by a main amplifier (not shown), and then output to the outside via the activated output buffer (OB) 113.
According to the burst operation, by supplying one column address signal from the outside, it is possible to sequentially generate the supplied column address signal and a predetermined number of column address signals consecutive thereto, and perform the read / write operation.

The SGRAM 100 includes a memory bank 101.
When the burst operation is being performed in memory bank 10
When the memory bank selection signal is supplied so as to specify 2, the operation of one memory bank 101 being executed is not affected and another memory bank 102 is not affected.
The word line selection operation is performed. For example, SGR
The AM 100 has means for internally holding data, address information, and control signals supplied from the outside, and particularly the address information and control signals are held for each memory bank. Therefore, the row address information can be supplied to a memory bank different from the memory bank to be accessed by the command being executed. By performing such access control, it is possible to quickly perform a burst operation to another memory bank after accessing the memory bank. Such an operation is called interleaving and can be set in the mode register 106 as access information. On the other hand, the operation of successively accessing one memory bank is called sequential and can be set in the mode register 106 as access information.

In the burst block write operation mode, the address signals A0 to A7 are supplied as column address signals to the activated column decoders 109 and 110 through the column address counter 108 through the column address buffer 107. Is decoded. The burst length set in the mode register 106 is used as the burst control signals BL1 to BL8 by the controller 11
5 to the block write circuits 119 and 120. The decode signal is the block write circuit 119,
At 120, the burst control signals BL1 to BL8 are collectively converted into a plurality of column selection signals.

FIG. 3 shows the block write circuit 119.
An example circuit diagram is shown. According to the figure, the block write circuit 119 is supplied with the decode signals DL0 to DL255 from the column address decoder 109. The block write circuit 119 has decode signals DL0 to DL2.
A column selection signal generation circuit 300 is provided corresponding to 55. Each column selection signal generation circuit 300 is provided with a clocked inverter unit for the burst length that can be set in the mode register 106. In this embodiment, since the maximum burst length is 8, the decode signals DL0-D0
The column selection signal generation circuit 300 corresponding to L248 is provided with clocked inverter units 301 to 308. The column selection signal generation circuit 300 corresponding to each of the decode signals DL249 to DL255 is sequentially provided with 7-1 clocked inverter units.

The clocked inverter section includes a P-channel MOS transistor 31 from the power supply voltage VCC side.
0, P channel type MOS transistor 311, N channel type MOS transistor 312, N channel type M
The OS transistor 313 and the power supply voltage VSS are connected in series in this order. For example, consider the column selection signal generation circuit 300 corresponding to the decode signal DL1. The decode signal DL1 is supplied to the clocked inverter units 301 to 301.
08 is commonly supplied to the gates of the respective P-channel type MOS transistors 310, inverted and coupled to the gates of the respective P-channel type MOS transistors 310, and commonly coupled to the gates of the respective N-channel type MOS transistors 313. Burst length information of 8 bits is supplied from the controller 115 to the gates of the P-channel type MOS transistor 311 and the N-channel type MOS transistor 312, respectively. Burst length information is burst control signal BL
1 to BL8, and BLn (hereinafter, n is an integer of 1 to 8) is coupled to the gate of the P-channel type MOS transistor 311 and the gate of the N-channel type MOS transistor 312 of the clocked inverter unit 30n. .
The clocked inverter unit 30n is a P-channel MO
The output at the connection point between the S-transistor 311 and the N-channel MOS transistor 312 is inverted and output, and the column selection signal Yn is generated. Generated column selection signal Y
n is connected to the same column selection signal Yn generated by another column selection signal generation circuit 300, and is supplied to the column switch 111 as one column selection signal Yn. The burst control signals (BL1, ..., BL8) are the same when the burst length information is 1 (1, 0, 0, 0, 0, 0, 0,
0) and the burst length information is 2 (1, 1, 0,
0, 0, 0, 0, 0), when the burst length information is 3 (1, 1, 1, 0, 0, 0, 0, 0), when the burst length information is 8 (1 1,1,1,1,1,1,
1, 1). For example, when “1” is set as the burst length information in the mode register 106 in the burst block write operation mode, the controller 11
Burst control signals (BL1, ..., BL)
8) is set to (1, 0, 0, 0, 0, 0, 0, 0) and is supplied to the column selection signal generation circuit 300. then,
When the decode signal DL1 is in the selected state (high level), only the output of the clocked inverter unit 301 is set to the high level, and only the column selection signal Y1 output from the clocked inverter unit 301 is in the selected state (high level). )become. When the decode signal DL1 is selected and the burst length information is 2, the burst control signal (B
L1, ..., BL8) is (1, 1, 0, 0, 0, 0, 0,
0), and only the column selection signals Y1 and Y2 output from the clocked inverter units 301 and 302 are in the selected state. As described above, the decode signals DL0 to DL25 selected by the column address signal supplied from the outside are selected.
5 and the burst control signals BL1 to BL8, a plurality of column selection signals Y0 to Y255 corresponding to the burst length can be collectively brought into a selected state. In the burst operation mode, burst control signals (BL1, ..., BL
8) is set to (1, 0, 0, 0, 0, 0, 0, 0) and is controlled so that only one column selection signal selected by the column address signal is selected.

FIG. 4 shows the block write circuit 119.
An example of the connection form of the internal column selection signal is shown. According to the figure, the column selection signals that can be output from the column selection signal generation circuit 300 corresponding to the decode signal DLx (x is an integer of 0 to 255) are Yx to Yx + 7.
However, the upper limit of the column selection signal formed is Y255. The column selection signals Y0 to Y255 output from each column selection signal generation circuit 300 are combined into the same column selection signal line to form one column selection signal. For example, the column selection signal Y2 that can be output from the column selection signal generation circuit 300 corresponding to the decode signal DL0 and the column selection signal generation circuit 30 that corresponds to the decode signal DL1.
The column selection signal Y2 that can be output from 0 and the column selection signal Y2 that can be output from the column selection signal generation circuit 300 corresponding to the decode signal DL2 are connected so as to be output as one column selection signal Y2. Therefore, the column selection signal Y2 is brought into a selected state by the output of one of the column selection signal generation circuits 300 corresponding to the decode signals Y0-2.

The operation of the SGRAM 100 is performed by the controller 115 identifying various operation commands supplied and instructing operation control according to the operation commands. The operation command is supplied to the controller 115 in synchronization with the clock signal CLK. The chip selection signal CS * (* indicates a row enable signal), the row address strobe signal RAS *, and the column address strobe signal CAS *. , Write enable signal WE *, and address information A0 to A9 supplied at that time. The operation command is divided into a precharge operation system, a row address drive system, and a column address drive system. By continuously supplying a plurality of operation commands to the controller 115 as necessary, a read operation and a write operation can be performed. To be done. SG in each operating state
When the CPU recognizes that the RAM 100 is in a predetermined state, the CPU can supply the SGRAM 100 with an operation command according to the state. The clock enable signal CKE is a signal that permits the input of the clock signal CLK when it is at a high level and prohibits it when it is at a low level.

Main operation command examples used in the SGRAM 100 will be described below.

(1) Precharge command (PRE):
The precharge command is an operation command that supplies a predetermined potential to the common data line CDL and the data line. This operation command includes a chip selection signal CS *, a row address strobe signal RAS *, and a write enable signal WE.
* Is low level, column address strobe signal CAS
When * is brought to a high level, it is recognized by the controller 115. The controller 115, which recognizes the precharge command, activates the discharge circuit provided for each data line by the column switches 111 and 112, for example, and controls the operation so that the data line has a predetermined potential. SGR
The state of AM100 is set to A (see FIG. 5) indicating the precharge state during the precharge, and the state after the precharge operation is the operation hold state in which only the chip selection signal CS * is enabled. Show B (Fig. 5
See).

(2) Mode register set command (M
RS): Mode register set command is SGRAM
The access information of 100 is set in the mode register 106. This operation command includes a chip selection signal CS *, a row address strobe signal RAS *, a column address strobe signal CAS *, and a write enable signal WE *.
When the low level is set to the high level, the controller 1
Recognized at 15. The controller 115 sets the address signals A0 to A9 supplied at that time in the mode register 106 via the row address buffer 103 in response to the mode register set command. SGRAM10
The state of 0 is set to C (see FIG. 5) indicating the information setting state while setting the read / write operation information in the mode register, and becomes B (see FIG. 5) indicating the post-setting operation suspension state.

(3) Row address drive system command (AC
TV): The row address drive system command is an operation command for selecting a word line and a memory bank. This operation command is recognized by the controller 115 when the chip selection signal CS * and the row address strobe signal RAS * are set to the low level, and the column address strobe signal CAS * and the write enable signal WE * are set to the high level. The controller 115 is responsive to the row address drive system command to supply the address signal A
0 to A7 are used as row address signals, and the row address decoder 10 is connected via the row address buffer 103.
Commonly supplied to Nos. 4 and 105. As a result, the word line is selected. At the same time, the address signals A8 and A9 are supplied, and the memory bank selecting operation is also performed as described above. The state of the SGRAM 100 becomes D (see FIG. 5) indicating the row address drive state during the word line / memory bank selection operation.

(4) Read command (READ): The read command is an operation command for selecting a data line, activating the output buffer 113, and instructing a read operation according to the access information set in the mode register 106. is there. When this read command is supplied, the burst operation is instructed to the mode register 106. In this operation command, the chip select signal CS * and the column address strobe signal CAS * are at low level, the row address strobe signal RAS * and the write enable signal W.
It is recognized by the controller 115 when E * is made high. Controller 115 that received the read command
Indicates a burst read set in the mode register 106. The controller 115 uses the address signals A0 to A7 supplied at that time as column address signals and supplies them to the column address counter 108 via the column address buffer 107. In the column address counter 108, using the supplied column address signal as an initial value, column address signals continuous with the initial value for the burst length are sequentially generated to select the data line, and CA
Data is output according to the S latency. When the burst type is interleaved, the generated column address signal is controlled to sequentially access the memory banks 101 and 102. The state of the SGRAM 100 is set to E (see FIG. 5) indicating the read state during the read operation, and becomes D (see FIG. 5) indicating the row address drive state after the read operation.

(5) Write command (WRITE): The write command is for selecting the data line and input buffer 114.
Is an operation command for instructing the write operation according to the access information set in the mode register 106. When this write command is supplied, the burst operation is set in the mode register 106. In this operation command, the chip select signal CS *, the column address strobe signal CAS *, and the write enable signal WE * are low level, and the row address strobe signal R
It is recognized by the controller 115 when AS * is brought to a high level. Controller 11 that received the write command
Reference numeral 5 indicates the burst write set in the mode register 106. The controller 115 uses the address signals A0 to A7 supplied at that time as column address signals and supplies them to the column address counter 108 via the column address buffer 107. When the burst write is instructed, the column address counter 108 sequentially generates the column address signals for the burst length according to the burst type by using the supplied column address signal as an initial value and selects the data line. , Data is input. The state of SGRAM100 is
It is set to F (see FIG. 5) indicating the write operation state during the write operation, and D indicating the row address drive state after the write operation.
(See FIG. 5).

(6) Block write command (BWRI
TE): The block write command is input buffer 11
4 is an activation command for instructing a burst block write operation according to the access information set in the mode register 106. When this block write command is supplied, the burst register write operation is set in the mode register 106. This operation command is recognized by the controller 115 when the chip select signal CS *, the column address strobe signal CAS *, and the write enable signal WE * are set to low level and the row address strobe signal RAS * is set to high level. Controller 11 that received the block write command
Reference numeral 5 designates a burst block write set in the mode register 106. The controller 115 uses the address signals A0 to A7 supplied at that time as column address signals and supplies them to the column address counter 108 via the column address buffer 107. When the burst block write is instructed, the column address counter 108 passes the supplied column address signal and supplies it to the column address decoders 109 and 110. The column address decoders 109 and 110 decode the decode signal DL0 according to the supplied column address signal.
~ DL255 forming block write circuits 119, 12
Supply 0. The block write circuits 119 and 110 are
By using the supplied decode selection signal as an initial value, continuous column selection signals for the burst length are collectively generated. Data lines corresponding to the generated plurality of column selection signals are connected to the common data line CDL. In this way, the same data is collectively supplied to the selected data line, and data is input. The state of the SGRAM 100 is set to F (see FIG. 5) indicating the block write state during the block write operation, and becomes D (see FIG. 5) indicating the row address drive state after the block write operation.

(7) Refresh command (REF):
The refresh command is an operation command for instructing self-refresh to refresh a predetermined area at a predetermined time interval. This operation command is recognized by the controller 115 when the write enable signal WE * is set to high level and other control signals are set to low level. The refresh is performed according to the operation logic of the refresh circuit (RfrC) 116. The state of the SGRAM 100 is the refresh state during the refresh operation, and G indicating the precharge operation state after the refresh operation (see FIG. 5).
Then, the state becomes B (see FIG. 5) showing the operation hold state after the precharge operation.

FIG. 5 shows an example of the command diagram of the SGRAM 100. After the power is turned on by setting the clock enable signal CKE to the high level, the SGRAM 100 is supplied with the precharge command, the state is set to A, and the precharge operation is performed. After precharging, the state becomes B and the operation is suspended. State B is chip select signal CS *
Only set to low level. When the mode register set command is recognized in the state B, the state is set to C and the mode register 106 is set.
Access information is set. After setting the information, the state returns to B. Then, by generating a row address drive command, the state becomes D, a row address signal is supplied, and a word line and a memory bank are selected. When a read command is generated while the state is D, the state becomes E, a column address signal is supplied, and continuous column address signals are sequentially generated by the column address counter 108 according to the burst length, and burst read is performed. . The state after burst read is set to D. When a write command or burst block write is generated when the state is D, the state becomes F, the column address signal is supplied, and the burst write or burst block write is performed according to the access information set in the mode register 106. Done. The state after the burst write or burst block write operation is D
become. During the burst operation, if the interleave operation is instructed, one of the memory banks is in the state E
At this time, the state of the other memory bank can be set to D, and for example, a write command or a block write command can be supplied immediately after the read operation. Therefore, burst write or burst block write can be executed without returning to the state D. Similarly in the state F, the read command can be supplied immediately after the write operation and the read can be executed. Further, the write command can be supplied to the other memory bank immediately after the write operation, or the read command can be supplied to the other memory bank immediately after the read operation. State D, E,
When the precharge command is recognized at F, the state becomes A, the precharge operation is performed, and the state shifts to state B. This precharge command is used when ending the row address driving operation. When a refresh command is generated when the state is B, the state shifts to G and self refresh is performed. After refreshing, the state shifts to A, is precharged and returns to B. In state B, the SGRAM 100 is powered down by setting the clock enable signal CKE to the low level.

FIG. 6 shows an example time chart of the burst block write of this embodiment. For example, when the state is B, the mode register set command (MR
S) is supplied and access information is set in the mode register. The address signal A8 supplied at this time is'
1'and A9 are set to '0', and the SGRAM 100 is instructed to perform the burst block write operation. When the mode register setting operation is completed, the state of the SGRAM 100 becomes B.
And the operation is suspended. A row address drive command (ACTV) is generated in synchronization with the rising edge of the clock signal CLK of TIME3, and the address signals A0 to A7 supplied at that time are used as row address signals to drive the selected word line. . Further, the column address decoder and the row address decoder activated by the address signals A8 and A9 supplied at the same time are selected. In the figure, the address signal A8 is "0", A9.
Is set to "0", and only the column address decoder 109 and the row address decoder 104 of the memory bank 101 are activated. Next, in the state of state D, the block write command (BWRITE) is supplied in synchronization with the rising of the clock signal CLK4, and the address signals A0 to A7 supplied at that time are set as the initial value of the column address signal. Based on the supplied initial value of the column address, the column selection signals for the burst length set in the mode register 106 are collectively written in the block write circuit 1.
The selected state is set at 19 and the same data is supplied to the selected data line to perform writing. Memory bank 10
When performing the burst block write operation for both 1 and 102, in the burst block operation, TIME
The address signal A8 supplied at 3 o'clock may be set to "1". In this way, by supplying the one-block write command, it is possible to collectively supply the write data to the data lines selected by the plurality of column selection signals.

According to the above embodiment, the following operational effects can be obtained.

(1) The user sets the burst block write operation mode and the predetermined burst length by using the mode register set command, if necessary.
Can be set to The burst block write operation is instructed when the block write command is recognized by the controller 115. The burst block write executes a batch write operation of the same data by setting a plurality of column selection signals corresponding to the burst length set in the mode register 106 to a selected state. The burst length can be changed at any time by using the mode register set command during memory access operation, and the write amount of burst block write is also changed according to the burst length.

(2) Further, the block write processing efficiency is improved by making both the memory banks 101 and 102 the targets of the burst block write by the memory bank selection information.

(3) As described above, the SGRAM 100 of the present invention which enables a burst block write process by designating a predetermined burst length and a memory bank, performs a large-scale batch write process of enormous identical data such as image processing data. For example, it is effective for batch erasing data and writing the same data in a rectangular area of the memory.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited thereto and various modifications can be made without departing from the gist thereof. Needless to say.

For example, in this embodiment, the block write is executed for all the memory cells coupled to the bit line selected by the continuous address signal, but a part of the selected bit line is mask-controlled. By providing a circuit, it is possible to set a write-protected area in the block write area. Further, in the present embodiment, an example in which there are two memory banks has been described, but the present invention is not limited to this. For example, in the case of a memory block including eight memory banks, burst block write can be performed by selecting one to eight memory banks.

Further, in the burst block write of the present embodiment, the selection range of the burst length is 1 to 8, but it is not particularly limited and the set bit of the burst length is increased and a predetermined hardware mechanism is provided. Allows a burst length greater than 8 to be set. Further, in the present embodiment, the burst block write is realized by using the block write circuit that collectively brings a plurality of column selection signals into the selected state, but the circuit configuration is not limited to the above embodiment. Further, the column address decoder may include logic for selecting the number of data lines designated by the burst length.

Further, in this embodiment, the decode signal DL0
-Column selection signal generation circuit 300 corresponding to DL255
The number of clocked inverter units is
Column selection signal generation circuit 30 corresponding to 0 to DL248
0 for each of 8 decode signals DL249-DL255
In the column selection signal generation circuit 300 corresponding to
Although the number is one, the number is not limited. For example, if the number of clocked inverter units of all column selection signal generation circuits 300 corresponding to the decode signals DL0 to DL255 is 8,
The column select signal generating circuit 300 corresponding to the decode signal DL249 has the formable outputs of the column select signals Y249 to Y255 and Y0, and similarly, finally, the column select signal generating circuit 300 corresponding to the decode signal DL255. Column select signal Y25
5, Y0 to 6, and the upper column select signal generation circuit 3
If the output of 00 is connected so as to be fed back to the output of the lower side, burst block writing for up to 8 columns can be performed for any address signal.

In the above description, the SGR, which is the field of application behind the invention made mainly by the present inventor, is the background.
Although the AM has been described as an example, the present invention is not limited to this and can be applied to at least a block-writable semiconductor memory device.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the second memory access mode, the burst line write in which the number of data lines designated by the burst length set in the mode register can be collectively selected and the same data is supplied to the selected data lines. The operation of can be realized. Burst length is
It can be changed according to the setting contents of the mode register,
The write data amount by burst block write can be changed accordingly. Further, the burst block write can be collectively executed on a plurality of storage areas. In this way, the amount of data for batch writing can be changed as necessary, and the efficiency of block writing can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a semiconductor memory device of the present invention.

FIG. 2 is an explanatory diagram of a mode register of the SGRAM of this embodiment.

FIG. 3 is an example circuit diagram of a block write circuit of the present embodiment.

FIG. 4 is an explanatory diagram of a block write circuit of this embodiment.

FIG. 5 is an explanatory diagram of a command diagram of the SGRAM of this embodiment.

FIG. 6 is a time chart of burst block write according to the present embodiment.

[Explanation of symbols]

 100 SGRAM 101 Memory Bank 102 Memory Bank 103 Row Address Buffer 104 Row Address Decoder 105 Row Address Decoder 106 Mode Register 107 Column Address Buffer 108 Column Address Counter 109 Column Address Decoder 110 Column Address Decoder 111 Column Switch 112 Column Switch 113 Output Buffer 114 Input Buffer 115 Controller 116 Refresh circuit 117 Mode decoder 119 Block write circuit 120 Block write circuit

Claims (4)

[Claims] 1. A function of inputting address information in synchronization with a clock signal and inputting / outputting data and control signals,
In a semiconductor memory device including an access mode and a mode register in which a burst length of input / output data is set, a word line selection state is maintained in a first memory access mode designated by the access mode set in the mode register. Address generating means for sequentially generating address information for selecting the number of data lines specified by the burst length so as to be continuous with the initial value, using the column address information supplied from the outside as the initial value. In the second memory access mode designated by the access mode set in the register, the column address information supplied from the outside is used as an initial value, and the number of data lines designated by the burst length is set so as to be continuous with the initial value. Data line selection information that generates information for selecting all at once The semiconductor memory device characterized by comprising a means. 2. The address generating means presets the column address signal output from the column address buffer, and sequentially generates the number of column address signals designated by the burst length with the preset value as an initial value,
2. The semiconductor memory device according to claim 1, further comprising a counter that supplies the generated address signal to a column address decoder. 3. The data line selection information generation means collectively sets the number of column selection signals designated by the burst length to the selection level, starting from the column selection signal of the selection level output from the column address decoder. 3. The semiconductor memory device according to claim 2, further comprising a batch selection logic circuit supplied to the column switch circuit. 4. A plurality of storage areas having a large number of memory cells whose selection terminals are connected to word lines and whose data terminals are connected to the data lines. A row address decoder selects a word line for each storage area. Then, the column address decoder selects a data line, the address signal supply path to each of the row address decoders is made common, and the address signal supply path to each of the column address decoders is also made common. And generating a control signal for controlling activation of the row address decoder and the column address decoder in units of the storage area, and in the second memory access mode,
4. The semiconductor memory device according to claim 3, further comprising a control circuit for collectively activating the row address decoder and the column address decoder corresponding to a plurality of storage areas.