JP2001285030A - Fir filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FIR filter which can reduce power consumption. SOLUTION: This FIR filter has data register circuits 10, arranged as many as an oversampling number at an input signal hold part 1, a data shift control part 31 selects one of data register circuits 10 arranged in parallel in the order at each timing point to hold and shift input signal data, and an input signal selection part 4 inputs the input signal data shifted and outputted from the data register circuits arranged in parallel at each sample timing point in the order in matching with the timing of the shifting by the data register circuits 10 under the control of a data selection control part 32 and taps and outputs the data to a product sum arithmetic part 2. Consequently, the operation rate of the data register circuit 10 can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FIR (Finite Imp
More particularly, the present invention relates to an FIR digital filter capable of reducing power consumption.

[0002]

2. Description of the Related Art In wireless communication such as a portable telephone, a digital filter is generally used as a demodulation circuit. The digital filter has an infinite impulse response (IIR) in which a feedback loop for reusing the output value in the filter is provided inside the filter, and the output is repeated indefinitely.
e) They are classified into filters and FIR filters that have no feedback loop and have a finite number of outputs.

[0003] The FIR filter is also called a transversal filter. The FIR filter sequentially outputs an input signal to a later-stage delay element while delaying and holding the input signal by a cascade-connected delay element. By tapping the output signal, multiplying the output signal by the filter coefficient and adding the result, the correlation operation at each timing can be sequentially performed.

[0004] In particular, FIR filters have advantages such as high-speed operation and stable output because of no feedback loop, and are widely used in various wireless communications. Code Division Multiple A
A matched filter used for demodulation or synchronization capture in a ccess (CDMA) system is a type of FIR filter.

[0005] The input signal to the FIR filter is once converted into a digital signal and sampled at a sampling frequency exceeding the bandwidth (frequency bandwidth) of the signal. Here, if the timing of the chip of the received signal is known accurately, sampling may be performed at the same frequency as the chip rate, but in general, the exact timing of the chip is often not known. If a sampling frequency close to the chip rate is used, image interference generated by sampling may not be completely removed. Therefore, to avoid these problems, sample the signal several times faster than the chip rate,
An oversampling method of calculating a correlation value from a plurality of sampling results for one chip is used.

In the conventional FIR filter, the number of oversampling is four times and the number of data register stages is eight.
The configuration of the IR filter will be described with reference to FIG.
FIG. 6 is a configuration block diagram of a conventional FIR filter. As shown in FIG. 6, the conventional FIR filter includes an input signal holding unit 1 ″ and a product-sum operation unit 2.

The components of the conventional FIR filter will be described. The input signal holding unit 1 ″ captures an input signal (SIGIN in the figure) generated at each sample timing,
Eight data registers (REG1 to REG1) connected in cascade
REG 8), the input signal data held at the previous timing is shifted to the next stage data register, and the held input signal is tapped from the data register 10 for each oversampling number.

Each data register 10 receives and shifts the oversample clock MCLK at each sample timing. In the FIR filter of FIG. 6, since the number of data register stages is 8 and the number of oversampling is 4, the input signals held in the fourth and eighth data registers 10, ie, REG4 and REG8, are tapped at each sample timing. Will do.

The sum-of-products operation unit 2 applies a filter coefficient accumulation unit (TREG1, TREG in the figure) to input signal data tapped from the input signal holding unit 1 ″ at sample timing.
REG2) 21 are multiplied by filter coefficients accumulated in a multiplier (MULT1 and MULT2 in the figure) 22 and the result of the multiplication is added by an adder (ADD in the figure) 23, and finally an FIR filter Is output. Note that the filter coefficient storage units TREG1, TRE
G2 stores the filter coefficients T1 and T2. In FIG. 6, in order to cope with demodulation of various input signal data, the filter coefficient storage unit 21 may store a plurality of filter coefficients and select a filter coefficient corresponding to the input signal data.

Next, the operation of the conventional FIR filter will be described with reference to FIG. In the operation of the conventional FIR filter, a newly generated input signal SIGIN is input to the input signal holding unit 1 at sample timing intervals. When the oversample clock MCLK is input to each data register 10 of the input signal holding unit 1 ″, the input signal SIGIN is stored in the first data register REG1, and the previous sample timing is stored in the other data registers REG2 to REG8. Thus, the input signal data held in the preceding data register is shifted to the next data register.

The input signal data is shifted in each data register 10, and the data registers for each oversampling number, ie, REG4 and RE
The input signal data held in G8 is tapped and output at each sample timing.

An input signal holding unit 1 is provided for each sample timing.
The input signal data tapped from the data registers REG4 and REG8 is multiplied by the multiplier MULT of the product-sum operation unit 2.
1 and MULT2.

The input signal data input to the multiplier MULT1 is multiplied by the filter coefficient T1 stored in the filter coefficient storage unit TREG1, and the result of the multiplication is expressed as MO.
UT1 is output, and the input signal data similarly input to multiplier MULT2 is multiplied by filter coefficient T2 stored in filter coefficient storage unit TREG2, and MOUT2 is output as a result of the multiplication. The multiplication results MOUT1 and MOUT2 are input to the adder 23, where the addition is performed.
An output FOUT of the FIR filter is output as a result of the addition. In the FIR filter of FIG. 6, the above-described operation is repeatedly performed at each sample timing.

FIG. 7 is a time chart of the input signal data held in each data register of the input signal holding unit 1 ″ and the output result of the product-sum operation in the product-sum operation unit 2 in the conventional FIR filter. In the time chart of FIG. 7, the oversample clock cycle, that is, the sample timing is set as a unit time, and t1, t2,
…. In addition, each input signal data uses a combination of the period and phase information of the input signal as an identifier. Since the oversampling number is 4,
In FIG. 7, the phases in one symbol are DA, DB, and D, respectively.
The periods C and DD represent the oversampling period by numerical values, and a combination of these information is used as an identifier of the input signal. In FIG. 7, since the input signals of the eighth to eleventh oversampling periods are to be described, the identifiers are DA08, DB08, DC08, D08.
, DC11 and DD11.

SIGIN is an input signal newly generated at each oversampling timing.
1, MOUT2 are multipliers MULT1, MULT of the product-sum operation unit 2.
FOUT represents the output result of ULT2, and FOUT represents the addition output result of MOUT1 and MOUT2 in the adder ADD.
In FIG. 7, the output of FOUT at time tn is FO.
UT (tn).

The input signal data held in each data register is shifted to the next data register in synchronization with the oversample clock MCLK, that is, at the sample timing. For example, the input signal data DA10 newly generated at the sample timing t1 is shifted and held in the first data register REG1 at the next timing t2. Thereafter, the input signal data DA10 is shifted to the data register of the next stage as REG2, REG3,... Every time the sample timing elapses. This is the same for other input signal data.

The input signal data held in the fourth and eighth data registers REG4 and REG8 are tapped and output to the product-sum operation unit 2 at each sample timing. A product-sum operation of coefficients is performed. The output results MOUT1 and MOUT2 of the respective multipliers are added in the adder ADD, and the output result of the adder ADD becomes the output FOUT of the FIR filter.

When the FIR filter is used in a transmitter, transmission data of a digital signal is suppressed to a desired frequency band. When the FIR filter is used in a receiver, received data of a digital signal is restored to a desired frequency band. Becomes possible.

[0019]

However, in the conventional FIR filter, the input signal data is input and held in all data registers in synchronization with the oversampling clock. Since the number of data registers must be increased, power consumption in the data registers increases.

The present invention has been made in view of the above circumstances, and has as its object to provide an FIR filter capable of reducing power consumption.

[0021]

According to the present invention, there is provided an FIR filter in which a data register circuit is arranged in parallel with an oversampling number in an input signal holding means, and a data holding control section is provided. Then, one of the data register circuits arranged in parallel is sequentially selected for each sample timing, and the data register circuit is caused to hold and shift the input signal data. , The input signal data shifted and output from the data register circuits arranged in parallel at each sample timing in accordance with the shift timing in the data register circuit, is sequentially taken in, and tapped output to the product-sum operation means,
The operation rate of each data register circuit can be reduced, and power consumption can be reduced.

According to the present invention, in the FIR filter, the storage means holds the input signal data for the number of oversampling in accordance with the selected address, and sequentially tap-outputs the input signal data in accordance with the selected address, thereby controlling the memory. The means selects the address in the storage means in order to hold the input signal data for the number of oversamplings at each sampling timing and sequentially output the taps, and replaces a part of the FIR filter with a storage means such as a RAM. Thereby, the circuit scale can be reduced.

According to the present invention, in the FIR filter, in the input signal holding means, the data register circuits are arranged in parallel with the number of oversamplings, and further the data register circuits connected thereto are arranged in parallel. The data register circuit arranged in parallel or the data register circuit connected thereto is sequentially selected at each sample timing, and the data register circuit is caused to hold and shift the input signal data. The input signal data shifted from the data register circuit arranged in parallel at each sample timing or the data register circuit connected thereto in synchronization with the shift timing in the data register circuit under the control of the data register circuit is sampled in units of parallel arrangement. Sequentially take at an integer multiple of speed The tap output is output to the product-sum operation means, and the product-sum operation means adds all the results of the product-sum operation in units of parallel arrangement and outputs a correlation, thereby reducing the operation rate of each data register circuit. The power consumption can be reduced, and the circuit scale of the product-sum operation means can be reduced.

According to the present invention, in the above-mentioned FIR filter, in the input signal holding means, a plurality of data register circuits are arranged in a plurality of columns of data register circuit groups, and the data register circuit groups are arranged in parallel with the number of oversampling. The data holding control unit sequentially selects the data register circuits in a plurality of columns corresponding to the data register circuit group arranged in parallel for each sample timing, and causes the data register circuit to hold and shift the input signal data. Under the control of the data selection output control unit, the input signal selection means selects a plurality of columns corresponding to a data register circuit group arranged in parallel at each sample timing in accordance with the shift timing in the data register circuit. Input signal data shifted from the data register circuit In a certain column unit, the data is sequentially taken in at an integer multiple of the sampling rate, and the output is tapped to the product-sum operation means. The product-sum operation means adds all the results of the product-sum operation in the corresponding column units and performs correlation. Output
The operation rate of each data register circuit can be reduced, the power consumption can be reduced, and the circuit scale of the product-sum operation means can be reduced.

[0025]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

The FIR filter according to the present invention sequentially selects one of input signal holding means in which data register circuits are arranged in parallel with the number of oversamplings and data register circuits arranged in parallel for each sample timing.
A data holding control unit for causing the data register circuit to hold and shift the input signal data, and a data register arranged in parallel for each sample timing in accordance with the shift timing in the data register circuit under the control of the data selection output control unit Input signal data sequentially shifted from the circuit, and input signal selection means for tap output to the product-sum operation means, which can reduce the operation rate of each data register circuit and reduce power consumption. is there.

Further, the FIR filter according to the present invention holds the input signal data for the number of oversampling according to the selected address, and sequentially tap-outputs the input signal data according to the selected address;
Memory control means for holding input signal data for the number of oversamplings at each sample timing and for sequentially outputting taps; and a memory control means for selecting an address in a storage means. The circuit scale can be reduced by substituting into.

The input signal holding means in the claims corresponds to the input signal holding units 1 and 5 in FIGS. 1 and 3, the product-sum operation means corresponds to the product-sum operation unit 2, and the input signal control means corresponds to the input signal control means. The input signal selection means corresponds to the input signal selection section 4, the data register circuit corresponds to the data register 10, the data holding control section corresponds to the data shift control section 31, and the data selection output section corresponds to the signal control section 3. The control unit corresponds to the data selection control unit 32.

The configuration of the FIR filter (first FIR filter) according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of an FIR filter (first FIR filter) according to the first embodiment of the present invention. Here, the oversampling number is 4
The case where the number of data register stages is eight will be described.
However, in practice, it can be freely set without being bound by this numerical value.

As shown in FIG. 1, the first FIR filter includes an input signal holding unit 1, a product-sum operation unit 2, an input signal control unit 3, and an input signal selection unit 4. As features of the present invention, the input signal control unit 3 and the input signal selection unit 4 are provided, and the input signal holding unit 1 is different from the conventional input signal holding unit 1 in the internal configuration.

Each part of the first FIR filter will be described. The input signal holding unit 1 includes data registers REG1 to REG1.
REG4 are arranged in parallel, and data registers REG5 to REG5 are cascaded to the data registers.
REG8 is arranged in parallel. Data register RE
G1 to REG4 hold the input signal SIGIN generated at each sample timing in accordance with the shift clock SCLK from the input signal control unit 3, and shift the input signal data previously held in the data registers REG1 to REG4 to shift output. Is done. Data register REG5
REG8 hold the input signal data shifted from the data registers REG1 to REG4 in accordance with the shift clock.

The input signal control section 3 includes a data shift control section (SFTCONT) 31 and a data selection output control section (D
SELCONT) 32. The data shift control unit 31 determines a data register of the input signal holding unit 1 for newly inputting input signal data at each sample timing, and generates any of shift clocks SCLK1 to SCLK4 for the determined data register.
Output. The data register REG to which the shift clock SCLK is input holds the input signal data.

The data selection output control unit 32 instructs the input signal selection unit 4 to read the input signal data from the data register 10 in order to tap-output the input signal data at each sample timing.
ELORD and an input signal read command). The operations of the data shift control unit 31 and the data selection output control unit 32 are performed independently.

An oversample clock (MCLK) is input to the data shift controller 31 and the data selection output controller 32 at each sample timing. When the oversample clock is input, the data shift control unit 31 and the data selection output control unit 32 perform the above-described operations.

The input signal selection section 4 is composed of two data selection output sections (DSEL1, DSEL2) 41, based on an input signal read command output from the data output selection control section 32 of the input signal control section 3. Data register 1
The input signal data from 0 is selected and read and output to the product-sum operation unit 2.

In the data selection output section 41, DSEL
1 is a data register REG1 to RE of the input signal holding unit 1.
One of G4, DSEL2 is a data register R
The input signal data held in any one of the data registers EG5 to REG8 is selected and read in accordance with the input signal read command.
Output to the product-sum operation unit 2 as SELOUT2.

The number of data selection output units 41 to be installed is as follows.
This corresponds to the number of input signal data that is tapped and output from the input signal holding unit 1 at each sample timing. In FIG. 1, the number of data register stages is eight and the number of oversampling is four times, so that the number of input signal data tapped and output at each sample timing, that is, the data selection output unit 41
Will be two.

The sum-of-products calculation unit 2 applies filter coefficient accumulation units (TREG1, TREG2) 2 to the input signal data output from the input signal selection unit 4 at the sample timing.
1 is multiplied by the filter coefficient stored in the multiplier (M
ULT1, MULT2) 22, the result of the multiplication is added by an adder (ADD) 23, and the output FOUT of the FIR filter is output. In FIG. 1, the filter coefficient accumulation unit 21 may accumulate a plurality of filter coefficients and select a filter coefficient corresponding to the input signal in order to cope with demodulation of various input signals.

Next, referring to FIG. 1, the first FI of the present invention will be described.
The operation of the R filter will be described. In the operation of the first FIR filter, first, a new input signal SIGIN is generated at each sample timing, and is input to the data registers REG1 to REG4 of the input signal holding unit 1. On the other hand, every time the oversample clock MCLK is input to the input signal control unit 3, the data shift control unit 31 selects the data register of the input signal holding unit 1 that holds the new input signal SIGIN by using the shift clocks SCLK1 to SCLK4. This is performed using The data register REG to which the shift clock SCLK is input holds the input signal data. The data selection output control unit 32 selects the data register REG of the input signal holding unit 1 for outputting the input signal data by an input signal read command.

For example, when the shift clock SCLK1 is output from the data shift control unit 31, the data register REG1 of the input signal holding unit 1 holds the input signal SIGIN, and furthermore, the data register R1 is cascaded.
The input signal data held in the data register REG1 is shifted to EG5. Other data register RE
Similar operations are performed for G2 to G4.

In order to select a data register for outputting the input signal data, the data selection output control unit 32
Outputs an input signal read command to the input signal selection unit 4. The data selection output unit 41 reads the input signal data from the selected data register of the input signal holding unit 1 based on the input signal read command, and outputs the input signal data to the product-sum operation unit 2. That is, in the input signal selection unit 4, the data selection output units DSEL1 and DSEL2 are respectively REG1 to REG1.
The input signal data is read from any of the data registers REG4 and REG5 to REG8,
Output to

Data selection output section DS of input signal selection section 4
Input signal data SE output from EL1 and DSEL2
LOUT1 and SELOUT2 are input to multipliers MULT1 and MULT2 of the product-sum operation unit 2, respectively. The multiplier MULT1 multiplies the input signal data by the filter coefficient T1 stored in the filter coefficient storage unit TREG1, and outputs a multiplication result MOUT1. The multiplier MULT2 multiplies the input signal data by the filter coefficient T2 stored in the filter coefficient storage unit TREG2, and outputs a multiplication result MOUT2. The output results MOUT1 and MOUT2 of the respective multipliers are added in the adder 23, and the output FIR of the FIR filter is output.
OUT is output.

FIG. 2 is a time chart of the input signal data held in each data register of the input signal holding unit 1 and the shift clock output from the input signal control unit 3 in the first FIR filter of the present invention. . In the time chart of FIG. 2, the oversampling timing is set as a unit time, and the identifier of the input signal data is expressed in the same manner as in the time chart of FIG.

SELOUT1 and SELOUT2 are data selection and output sections DSEL1 and DSEL1 of the input signal selection section 4, respectively.
The input signal data output from DSEL2, SC
LK1 to LK4 indicate shift clocks output from the data shift control unit 31 of the input signal control unit 3. still,
The multiplication results MOUT1 and MOUT2 of the multipliers MULT1 and MULT2 of the product-sum operation unit 2 and the output F of the FIR filter
OUT is the same as that of the conventional FIR filter, and the description is omitted.

In the first FIR filter of the present invention, input signal data whose phase is a DA series is stored in the data register RE.
G1 and REG5. Similarly, the phase is DB,
Input signal data of DC and DD series are data registers REG2 and REG6, REG3 and REG, respectively.
7, REG4 and REG8.

In the timing chart of FIG. 2, an input signal SIG newly generated for each sample timing is shown.
Focusing on IN, at sample timing t1, an input signal whose identifier is DA10, which is a DA sequence, is generated. Thereafter, at t2, the DB sequence, at t3, the DC sequence, t
In step 4, an input signal of a DD sequence is generated, and this rotation is repeated every four sample timings.

As described above, the sample timing t1
And new input signal data DA1 whose phase is a DA sequence.
Since 0 has been generated, the data shift controller 31 of the input signal controller 3 outputs the shift clock SCLK1 to the data registers REG1 and REG5 at the rising edge of the sample timing t2.

The data register REG1 to which the shift clock SCLK1 has been input receives and holds the input signal data DA10 newly generated at the previous timing t1, and shifts the input signal data DA09 which has been held so far to the data register REG5. . The data register REG5 to which the shift clock SCLK1 has been input receives and holds the input signal data DA09 shifted from the data register REG1.

At the next sample timing t2, the phase becomes D
Since the new input signal data DB10 of the B series has been generated, the data shift control unit 31 outputs the shift clock SCLK2 to the data registers REG2 and REG6 at the rising edge of the sample timing t3.

The data registers REG2 and REG6 to which the shift clock SCLK2 has been input become the data registers REG1 and REG6 at the rising edge of the sample timing t3.
As in the case of G5, input signal data input and holding operations are performed.

Thereafter, each time new input signal data of the DC series and the DD series is generated, the data shift control unit 31 sets the shift clock SC at the next sample timing.
LK3 and SCLK4 are generated, and the data register REG is generated.
3, REG7 and the data registers REG4, REG8 perform input signal data input and hold operations.

On the other hand, the data selection output control section 32 of the input signal control section 3 issues an input signal read command to read input signal data from the data register REG1 at the sample timing t1.
An input signal read command for reading input signal data from the data register REG5 is output to the data selection output unit DSEL2 of the input signal selection unit 4 to SEL1.

The data selection output units DSEL1 and DSEL2 to which the input signal read command is input read the input signal data DA10 and DA09 held in the data registers REG1 and REG5, respectively, and the SELOUT1 and SELOUT2 are respectively input to the product-sum operation unit 2. Output as

Thereafter, the data selection output control unit 32 determines that the DB sequence at t2, the DC sequence at t3, t4
Outputs an input signal read command to read the input signal data of the DD series to the data selection output unit 41. That is, the input signal reading instruction is performed at the sample timing t2.
Then, from the data registers REG2 and REG6, from REG3 and REG7 at t3, and from REG4 and REG8 at t4.
From the input signal data. The data selection output control unit 32 thereafter repeats this rotation every four sample timings.

The data selection output unit 41 reads input signal data from the corresponding data register 10 based on the input input signal read command, and outputs the read input signal data as SELOUT1 and SELOUT2 to the product-sum operation unit 2. I do. Input signal data SELOUT1,
SELOUT2 is the newly generated input signal SIGI
Compared to the phase with N, each signal is delayed by one symbol and two symbols.

In the FIR filter of FIG. 1, each data register 10 of the input signal holding unit 1 updates the input signal data every four sample timings. On the other hand, in the conventional FIR filter, each data register is updated at each sampling timing.
Therefore, the first filter of the present invention has an operation rate reduced to 1/4 times as compared with the conventional FIR filter, and has reduced power consumption.

Further, the first FIR filter can be applied even if the number of oversampling and the number of data registers are changed. That is, in the first FIR filter, the number of data registers in the input signal holding unit 1 is set to be equal to the number of oversampling in accordance with the number of oversampling and the number of data registers. , The number of multipliers 22 and the number of filter coefficient storage units 21 of the product-sum operation unit 2 may be set as many as the number of data registers included in each data register group.

According to the first FIR filter, the data register groups for holding the input signal data sampled in the input signal holding unit 1 are arranged in parallel for the number of oversampling, and the sampled input signal data is sequentially selected. Data registers, and the data registers are read out sequentially from the data registers at the timing of oversampling, and the product-sum operation is performed. Therefore, the operation rate of each data register can be reduced, and the entire FIR filter can be reduced. Thus, there is an effect that power consumption can be reduced and an FIR filter with stable operation can be realized.

In the first FIR filter, the input signal holding unit 1, the input signal control unit 3, and the input signal selection unit 4
This can be easily realized by installing. That is, the first FIR filter can be realized by adding a circuit of a slightly larger scale to the conventional FIR filter, so that the labor and cost for installing the circuit can be reduced.

Next, another type of FIR filter (second FIR filter) using the technique of the first FIR filter of the present invention will be described. First, referring to FIG.
The configuration of the FIR filter will be described in comparison with the first FIR filter. FIG. 3 is a configuration block diagram of the second FIR filter. The FIR filter of FIG. 3 is described as having the same function as the first FIR filter, that is, the number of oversampling is four times and the number of data register stages is eight. Can be set. Parts having the same configuration as in FIG. 1 are described with the same reference numerals.

As shown in FIG. 3, the second FIR filter includes an input signal holding unit 5, a product-sum operation unit 2, and a memory control unit (MEMCONT) 61. The input signal holding unit 5 includes a RAM (Random Access Memory: DT).
RAM1, DTRAM2) 51.

The RAM 51 realizes the functions of the input signal holding unit 1, the input signal selection unit 4, and the data selection output control unit 32 of the input signal control unit 3 in the first FIR filter. That is, the RAM 51 fetches the newly generated input signal SIGIN, holds the input signal SIGIN at a specific address, shifts the input signal data held so far to another address, and selects input signal data to be output at each sample timing. Output. First FIR
The function of each data register of the filter can be realized by storing and holding at a specific address in the RAM 51.

Of the RAM 51, DTRAM1 is a data register REG1-RE in the first FIR filter.
Equipped with G4 function, SE at each sample timing
LOUT1 is output. Also, the DTRAM2 is provided with the first F
Data registers REG5 to REG in IR filter
8 functions, and SEL for each sample timing
OUT2 is output. The input signal data shifted from the DTRAM1 is input to the DTRAM2.

The memory control unit (MEMCONT) 61
This corresponds to the data shift controller 31 of the first FIR filter, and when the oversample clock MCLK is input,
It is determined which input signal data is to be input to which RAM 51, and an instruction to input and hold the input signal data (hereinafter, input signal holding instruction) is issued to DTRAM1, DTRAM1.
The data is input to both RAMs 51 of the RAM 2.

The product-sum operation unit 2 is the same as the first FIR filter, and the input signal data SELOUT1 and SELOUT output from the input signal selection unit 4 at the sample timing.
2, the filter coefficient storage units (TREG1, TRE
G2) Multiplication with the filter coefficients stored in 21 is performed using multipliers (MULT1, MULT2) 22. The result of the multiplication is added by an adder (ADD) 23, and FI
It outputs the output FOUT of the R filter. Second
The configuration of the product-sum operation unit 2 in the FIR filter of
This is similar to the FIR filter.

Next, the operation of the second FIR filter will be described with reference to FIG. In the operation of the second FIR filter, first, a new input signal SIGIN is taken into the input signal holding unit 5 at sample timing intervals. On the other hand, in the memory control unit 61, the oversample clock MC
Each time LK is input, an address on the RAM 51 of the input signal holding unit 5 is set for each of the DTRAM1 and DTRAM2 in order to input and hold input signal data.

When an address on the RAM 51 for holding input signal data is set in the memory control section 61, the memory control section 61 outputs a command to the DTRAM1 and DTRAM2 to write the input signal data to the set address. I do.

When a write command for input signal data is input, a new input signal SIGIN is input and held at the set address in the DTRAM 1, and the input signal data held so far is shifted to the DTRAM 2,
In the DTRAM2, input signal data shifted from the DTRAM1 is input to a set address and held. The time chart of the input signal data is REG1 to REG4
Is the address on the DTRAM1 and REG5 to REG8 are D
2 except that it is replaced with an address on TRAM2.
As shown in the time chart of FIG.

The DTRAM 1 of the input signal holding unit 5
Each time the oversample clock MCLK is input, the DTRAM 2 selects an address where input signal data to be output to the product-sum operation unit 2 is held. When the address is selected, the DTRAM1 and DTRAM2 output the input signal data held at the selected address to the product-sum operation unit 2 as SELOUT1 and SELOUT2, respectively. The input signal data and timing output as SELOUT1 and SELOUT2 are as shown in the time chart of FIG.

The input signal data SELOUT1 and SELOUT2 output from the input signal holding unit 5 are input to multipliers MULT1 and MULT2 of the product-sum operation unit 2, respectively. Hereinafter, the operation of the product-sum operation in the product-sum operation unit 2 is performed in the same manner as in the first FIR filter. That is, when the product-sum operation is performed in the product-sum operation unit 2, the output FOUT of the FIR filter is finally output. Similarly to the case of the first FIR filter, the filter coefficient accumulation unit 21 accumulates a plurality of filter coefficients and selects a filter coefficient corresponding to the input signal in order to correspond to demodulation of various input signals. It may be.

In the second FIR filter, the first FIR filter
In addition to the effect of the filter, the input signal holding unit 1, the input signal selection unit 4, and the data selection output control unit 32 of the input signal control unit 3 in the first FIR filter of FIG.
By replacing with M51, there is an effect that the circuit scale can be reduced as compared with the first FIR filter, and an inexpensive FIR filter can be realized.

For example, as a method of realizing the first FIR filter, Flip Fl
A method of configuring the input signal holding unit 1 of the first FIR filter by using a plurality of storage elements such as op and combining a plurality of these storage elements is conceivable. On the other hand, in the second FIR filter, for example, ASIC (Application Specific Integrator)
ted Circuit), FPGA (Field Programmable Gate A)
By using (rray) or the like, an integrated circuit according to the application can be configured, and the RAM 51 can be easily realized.
Further, in the RAM 51, since the functions of the input signal selection unit 4 and the data selection output control unit 32 of the input signal control unit 3 in the first FIR filter can be realized, the area occupied by these circuits in the first FIR filter is reduced. And further downsizing can be achieved.

Next, FIR filters according to the third and fourth embodiments of the present invention will be described. Third aspect of the present invention
The FIR filter has an input signal holding means for arranging data register circuits in parallel with the number of oversamplings and further arranging the data register circuits connected thereto in parallel, and a data register circuit arranged in parallel for each sample timing or connected to it. A data holding circuit that sequentially selects the data register circuits to perform and holds and shifts the input signal data to the data register circuit, and samples the data register circuit according to the shift timing in the data register circuit under the control of the data selection output control unit. Input signal data shifted and output from the data register circuit arranged in parallel at each timing or the data register circuit connected thereto is sequentially taken in as a unit of parallel arrangement at an integral multiple of sampling speed, and the tap output to the product-sum operation means Input signal selection means And a product-sum operation means for adding all the results of the product-sum operation in units of data and outputting a correlation, thereby reducing the operation rate of each data register circuit, reducing power consumption, and further performing the product-sum operation. The circuit scale in the means can be reduced.

A fourth FIR filter according to the present invention is the above-mentioned FIR filter, wherein a plurality of data register circuits are formed into a plurality of columns of data register circuit groups.
Input signal holding means for arranging the data register circuit group in parallel with the number of oversampling, and sequentially selecting data register circuits of a plurality of columns in correspondence with the data register circuit group arranged in parallel for each sample timing; A data holding control unit for causing the data register circuit to hold and shift the input signal data, and a data register arranged in parallel for each sample timing in accordance with the shift timing in the data register circuit under the control of the data selection output control unit An input for sequentially taking in input signal data shifted from a plurality of columns of data register circuits corresponding to a circuit group at a speed of an integral multiple of sampling in units of columns having a corresponding relationship, and tap-outputting the product-sum operation means The result of the product-sum operation for each corresponding column is It is those having a product sum calculating means for correlation output by adding, to reduce the operating rate of the data register circuit each individual, the power consumption can be reduced, in which the circuit scale can be reduced in the further product-sum operation unit.

The input signal holding means in the claims corresponds to the input signal holding section 1 in FIGS. 4 and 5, the product-sum operation means corresponds to the product-sum operation section 2, and the input signal control means corresponds to the input signal control section. The input signal selection means corresponds to the input signal selection section 4, the data register circuit corresponds to the data register 10, the data holding control section corresponds to the data shift control section 31, and the data selection output control section corresponds to the input signal selection section 4. Corresponds to the data selection control unit 32.

FIG. 4 is a configuration block diagram of an FIR filter (third FIR filter) according to the third embodiment of the present invention. Hereinafter, the configuration of the third FIR filter in the case where the number of oversampling is four and the number of data register stages is eight will be described with reference to FIG. FIG.
Portions having the same configuration as those described above will be described with the same reference numerals. For convenience of explanation, the number of oversampling is four times and the number of data register stages is eight in FIG. 4, but the number can be freely set without being limited to the actual values.

As shown in FIG. 4, the third FIR filter includes an input signal holding unit 1 ', a product-sum operation unit 2', an input signal control unit 3, and an input signal selection unit 4. I have. The features of the present invention are that the data register group is folded back in the input signal holding unit 1 'and that the data register MREG holding the output result of the multiplier is provided in the product-sum operation unit 2'.

The components of the third FIR filter will be described. The input signal holding unit 1 'has eight data registers R
EG <b> 1 to REG <b> 8 are arranged in parallel, and input signal data held in each data register REG is output to the input signal selection unit 4. The input signal SIGIN is input to the data registers REG1 to REG4, and the input signal data shifted from the data registers REG is held in the data registers REG5 to REG8. The shift clock SCLK1 is applied to the data registers REG1 and REG5, and the shift clock SCLK2 is applied to the data registers REG2 and REG6.
The shift clock SCLK3 is the data register REG3,
7, the shift clock SCLK4 is stored in the data register RE.
G4, 8 are input.

More specifically, the data register 10 of the input signal holding section 1 ′ has a data register group for holding the input signal of the leading phase DA series in one symbol.
1. REG5 is installed in the lower stage and is cascaded. A data register group for holding other DB, DC, and DD series input signals is provided in the same manner. In the input signal holding section 1 ', any one of the input signal data held in the data register is tapped and output in REG1 to REG8 at twice the speed of the sample timing.

The input signal control unit 3 has a data shift control unit (SFTCONT) 3 like the first FIR filter.
1 and data selection output control unit (DSELCONT) 32
It is composed of The data shift control unit 31 determines the data register 10 of the input signal holding unit 1 'for newly inputting the input signal data at each sampling timing according to the oversampling clock MCLK, and shift clocks SCLK1 to SCLK1 to the determined data register.
One of SCLK4 is generated and output.

The data selection output control section 32 determines the data register 10 for tapping out the input signal data at twice the sampling timing, and reads the input signal read command (DSELORD) from the determined data register 10.
Is output to the input signal selection unit 4. Data shift control unit 3
1 and the operation of the data selection output control unit 32 are performed independently of each other. Further, the oversampling clock MCLK is input to the data shift control unit 31 and the data selection output control unit 32 at each sample timing, and accordingly, the data shift control unit 31 and the data selection output control unit 3
2 perform the operations described above.

The input signal selection section 4 comprises a data selection output section (DSEL) 41. The input signal selection section 4 reads the input signal data based on the DSELORD output from the data output selection control section 32 of the input signal control section 3, and performs a product-sum operation. Output to the operation unit 2 '. The data selection output unit 41 reads out any of the input signal data of the data registers REG1 to REG8 of the input signal holding unit 1 'at twice the speed of the sample timing, and outputs the data as SELOUT to the product-sum operation unit 2'.

The sum-of-products operation unit 2 'applies a filter coefficient storage unit (TREG) 21 to the input signal data output from the input signal selection unit 4 at twice the sampling timing.
Multiplication with the filter coefficient stored in the multiplier (MU)
LT) 22 and the result of the multiplication is added to an adder (AD
D) Addition by 23 and the output FOU of the FIR filter
Output T.

In the product-sum operation unit 2 ′, the multiplication result MOUT performed by the multiplier 22 is input to and held in two multiplication output data registers (MREG 1, MREG 2) 24.
The multiplication output data registers are cascaded, and when a new multiplication result is input in a state where data is held in MREG1, the new multiplication result becomes MREG1.
, And the data held by MREG1 is shifted to MREG2. When the data is held in the multiplication output data registers MREG1 and MREG2, the adder 23 adds the respective data, and
The output FOUT of the IR filter is output. In FIG. 4, the filter coefficient accumulating unit 21 may accumulate a plurality of filter coefficients and select a filter coefficient corresponding to the input signal in order to cope with demodulation of various input signals.

Next, the operation of the third FIR filter will be described with reference to FIG. In the operation of the third FIR filter, first, the input signal SIGIN is taken into the input signal holding unit 1 'at each sample timing. On the other hand, in the input signal control unit 3, similarly to the first FIR filter, every time the oversample clock MCLK is input, the data shift control unit 31 generates a new input signal SIGIN.
Is selected in the input signal holding unit 1 'holding the data register.

When the data register holding input signal SIGIN is selected in data shift control section 31,
The data shift control unit 31 generates and outputs a data shift clock SCLK to the selected data register. In the data register to which the data shift clock SCLK has been input, the input signal SIGIN is held, and the input signal data held at the previous timing is shifted and held in the next cascaded data register. The relationship between the shift clock output to each data register and the data register that holds input signal data in synchronization with each shift clock is the same as in the case of the first FIR filter, and a description thereof will be omitted.

When the input signal control section 3 receives the oversample clock MCLK, the data selection output control section 32 selects a data register of the input signal holding section 1 'for outputting input signal data. In the data selection output control unit 32, the oversample clock MC
When LK is input, first, an input signal holding data register group for outputting the input signal data is selected, and among the selected input signal holding data registers, the upper data register is set as the data register for outputting the input signal data. select. When the data register is selected, the data selection output control section 32 outputs DSELORD to the input signal selection section 4 so as to acquire the input signal data of the selected upper data register.

For example, when the input signal data having the phase of the DA series is to be output, the data selection / output control unit 32 selects the data register group in which the data registers REG1 and REG5 are installed, and then selects the data register REG1 in the upper stage. And outputs DSELORD to the input signal selection unit 4 to obtain the input signal data of the data register REG1. The data selection output control unit 32 performs the above-described series of operations at twice the speed of the sample timing.

DSELORD output from the data selection output control section 32 is input to the data selection output section DSEL41 of the input signal selection section 4. Data selection output section DSE
L41 is an input signal read command DSELO that has been input.
Based on the RD, the input signal data is read from the data register of the selected input signal holding unit 1 'and output to the product-sum operation unit 2'.

Data selection output section DS of input signal selection section 4
Input signal data SELOUT output from EL41
Is input to the multiplier MULT22 of the product-sum operation unit 2 '. In the multiplier MULT, the input signal data and the filter coefficient T stored in the filter coefficient storage unit TREG21 are stored.
, And a multiplication result MOUT is output. The multiplication result MOUT is stored in the multiplication output data register MREG1.
Is entered and held.

Next, the data selection output control unit 32 of the input signal control unit 3 outputs the data signal of the lower stage as a data register for outputting the input signal data from the input signal data register group of the input signal holding unit 1 'which has already been selected. Select a register. When the data register is selected, the data selection output control unit 32 outputs DSELORD to the input signal selection unit 4 so as to acquire the input signal data of the selected lower data register. The data selection output control unit 32 performs the above-described series of operations at twice the speed of the sample timing.

The DSELORD output from the data selection output control section 32 is input to the data selection output section DSEL41 of the input signal selection section 4. Data selection output section DSE
L41 is an input signal read command DSELO that has been input.
Based on RD, the input signal data is read from the data register of the selected input signal holding unit 1 and output to the product-sum operation unit 2 '.

Data selection output section DS of input signal selection section 4
Input signal data SELOUT output from EL41
Is input to the multiplier 22 of the product-sum operation unit 2 'and then multiplied by the filter coefficient, as in the case of the upper data register.

The multiplication result MOUT in the multiplier 22 is input to the multiplication output data register MREG1.
Input signal data read from the upper data register held in REG1 is shifted to cascaded MREG2. When the input signal data is input to the multiplication output data registers MREG1 and MREG2, the adder 23 adds the multiplication output data held in both, and outputs the output FOUT of the FIR filter. In the third FIR filter, the relationship between the sample timing and the input signal data held in each data register of the input signal holding unit 1 'is the same as that shown in the time chart of FIG.

In the third FIR filter, in the first half of each sample timing, the input is sequentially performed from the upper data register in the data register group holding the same phase input signal, and in the second half, the input is sequentially performed from the lower data register in the data register group. Input signal data S read by the signal selection unit 4
Output as ELOUT.

That is, SELOUT is a time series in which SELOUT1 is output in the first half of each sample timing and SELOUT2 is output in the second half when the expression in the time chart of FIG. 2 is used. Therefore, in the product-sum operation unit 2, the number of the multipliers 22 for multiplying the input signal data by the filter coefficients is only one.

FIG. 5 is a configuration diagram of an FIR filter in which N data registers are provided in each data register group of the input signal holding unit 1 'in order to adapt the third FIR filter to a large number of samplings. . Hereinafter, the configuration and operation of the FIR filter shown in FIG. 5 in the case where the number of oversampling is four will be described, focusing on differences from the third FIR filter. In FIG. 5, the shift clocks SCLK1 to SCLK4 output from the data shift control unit 31 of the input signal control unit 3 are actually input to all the data registers of each data register group. Omitted.

The FIR filter (fourth FIR filter) shown in FIG.
In each of the data register groups of the input signal holding unit 1 ', N data registers 10 are cascade-connected, and each of the data register groups is folded back into two stages of an upper stage and a lower stage by N / 2. Here, the number of stages n of the data register group is
Any number may be used as long as it is a divisor of the number N of data registers.
Since the speed of reading the input signal data of the input signal selection unit 4 becomes multiple of the number of stages of the sample timing, it is desirable to set the speed in consideration of the processing capability of the input signal selection unit 4.

Further, since the input signal data is read from the upper and lower data registers of one data register group at twice the speed of each sample timing, the data selection output section 41 of the input signal selection section 4 outputs N / N. Two are installed. Similarly, N / 2 multipliers 22 and filter coefficient storage units 21 of the product-sum operation unit 2 'are provided. That is, in the fourth FIR filter, when the data register group of the input signal holding unit 1 'is folded over the number of stages n, the data selection output unit 41 of the input signal selection unit 4, the multiplier 22 of the product-sum operation unit 2, and The filter coefficient accumulating section 21 has N /
It is necessary to install n units.

The output result of each multiplier 22 of the product-sum operation unit 2 'is hierarchically added by a plurality of adders 25.
The final addition result is input to and held in the multiplication output data register 24. When the result of multiplication of the data register group of the input signal holding unit 1 'with the upper and lower filter coefficients is input to the multiplication output data register 24, the adder 23 outputs the multiplication output data held in the multiplication output data register 24. And outputs the output FOUT of the FIR filter.

As described above, according to the fourth FIR filter, the sample timing is divided by the number of stages of the data register group, and the input signal data is sequentially switched and read from the input signal holding unit 1 'at the divided time. Since the number of multipliers in the product-sum operation unit can be reduced, there is an effect that the circuit scale of the product-sum operation unit can be reduced, and the circuit size of the entire FIR filter can be reduced.

Further, the fourth FIR filter is provided with a second FIR filter.
It is possible to replace with a configuration like an IR filter. That is, the functions of the input signal holding unit 1 ', the input signal selection unit 4, and the data selection output control unit 32 of the input signal control unit 3 in the fourth FIR filter are stored in the RAM, and the data shift control unit 31 of the input signal control unit 3 is used. Can be replaced with a memory control unit to implement a fourth FIR filter.

However, in the fourth FIR filter,
If the number of data registers provided in each data register group is N and the number of stages is n, N / n RAMs are provided, and the RAM reads addresses at which input signal data is read at n times the sampling timing. It is necessary to select and output the input signal data to the product-sum operation unit 2 '.

Using the configuration of the second FIR filter, the fourth
By realizing the FIR filter described above, the circuit scale of the product-sum operation unit 2 'can be reduced, and the scale of the circuit part replaced by the RAM can be reduced. Therefore, the circuit scale of the entire FIR filter can be reduced and the cost can be reduced. There is an effect that an FIR filter can be realized.

[0105]

According to the present invention, in the input signal holding means, the data register circuits are arranged in parallel with the number of oversamplings, and in the data holding control section, one of the data register circuits arranged in parallel for each sample timing is provided. Are sequentially selected to cause the data register circuit to hold and shift the input signal data, and the input signal selection means controls the data selection output control unit to adjust the shift timing in the data register circuit at each sample timing. Since the input signal data shifted and output from the data register circuits arranged in parallel is taken in order and the FIR filter is tapped and output to the product-sum operation means, the operation rate of each data register circuit is reduced and the power consumption is reduced. There is an effect that can be.

According to the present invention, the storage means holds the input signal data for the number of oversampling in accordance with the selected address, and sequentially tap-outputs the input signal data in accordance with the selected address. In order to hold the input signal data for the number of oversamplings at each timing and output the taps sequentially,
Since the FIR filter is used to select an address in the storage unit, the circuit scale can be reduced by replacing a part of the FIR filter with a storage unit such as a RAM.

According to the present invention, in the input signal holding means, the data register circuits are arranged in parallel with the number of oversamplings, and the data register circuits connected thereto are also arranged in parallel.
The data holding control unit sequentially selects a data register circuit arranged in parallel at each sample timing or a data register circuit connected thereto, causes the data register circuit to hold and shift the input signal data, and Under the control of the data selection output control unit, the input signal data shifted and output from the data register circuit arranged in parallel at each sample timing or the data register circuit connected thereto in parallel with the shift timing in the data register circuit is controlled in parallel. FIs that sequentially take in the arrangement unit at an integer multiple of the sampling speed and tap output to the product-sum operation unit, and the product-sum operation unit adds all the results of the product-sum operation in the unit of the parallel arrangement and outputs a correlation.
Since the R filter is used, the operation rate of each data register circuit can be reduced, and the power consumption can be reduced.
Further, there is an effect that the circuit scale in the product-sum operation means can be reduced.

According to the present invention, in the input signal holding means, a plurality of data register circuits are arranged in a plurality of columns of data register circuit groups, and the data register circuit groups are arranged in parallel with an oversampling number. Input signal selecting means for sequentially selecting a plurality of columns of data register circuits corresponding to a data register circuit group arranged in parallel for each sample timing, causing the data register circuit to hold and shift input signal data, In accordance with the control from the data selection output control unit, the shift output is performed from the data register circuits in a plurality of columns corresponding to the data register circuit group arranged in parallel at each sample timing in accordance with the shift timing in the data register circuit. Integers for sampling input signal data into corresponding column units , And tap output to the product-sum operation means. The product-sum operation means employs the above-mentioned FIR filter which adds all the results of the product-sum operation in the corresponding column units and outputs a correlation. This has the effect of reducing the operating rate of each data register circuit, reducing power consumption, and further reducing the circuit scale of the product-sum operation means.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first FIR filter of the present invention.

FIG. 2 is a time chart of input signal data held in each data register of an input signal holding unit of a first FIR filter and a shift clock output from an input signal control unit;

FIG. 3 is a configuration diagram of a second FIR filter of the present invention.

FIG. 4 is a configuration diagram of a third FIR filter of the present invention.

FIG. 5 is a configuration diagram of an FIR filter in a case where the third FIR filter is adapted to a large number of samplings.

FIG. 6 is a configuration diagram of a conventional FIR filter.

FIG. 7 is a time chart of the input signal data held in each data register of the input signal holding unit and the output result of the product-sum operation in the product-sum operation unit in the conventional FIR filter.

[Explanation of symbols]

1, 5: input signal holding unit, 2: product-sum operation unit, 3: input signal control unit, 4: input signal selection unit, 10: data register, 21: filter coefficient storage unit, 22: multiplier, 23, 25 ... Adder, 24 ... Multiplication output data register, 31 ... Data shift control unit, 32 ... Data selection control unit, 41 ... Data selection output unit, 51 ... RA
M, 61: Memory control unit

Claims (4)

[Claims] An input signal holding means for holding a sampling result obtained by sampling a signal to be demodulated as input signal data, sequentially shifting to a next stage, and arranging a data register circuit for tap output in parallel with an oversampling number. A filter-coefficient storage unit that stores filter coefficients, performs a product-sum operation of the input signal data tapped from the data register circuit and the filter coefficient, and performs a correlation output; An input signal selecting unit that inputs input signal data output from the tap and outputs the input signal data to the product-sum operation unit; a data holding control unit that controls the data register circuit to hold and shift the input signal data; The input signal selecting means for shifting the input signal data output from the data register circuit And a data selection output control unit for performing a tap output to the product-sum operation unit, and an input signal control unit, wherein the data holding control unit is configured to control the data arranged in parallel for each sample timing. Select the register circuit sequentially,
A data holding control unit that causes the data register circuit to hold and shift the input signal data, wherein the input signal selecting unit adjusts the shift timing in the data register circuit under the control of the data selection output control unit. An input signal selecting means for sequentially taking in input signal data shifted from the data register circuits arranged in parallel at each of the sample timings and tap-outputting the input signal data to the product-sum operation means. 2. A storage means for holding a sampling result obtained by sampling a signal to be demodulated as input signal data for the number of oversampling in accordance with an address selected, and for sequentially tap-outputting input signal data in accordance with the selected address, and a filter. A filter coefficient accumulating unit for accumulating coefficients, performing a product-sum operation of the input signal data tapped from the storage means and the filter coefficient, and performing a correlation output; and In order to hold data for the number of oversampling and output taps sequentially,
An FIR filter comprising: a memory control unit for selecting an address in the storage unit. 3. A sampling result obtained by sampling a signal to be demodulated is held as input signal data, sequentially shifted to the next stage, and data register circuits for tap output are arranged in parallel with the number of oversampling, and furthermore, Input signal holding means for arranging the data register circuit connected to the arranged data register circuit in parallel; and a filter coefficient accumulating section for accumulating a filter coefficient, wherein the input signal data tapped from the data register circuit and the filter The product-sum operation with the coefficient is performed at an integer multiple of the sampling speed, and the product-sum operation means for performing a correlation output; and input signal data tapped from the data register circuit are input and output to the product-sum operation means Input signal selection means, and holding and shifting the input signal data in the data register circuit A data holding control unit for performing control for causing the input signal data to be shifted and output from the data register circuit to the input signal selection unit, and a data selection and output control unit for performing control to cause the product-sum operation unit to output a tap. The data holding control unit sequentially selects the data register circuit arranged in parallel or the data register circuit connected to the data register circuit arranged in parallel at each sample timing. A data holding control unit that causes the data register circuit to execute holding and shifting of the input signal data; and wherein the input signal selecting unit controls a shift timing in the data register circuit under the control of the data selection output control unit. The data arranged in parallel at each sample timing according to Input signal data shifted and output from the register circuit or the data register circuit connected to the data register circuit arranged in parallel with the parallel arrangement unit at an integer multiple of the sampling speed in sequence; FIR, wherein the product-sum operation means is a product-sum operation means for adding all the results of the product-sum operation in units of the parallel arrangement and for outputting a correlation output. filter. 4. An input signal holding means comprising: a plurality of data register circuits for sequentially shifting input signal data as a plurality of columns of data register circuit groups; and an input signal for arranging the data register circuit groups in parallel with an oversampling number. Holding means, wherein the data holding control section sequentially selects the data register circuits in a plurality of columns corresponding to the data register circuit group arranged in parallel for each sample timing, and inputs the input data to the data register circuit. A data holding control unit that executes holding and shifting of the signal data, wherein the input signal selecting unit is controlled in parallel with the shift timing in the data register circuit by the control of the data selection output control unit for each of the sample timings. Data of a plurality of columns corresponding to the placed data register circuit group Input signal data which is shifted and output from the register circuit, sequentially takes in the corresponding column unit at an integer multiple of the sampling speed, and tap-outputs to the product-sum operation means; 4. The FIR filter according to claim 3, wherein the calculating means is a sum-of-products calculating means for adding all the results of the sum-of-products operation for each of the columns having the corresponding relationship and for outputting a correlation output.