JPH0837444A - Oversampling digital filter - Google Patents

Abstract

PURPOSE:To simplify the hardware by decreasing the member of adders. CONSTITUTION:Input data are given sequentially to a shift register 20-0 in a timing of rising of a clock signal CLK. The shift register 20 shifts a signal by one bit in the rising timing of the clock signal CLK. Each shift register 20-i provides an output of an output signal SHR1 to a coefficient selection circuit 21-i. The coefficient selection circuit 21-i selects the inverse of K4*1+(k-1) when the output signal SHR1 is at '1' in the timing of each of timing signals Tk (k=1, 2, 3, 4) and selects a K4*i+(k-1) when the output signal SHR1 is at '0' and provides its value F1 to an adder 22. The adder 22 is operated by a clock signal whose frequency is four times that of the clock signal CLK and adds tap coefficients F1 outputted from the coefficient selection circuit 21-i in an oversample frequency being four times that of the clock signal CLK and provides an output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a code division multiple access (CDMA (Code
(division multiple access)) method, and relates to an oversampled digital filter in the case of transmitting a baseband signal.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference 1; Nikkei Electronics, 1993-10, "Spread spectrum technology", P253-265 Reference 2: Yamayuki Yukiji, "Digital mobile communication system", 1
993-2, Tokyo Denki University Press, P24-31 The CDMA system used in the mobile communication digital modulator is, as described in the above-mentioned reference 1, a convolutional encoding process of 10 kHz encoded voice data. , Interleaving, scrambling, and spread spectrum processing are performed sequentially, then band components other than 1.25 MHz are cut by using an oversampled digital baseband filter that is n times the input data, D / A conversion processing and high frequency modulation are performed. It is something to send. With this CDMA system, the same band can be shared by a plurality of communication channels, and the number of users that can be accommodated in mobile communication can be increased. As described in the above-mentioned reference 2, the role of the oversampling digital filter is that the modulated baseband signal has a too wide band and side lobes are generated. It is to remove high frequency components through a filter. The filter for this purpose needs to prevent the signal from being output to the adjacent band, and thus requires a digital FIR (Finete Impulse Response) filter having a steep characteristic.

FIG. 2 shows an example of a conventional digital FIR filter having a 4-fold oversampling structure, and is a block diagram of a digital FIR filter having 48 tap coefficients. In this digital FIR filter, input data
When X (n) is input, it has an interpolator 1 that creates four pieces of data X (n), 0,0,0 with a clock CLK2 that is four times the clock CLK1 of the input data IN. The shift register 2 is connected to the output side of the interpolator 1. The shift register 2 has 48 2-bit shift registers 2-i (i = 0 to 47) that shift in synchronization with the clock CLK2. On the output side of the shift register 2-i (i = 1 to 46), the shift register 2- (i + 1) and the tap coefficient K _i are stored and depending on the output value of the shift register 2-i, its positive, negative, or A coefficient buffer 3-i that outputs one of zero is connected, and a coefficient buffer 3-47 is connected to the output side of the shift register 2-47.
4 on the output side of the coefficient buffer 3-i (i = 0 to 47)
An 8-input adder 4 is connected.

Next, the operation of the digital FIR filter having the quadruple oversampling structure shown in FIG. 2 will be described. When the input data X (n) is input to the interpolator 1, the interpolator 1 outputs a clock CLK2 that is four times the clock CLK1 of the input data.
Then, X (n), 0,0,0 is sequentially created and output to the shift register 2-1. The shift register 2 shifts in synchronization with the clock signal CLK2 having the oversampling frequency, and outputs the 2-bit contents from the shift register 2-i to the coefficient buffer 3-i. In the coefficient buffer 3-i, tap coefficients K _i , -K _i , or 0 are output according to the output values -1, 1, 0 of the shift register 2-i (when 0 generated by the interpolator 1 is output). Is output to the adder 4. In the adder 4, the 48 tap coefficients output from the coefficient buffer 3-i are added with the clock having the same oversampling frequency as the clock CLK2, and the output data O
Output UT.

[0005]

However, in the conventional n-fold oversampled digital filter,
There were the following issues. If a digital filter is used to implement a rapid filter for band limitation, a large number of filter tap coefficients (for example, 48) are required. Therefore, when manufacturing hardware, two-input adders corresponding to the number of filter tap coefficients are required, which causes a problem of enormous amount of hardware. For example, a case of 8-tap coefficient will be briefly described. FIG. 3 is a diagram showing the configuration of the 8-input adder. As shown in the figure, in the case of an 8-tap coefficient digital filter, seven 2-input adders 14-1 to 14-7 are required, and many 2-input adders are required. Further, in the case of 48 tap coefficients, a total of 48 two-input adders of 24 + 12 + 6 + 3 + 2 + 1 are required.

[0006]

In order to solve the above problems, the present invention provides the following circuit in an oversampling digital filter for filtering at an oversampling frequency which is n times the frequency of a clock of input data. . That is, m (m is a natural number) shift registers that perform a shift operation with a clock having the same frequency as the input data, and timing signals for inputting the signals output from the shift registers are input, and the output of each shift register is input. M coefficient selection circuits that generate tap coefficients at an oversampling frequency that is n times that of the clock according to the value and the timing signal, and clocks that have the same frequency as the oversampling frequency. And an adder that calculates the sum of the output m tap coefficients.

[0007]

According to the present invention, since the oversampling digital filter is constructed as described above, it is possible to use the m number of shift registers to generate 1 clock with the same frequency as the input data.
Input data is output to each coefficient selection circuit while being shifted bit by bit. Each coefficient selection circuit samples the input data from the input timing signal with a clock having a frequency n times the frequency of the input data, and outputs a tap coefficient corresponding to the value to the adder. The adder adds the input data at an oversampling frequency of a clock that is n times the input data. This allows the adder to have m inputs.
Therefore, the above problem can be solved.

[0008]

FIG. 1 is a circuit diagram of an oversampling digital filter with 4 times the 48-tap coefficient according to an embodiment of the present invention. This oversampling digital filter is different from the conventional oversampling digital filter in that the number of shift registers 20-i (i = 0 to 11) is reduced to 12 and the shift operation clock CLK has the same frequency as the input data clock. with the clock, the output of the shift register 20-i receives the timing signal of the over sampling frequency _{T 0, T 1, T 2} , T 3 , the timing signal _{T 0, T 1, T 2} , T 3 And the value SHR _i of the shift register 20-i, operate with 12 coefficient selection circuits 21-i that output tap coefficients at an oversampling frequency that is 4 times the frequency of the clock CLK and a clock that is 4 times the frequency of the clock CLK. That is, a 12-input adder 22 is provided.

As shown in FIG. 1, this oversampling digital filter has a shift register 20 that performs a 1-bit shift operation with a clock CLK having the same frequency as the clock of the input data IN. Shift register 20
Is 12 shift registers 20-i (i = 0 to 11)
have. Shift register 20-i (i = 0 to 1
0) data output terminal Q has a shift register 20-
The (i + 1) data input terminal D and the coefficient selection circuit 21-i for selecting the tap coefficient are connected, and the data output terminal Q of the shift register 20-11 includes the coefficient selection circuit 21-11 for selecting the tap coefficient. It is connected. A clock signal CLK that defines the shift operation and has the same frequency as the clock of the input data is input to the clock input terminal CP of each shift register 20-i. Shift register 20
The input data IN is input to the −0 data input terminal D. Four timing signals T ₀ , T ₁ , T ₂ and T ₃ are input to the coefficient selection circuit 21-i. The timing signals T ₀ , T ₁ , T ₂ , T ₃ are input clock CLK.
Has a pulse width divided by four, and each has a different quarter phase. On the output side of the coefficient selection / selection circuit 21-i,
A 12-input adder 22 is connected. Adder 22
Operates with a clock having a frequency four times that of the clock signal CLK. Output data OUT is output from the adder 22. SHR _i is the output signal of the shift register 20-i, and F _i is the output signal of the coefficient selection circuit 21-i.

FIG. 4 is a diagram showing a memory of tap coefficients. The tap coefficient memory stores 48 tap coefficients K ₀ , K ₁ , ..., K ₄₇ , and the coefficient selection circuit 21-
i (i = 0 to 11) is the tap coefficient K _{4 * i} , K _{4 * i + 1} ,
It is connected to a memory for storing K _{4 * i + 2} and K _{4 * i + 3} . FIG. 5 is a timing chart for explaining the operation of FIG. Hereafter, referring to these figures, FIG.
The operation of the double oversampling digital filter will be described. The shift register 20-0 has a clock signal CLK.
Digital input data n, n at the rising edge of
+1, n + 2, n + 4, ... Are sequentially input. The shift register 20 performs a 1-bit shift operation at the rising timing of the clock signal CLK, and each shift register 2
0-i outputs the output signal SHR _i from the coefficient selection circuit 21-
output to i.

FIG. 6 is a logic table showing the operation of the coefficient selection circuit 21-i shown in FIG. Coefficient selection circuit 21
-I, as shown in FIG. 6, each timing signal T _k
When (k = 1,2,3,4) is “1” and the output signal SHR _i of the shift register 20- _i is “1”, the tap coefficient K _{4 *} stored in the tap coefficient memory is stored _{. If} a negative value of _{i + (k-1)} is selected and it is "0", a positive value of the tap coefficient K4 _{* i + (k-1)} is selected and its value F _i is sent to the adder 22. Output.
That is, as shown in FIG. 5, the coefficient selection circuit 21-i shifts the shift register 20-i at the timing when the timing signal T _k (k = 1,2,3,4,1, ...) Becomes “1”. Corresponding to the value of the output signal SHR _i of the tap coefficient m, m + 1, m + 2, at an oversampling frequency that is four times as high as the clock CLK.
m + 3, m + 4, ... Are generated and output to the adder 22. The adder 22 operates with a clock having an oversampling frequency that is four times the clock signal CLK, adds the tap coefficients F _i output from the coefficient selection circuit 21-i, and outputs the output data OUT from D / Output to A converter.

Next, it will be shown that the transfer characteristic of the digital filter having a 48-tap coefficient which is four times as large as that of the present embodiment is equal to the transfer characteristic of the conventional digital filter shown in FIG. Input data IN is X (11), X (10), ..., X (0)
2 are input in this order, the shift register 2 in FIG.
Outputs the following patterns (I) to (IV). (I) X (0), 0,0,0, X (1), 0,0,0, X (2),…, X (11), 0,0,0 (II) 0, X (0 ), 0,0,0, X (1), 0,0,0, X (2), ..., 0, X (11), 0,0
(III) 0,0, X (0), 0,0,0,, X (1), 0,0,0, X (2),…, 0,0, X (1
1), 0 (IV) 0,0,0, X (0), 0,0,0,, X (1), 0,0,0, X (2),…, 0,0,
0, X (11) Then, (I) ~ each output pattern of (IV) are each timing signal T _o, T _1, T _2, the clock CLK2 in Figure 2 corresponds to the rise each of T ₃ rise of It is output from the shift register 2 at a timing. As shown in (I) to (IV), shift registers 2 to X (0), X (1), ..., X
Each shift register 2-i to which (11) is output is uniquely determined, and 0 is output to the adder 4 as the tap coefficient by 0 created by the interpolator 1.

On the other hand, the coefficient selection circuit 21-i in FIG.
X (0), X (1), ..., X (1 of each output pattern of (I) to (IV) above
1) is output, the tap coefficient corresponding to the output value of the shift register 2 in FIG. 2 is used as the timing signals T ₀ , T ₁ , T ₂ , T
It occurs at each timing of ₃ and is added by the adder 22 in FIG. Therefore, the output result of the adder 22 is the same as the output result of the adder 4 in FIG. That is, 4 of the present embodiment
It can be seen that the transfer characteristic of the 48-tap digital filter having the double oversampling configuration is the same as the transfer characteristic of the conventional digital filter. As described above, this embodiment has the following advantages. (A) Twelve shift registers 20-i that shift at the timing of the clock CLK of input data and a pulse width obtained by dividing the frequency of oversampling by 4 according to the value of the output SHR _i of each shift register 20-i. And a coefficient selection circuit 21-i for outputting tap coefficients at timings of the timing signal T _k having different phases by 1/4.
Since the adder 22 that operates with four times the clock of the clock signal CLK is provided, there is an advantage that the number of 2-input adders required in the adder 22 can be reduced to one fourth. (B) There is an advantage that the number of shift registers 20 can be reduced to 1/4 and the circuit of the digital filter can be simplified. (C) There is an advantage that the interpolator 1 in FIG. 2 becomes unnecessary and the circuit of the digital filter becomes simple.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In this embodiment, 4 times the 4 times oversampling configuration is used.
Although the 8-tap coefficient digital filter has been described, even in the case of an m × n tap coefficient digital filter having an n (n ≠ 4) times oversampling configuration, m shift registers and input data clock CLK are multiplied by n times. M coefficient selection circuits and clock CL for inputting timing signals for sampling at the oversampling frequency of
It is advisable to provide an m-input adder that operates with a clock that is n times as large as K. (2) In this embodiment, 1-bit input data has been described. However, even in the case of 2-bit or more input data, each shift register has the same bit configuration as the input data bit, , A tap coefficient corresponding to the value of the shift register can be generated.

[0015]

As described in detail above, according to the present invention, the oversampling digital filter is provided with m (m is a natural number) shift registers that shift with a clock having the same frequency as the input data, and each shift. According to the output value of the register and the timing signal, m coefficient selection circuits that generate tap coefficients at an oversampling frequency that is n times the clock, and a coefficient selection circuit that operates with a clock having the same frequency as the oversampling frequency. Since it is provided with an adder for obtaining the sum of m tap coefficients output from, the number of adders can be reduced and the hardware configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a 4 × oversampling digital filter according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional 4 × oversampling digital filter.

FIG. 3 is a configuration diagram of an 8-input adder.

FIG. 4 is a diagram showing a memory of tap coefficients.

FIG. 5 is a timing chart of FIG.

6 is a diagram showing a logical table of a coefficient selection circuit 21-i in FIG.

[Explanation of symbols]

 20, 20-0, ..., 20-11 Shift register 21-0, ..., 21-11 Coefficient selection circuit 22 Adder

Claims (1)

[Claims] 1. An oversampling digital filter for filtering at an oversampling frequency n times (n is a natural number of 2 or more) the frequency of a clock of input data, wherein m ( (m is a natural number), a timing signal for inputting a signal output from the shift register is input, and an output value of the shift register and the timing signal are input to generate an oversampling frequency n times the clock. M coefficient selection circuits that generate tap coefficients, and an adder that operates with a clock having the same frequency as the oversampling frequency and that calculates the sum of m tap coefficients output from the coefficient selection circuit are provided. An oversampled digital filter characterized by the following.