JP2001230263A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a filed effect transistor which has characteristics for high breakdown strength, good gain and good high frequency. SOLUTION: A dielectric film 4 consisting of a high dielectric material of permittivity of 8 or more is provided between a field plate part 9 and a channel layer 2. As the high dielectric material, tantalum oxide (Ta2O5), or example, is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a Schottky gate field effect transistor that operates in a microwave region such as mobile communication, satellite communication, and satellite broadcasting.

[0002]

2. Description of the Related Art A compound semiconductor has a higher electron mobility than that of Si.
Is about 6 times larger in a low electric field and 2-3 times larger in a high electric field. Utilizing this high speed of electrons, applications as high-speed digital circuit elements or high-frequency analog circuit elements have been advanced.

However, in a field-effect transistor using a compound semiconductor, since the gate electrode is in Schottky junction with the channel layer of the substrate, the electric field concentrates on the lower end on the drain side of the gate electrode (encircled portion in FIG. 14). May cause destruction. This is a particularly serious problem in the case of a high-output field-effect transistor requiring a large signal operation.

Therefore, attempts to prevent the electric field concentration at the edge of the gate electrode on the drain side and improve the withstand voltage characteristics have been conventionally studied.

One of the reasons is that an eaves portion (hereinafter, referred to as an eaves portion) is formed on the gate electrode.
There is an attempt to form a dielectric film made of SiO ₂ therebelow. FIG.
Reference numeral 2 denotes a schematic structure of a field-effect transistor disclosed in Japanese Patent Application Laid-Open No. 63-87773, in which a dielectric film 34 is buried in a portion on the drain side below a gate electrode 33. By providing such a dielectric film, the concentration of an electric field generated at the drain-side edge of the gate electrode 33 is suppressed.

[0006]

However, in the above prior art, in order to obtain a sufficient effect of alleviating the electric field, the dielectric film has to be thinned, and thus, the field plate portion, the channel layer, and the portion sandwiched between them. It was necessary to increase the value of the capacitance formed by the dielectric film. However, when the thickness of the dielectric film is reduced, there are problems such as breakage of the dielectric film and occurrence of current leakage.

Further, since there is a certain limit in reducing the thickness of the dielectric film, there is naturally an upper limit of the capacitance value. For this reason, in order to generate a sufficient electric field relaxation effect, the length of the field plate portion needs to be longer than a certain value, for example, about the gate length. Further, in this case, the high frequency characteristics are remarkably deteriorated, and this becomes a serious problem depending on the use application.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a field effect transistor having high withstand voltage characteristics, good gain characteristics, and good high frequency characteristics.

[0009]

According to the present invention, there is provided a semiconductor substrate having a channel layer formed on a surface thereof, a source electrode and a drain electrode formed separately on the semiconductor substrate, A gate electrode disposed between the source electrode and the drain electrode and Schottky-bonded to the channel layer; the gate electrode includes an eaves-shaped field plate portion on the drain electrode side; A field effect transistor, wherein a dielectric film made of a high dielectric material having a relative dielectric constant of 8 or more is provided between the dielectric layer and the channel layer.

In the field-effect transistor of the present invention, since the dielectric film is provided between the field plate portion and the channel layer, the electric field concentration generated at the edge of the gate electrode on the drain side is dispersed and reduced. The withstand voltage characteristics are improved. This is because the capacitance formed by the field plate portion, the channel layer, and the dielectric film interposed therebetween has a function of terminating the lines of electric force starting from the ionized donor.

In the field effect transistor according to the present invention, a material having a relative dielectric constant of 8 or more is used as a material of the dielectric film provided between the field plate portion and the channel layer. For this reason, even if the dielectric film is thickened, a high capacitance value can be obtained, and a sufficient electric field relaxation effect can be obtained. For example, as compared with the SiO ₂ film used in the prior art, the film thickness for obtaining a constant capacitance can be about twice as large as that in the related art.

As described above, in the present invention, since the thickness of the dielectric film can be made larger than before, the dielectric film can be prevented from being broken and current leakage can be prevented, and the withstand voltage characteristics of the element can be improved. be able to.

Further, since the dielectric film having a high dielectric constant is provided as described above, a sufficient electric field relaxation effect can be obtained without making the length of the field plate portion too long. For example, the length of the field plate portion may be shorter than the gate length. Therefore, high withstand voltage characteristics can be obtained while suppressing a decrease in gain characteristics.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the high dielectric material is aluminum oxide (Al ₂ O ₃ ), aluminum nitride, tantalum oxide (Ta ₂ O ₅ ), strontium titanate (SrTiO ₃ ), barium titanate ( BaTi
O ₃ ), barium strontium titanate (Ba _x Sr)
It is preferably any material selected from the group consisting of _1-x TiO ₃ (0 <x <1)) and bismuth strontium tantalate (SrBi ₂ Ta ₂ O ₉ ). This is because the material has good film-forming properties, has a high relative dielectric constant of 8 or more, and can realize high capacitance in a region below the gate electrode.

In the present invention, it is preferable that the dielectric film is formed only in a region immediately below the field plate portion. For example, as shown in FIG. 3D, the dielectric film 4 is provided immediately below the gate electrode 5, and the source electrode 7-drain electrode 8
It is preferable that a dielectric film is not provided in another region between them. This is because an unnecessary increase in capacitance between the gate and the drain can be avoided and a decrease in gain can be prevented.

As described above, when the dielectric film is formed only in the region immediately below the field plate portion, part or all of the surface of the channel layer is covered with the silicon oxide film,
It is preferable that a dielectric film is provided between the silicon oxide film and the field plate portion. By doing so, the channel layer comes into contact with the upper semiconductor layer via the silicon oxide film, so that deterioration of device characteristics due to deterioration of interface characteristics can be prevented.

In the present invention, the width of the field plate portion is preferably 0.1 μm or more, and more preferably 0.1 μm.
1 μm or more and 2 μm or less. If the width value of the field plate portion is too small, sufficient withstand voltage characteristics may not be obtained. On the other hand, when the value of the width of the field plate portion is too large, the gain characteristics and the high frequency characteristics may deteriorate.

In the present invention, when a high dielectric material is used for the dielectric film, the average value of the thickness of the dielectric film is preferably 100 to 1500 nm, more preferably 300 to 10 nm.
00 nm. If the dielectric film is too thick, the electric field relaxation effect may be reduced. On the other hand, if the dielectric film is made too thin, the insulation film may be broken or current leak may occur. It is preferable to select an appropriate value from the above range according to the value of the dielectric constant of the dielectric film. When the dielectric film has a multilayer structure, the sum of the thicknesses of the respective layers is preferably within the above range.

In the field-effect transistor of the present invention, the capacitance per unit area formed by the field plate portion, the channel layer, and the insulating film sandwiched between the field plate portion, the channel electrode, and the gate electrode is smaller than that of the drain electrode. Preferably, it is larger. By doing this,
The electric field relaxation effect of the field plate portion is moderated on the drain side, and an ideal electric field distribution can be obtained. In the case of such a configuration, particularly, a decrease in high-frequency characteristics can be effectively suppressed.

Here, the magnitude of the capacitance is expressed by the following equation (1).
It is represented as C = εS / d (1) (C: Capacitance ε: Dielectric constant S: Electrode area d: Interelectrode distance) Therefore, as the configuration of the above-described field-effect transistor, as the distance from the gate electrode increases, the distance between electrodes d,
A configuration in which either the electrode area S or the dielectric constant ε is changed can be considered. Specifically, the following are mentioned.

A field effect transistor in which the thickness of the insulating film immediately below the field plate portion is smaller on the gate electrode side than on the drain electrode side.

In this configuration, the value of the capacitance per unit area is changed by changing the distance d between the electrodes.

A field effect transistor having one or more holes formed in a field plate portion.

In this configuration, the value of the capacitance per unit area is changed by changing the electrode area S. FIG. 10C shows an example of a field plate portion having such a structure. As shown in the figure, the holes are preferably provided in a portion of the field plate portion on the drain electrode side. The “hole” refers to a hole penetrating the field plate portion, and may have any shape.

A field-effect transistor in which the end of the field plate on the drain electrode side has a comb shape.

In this configuration, the value of the capacitance per unit area is changed by changing the electrode area S. Here, the term “comb shape” means that the edge portion of the field plate portion has a complicated shape as shown in FIGS. 10A and 10B, for example. However, the present invention is not limited to the example shown in the drawings, and any shape may be used as long as the edge portion is intricate so that the substantial area of the electrode is reduced on the drain electrode side.

A field-effect transistor in which the dielectric constant of the insulating film immediately below the field plate portion decreases as the distance from the gate electrode increases.

In this configuration, the value of the capacitance per unit area is changed by changing the dielectric constant ε.

In the field-effect transistor of the present invention, a float electrode may be provided below the field plate portion. Thus, even when the application to the field plate portion is turned off, the electrons are held in the float electrode, and the electric field concentration at the drain-side edge portion of the gate electrode is dispersed and relaxed. The material of the float electrode is tungsten silicide (WSi), aluminum, gold, titanium /
Platinum / gold or the like can be used. For example, it can be formed by a method of depositing a metal film on the entire surface and then removing unnecessary portions by ion milling using a photoresist as a mask.

In the field effect transistor according to the present invention, an electric field control electrode may be provided between the gate electrode and the drain electrode above the channel layer via a dielectric film. The electric field control electrode has a function of terminating electric lines of force originating from the ionized donor, and disperses and alleviates the electric field concentration generated at the drain-side edge of the gate electrode, thereby improving the breakdown voltage characteristics. Therefore, a synergistic effect with the electric field relaxation effect by the field plate portion is obtained, and the withstand voltage characteristics are further improved. In addition, when both the dielectric film immediately below the field plate portion and the electric field control electrode are provided,
An ideal electric field distribution can be formed between the gate electrode and the drain electrode, and the withstand voltage characteristics can be improved while minimizing deterioration of gain characteristics and high-frequency characteristics.

The high dielectric material used for the electric field control electrode is preferably a high dielectric material having a relative dielectric constant of 8 or more. For example, aluminum oxide (Al ₂ O ₃ ), aluminum nitride, tantalum oxide (Ta ₂ O ₅ ), strontium titanate (SrTiO ₃ ), barium titanate (Ba)
TiO ₃ ), barium strontium titanate (Ba _x
Any material selected from the group consisting of Sr _1-x TiO ₃ (0 <x <1)) and bismuth strontium tantalate (SrBi ₂ Ta ₂ O ₉ ) is preferably used. Further, when the relative dielectric constant of the dielectric film is ε and the film thickness is t, a material satisfying the following (1) or (2) can be used. (1) 1 <ε <5 and 25 <t / ε <70 (2) 5 ≦ ε <8 and 100 <t <350 The material of the electric field control electrode is tungsten silicide (WS
i), aluminum, gold, titanium / platinum / gold and the like can be used. For example, after depositing a metal film on the entire surface,
It can be formed by a method of removing unnecessary portions by ion milling using a photoresist as a mask.

The electric field control electrode is preferably connected to the gate electrode and kept at the same potential. However, an independent potential different from that of the gate electrode may be applied. In particular, by appropriately adjusting the voltage applied to the electric field control electrode, to form an ideal electric field distribution, to prevent electric field concentration directly below the gate electrode while maintaining good gain characteristics and high-frequency characteristics, and to improve withstand voltage characteristics. Can be.

In the field effect transistor according to the present invention, a sub-electrode may be further provided between the source electrode and the gate electrode via a dielectric film above the channel layer. This makes it possible to reduce the resistance of the region immediately below the sub-electrode, thereby increasing the efficiency of the device.

As the material of the sub-electrode, tungsten silicide (WSi), aluminum, gold, titanium / platinum / gold, or the like can be used. For example, after depositing a metal film on the entire surface, ion It can be formed by a method of removing unnecessary portions by milling. The sub-electrode is connected to, for example, a drain electrode and applies a positive voltage. As a result, the region immediately below the sub-electrode has a low resistance, which makes it easier for current to flow, thereby increasing the efficiency of the device.

In the field-effect transistor according to the present invention, the distance between the gate electrode and the drain electrode is preferably longer than the distance between the gate electrode and the source electrode. This is a so-called offset structure, and the electric field concentration at the drain side edge of the gate electrode can be more effectively dispersed and reduced. There is also an advantage in manufacturing that the field plate portion can be easily formed. Further, the field effect transistor of the present invention preferably has a recess structure. This makes it possible to more effectively disperse and reduce the electric field concentration at the drain-side edge of the gate electrode. In the case of a recess structure, a multistage recess may be used.

In the field effect transistor of the present invention, a III-V compound semiconductor such as GaAs can be used as a constituent material of the substrate or the channel layer. III-V compound semiconductors include GaAs, AlGa
As, InP, GaInAsP, and the like. By using a material made of a III-V compound semiconductor, a high-speed and high-output field-effect transistor is realized.

[0037]

(Embodiment 1) The field-effect transistor of this embodiment has a field plate portion 9 having an eave-like gate electrode as shown in FIG. 2 (g). In between, a dielectric film 4 made of Ta ₂ O ₅ is formed.

Hereinafter, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS.

First, MB is placed on a semi-insulating GaAs substrate 1.
According to the E method, 2 × 10¹⁷cm ^-3Doped N-type G
aAs channel layer 2 (230 nm thick) and Si
5 × 10¹⁷cm^-3Doped N-type GaAs contact layer
3 (thickness: 150 nm) is grown (FIG. 1A).

Next, using a resist (not shown) as a mask, an aqueous solution of sulfuric acid or phosphoric acid is used to form the channel layer 2,
The contact layer 3 is wet-etched to form a recess (FIG. 1B).

Subsequently, a dielectric film 4 made of Ta ₂ O ₅ having a thickness of 300 nm is deposited on the entire surface by the CVD method (FIG. 1).
(C)). A resist (not shown) is formed on the dielectric film 4, and the dielectric film 4 at the gate electrode formation location is dry-etched using CHF ₃ or SF ₆ using the resist as a mask. Next, using the dielectric film 4 as a mask, the channel layer 2 at the electrode formation location is etched by about 30 nm (FIG. 1).
(D)).

Next, a 100 nm WSi film, 50
nm TiN film, 15 nm Pt film, 400 nm Au
The films are deposited by sputtering in this order to form a gate metal film 6 (FIG. 2E). Thereafter, a photoresist is provided only at the gate electrode forming portion, and unnecessary portions are removed by ion milling to form the gate electrode 5 (FIG. 2F).

Subsequently, a predetermined portion of the dielectric film 4 is etched to expose the contact layer 3, and an 8 nm Ni film,
A 0 nm AuGe film and a 250 nm Au film are vacuum-deposited in this order to form a source electrode 7 and a drain electrode 8.
A field effect transistor is completed (FIG. 2G).

In the field-effect transistor of this embodiment, since Ta ₂ O ₅ (relative dielectric constant: about 20) is used as the material of the dielectric film 4 between the field plate portion and the channel layer, a sufficient electric field is applied. The thickness of the dielectric film 4 can be increased while obtaining a relaxation effect. For this reason, the breakdown of the dielectric film and the occurrence of current leak, which are problems in the conventional technology, are unlikely to occur.

In this embodiment, the material of the dielectric film 4 is Ta.
_{Although 2} O ₅ is used, silicon nitride (Si ₃ N ₄ ),
Aluminum oxide (Al ₂ O ₃ ), strontium titanate (SrTiO ₃ ), barium titanate (BaTi
O ₃ ), barium strontium titanate (Ba _x Sr)
_1-x TiO ₃ (0 <x <1)) or bismuth strontium tantalate (SrBi ₂ Ta ₂ O ₉ ) can be used. At this time, the film thickness is set to an appropriate value according to the dielectric constant of the selected material. For example, when aluminum oxide (Al ₂ O ₃ ) is used, the thickness is set to 150 to 300 nm.

In this embodiment, the channel layer 2 and the contact layer 3 are formed by the MBE method.
It can also be formed by a method.

(Embodiment 2) In the field-effect transistor of this embodiment, as shown in FIG. 3D, a dielectric film 4 made of Ta ₂ O ₅ is formed only in a region immediately below a field plate portion. I have. Hereinafter, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIG.

First, as in the first embodiment, semi-insulating Ga
An N-type GaAs channel layer 2 and an N-type Ga
A structure in which the As contact layer 3, the dielectric film 4, and the gate metal film 6 are laminated is formed (FIG. 3A). Next, a photoresist is provided only at the gate electrode forming portion, and unnecessary portions are removed by ion milling to form the gate electrode 5 (FIG. 3B). Subsequently, the dielectric film 4 in a region other than the portion where the gate electrode 5 is formed is removed by etching (FIG. 3C). Then, an 8 nm Ni film, 50 nm
Then, an AuGe film of 250 nm and an Au film of 250 nm are vacuum-deposited in this order to form a source electrode 7 and a drain electrode 8, thereby completing a field-effect transistor (FIG. 3D).

In the field effect transistor of this embodiment, since the dielectric film 4 made of Ta ₂ O ₅ is formed only in the region immediately below the field plate portion, good gain characteristics are obtained while having high withstand voltage characteristics. Is obtained.

(Embodiment 3) In the field-effect transistor of this embodiment, as shown in FIG. 5E, a step-like dielectric film 4 made of Ta ₂ O ₅ is formed in a region immediately below a field plate portion. Have been.

Hereinafter, a method of manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS.

First, in the same manner as in Embodiment 1, semi-insulating Ga
An N-type GaAs channel layer 2 and an N-type Ga
An As contact layer 3 is formed. Next, a dielectric film 4 made of Ta ₂ O ₅ is formed (FIG. 4A). The thickness of the dielectric film 4 is 300 nm.

Subsequently, a photoresist (not shown) is provided in a region other than the gate electrode forming portion, and the dielectric film 4 is dry-etched (FIG. 4B). After the photoresist is stripped, the width of the opening is made wider than that, a photoresist (not shown) is provided again, and the dielectric film 4 is dry etched (FIG. 4C). As a result, a step portion is formed at the gate electrode formation location.

Next, a 100 nm WSi film, 50
nm TiN film, 15 nm Pt film, 400 nm Au
After a film is formed by sputtering in this order to form a gate metal film 6, unnecessary portions are removed to form a gate electrode 5 (FIG. 5D).

Next, the dielectric film 4 formed in a region other than the gate electrode forming portion is removed by etching. Subsequently, an 8 nm Ni film, a 50 nm AuGe film, and a 250 nm
The Au film is vacuum-deposited in this order to form a source electrode 7 and a drain electrode 8, thereby completing a field effect transistor (FIG. 5E). The thickness of the dielectric film 4 in the step portion below the field plate portion is 15 in the thin film portion on the left side in FIG.
0 nm, and 300 nm in the right thick film portion.

According to the present embodiment, since the step-like dielectric film made of Ta ₂ O ₅ is formed in the region immediately below the field plate portion, the dielectric film has high withstand voltage characteristics and further excellent high frequency characteristics. Thus, a field-effect transistor having the above characteristics can be obtained.

(Embodiment 4) As shown in FIG. 7, the field-effect transistor of this embodiment has an eave-shaped field plate portion having a gate electrode, and a gate electrode is provided between the field plate portion and the channel layer 2. It has a structure in which two types of dielectric films 4a and 4b are formed. The dielectric film 4b has a lower relative dielectric constant than the dielectric film 4a. In a region immediately below the field plate portion, the relative dielectric constant (average value) of the dielectric film decreases from the gate electrode 5 toward the drain electrode 8. The thickness is increasing. For this reason, the capacitance formed by the field plate portion and the channel layer 2 and the first dielectric film 4a and the second dielectric film 4b sandwiched therebetween gradually decreases toward the drain electrode 8. I have. Hereinafter, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS.

First, in the same manner as in Embodiment 1, semi-insulating Ga
An N-type GaAs channel layer 2 and an N-type Ga
A structure in which the As contact layer 3, the first dielectric film 4a, and the gate metal film 6 are laminated is formed, and unnecessary portions of the gate metal film 6 are removed by ion milling to form the gate electrode 5 (FIG. 6A )). The material of the first dielectric film 4a is Ta ₂ O ₅ and the thickness is 150 nm.

Next, a second dielectric film 4b is deposited on the entire surface (FIG. 6B). The material of the second dielectric film 4b is Si ₃
N ₄ and a thickness of 150 nm.

Subsequently, the entire surface is dry-etched to substantially completely remove the second dielectric film 4b on the upper surface of the gate electrode 5 (FIG. 6C).

Next, a 50 nm TiN film, 15n
An Mt Pt film and a 400 nm Au film are sputter-deposited in this order, and a gate metal film 6 is formed again. Then, unnecessary portions are removed by ion milling to form a gate electrode 5 (FIG. 6D).

Next, the first and second dielectric films 4a and 4b in the region other than where the gate electrode is to be formed are removed by etching. Thereafter, an 8 nm Ni film and a 50 nm AuG
An e film and a 250 nm Au film are vacuum deposited in this order to form a source electrode 7 and a drain electrode 8, thereby completing a field effect transistor (FIG. 7).

In the field effect transistor of this embodiment, Ta ₂ O ₅ and S
Since the dielectric film made of i ₃ N ₄ is formed, good gain characteristics can be obtained while having high withstand voltage characteristics.

The field effect transistor of this embodiment has a structure in which the capacitance formed immediately below the field plate portion gradually decreases toward the drain electrode 8. For this reason, the electric field relaxation effect by the field plate portion is moderated on the drain side, and an ideal electric field distribution can be obtained. Therefore, a field-effect transistor having high withstand voltage characteristics and further excellent high-frequency characteristics can be obtained.

(Embodiment 5) In the field-effect transistor of this embodiment, as shown in FIG. 9F, two types of dielectric films 4a are provided between the eave-shaped field plate portion and the channel layer 2. , 4b are formed. In a region directly below the field plate portion, the average dielectric constant decreases from the gate electrode 5 to the drain electrode 8. Therefore, the capacitance formed by the field plate portion and the channel layer 2 gradually decreases. Hereinafter, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS.

First, similarly to the first embodiment, semi-insulating Ga
An N-type GaAs channel layer 2 and an N-type Ga
A structure in which the As contact layer 3, the first dielectric film 4a, and the gate metal film 6 are stacked is formed. Next, after depositing a gate metal film on the entire surface, unnecessary portions are removed by ion milling to form a gate electrode 5 (FIG. 8A).

Next, the first and second dielectric films 4 are formed on the entire surface.
a and 4b are deposited (FIG. 8B). First dielectric film 4
The material of a is Ta ₂ O ₅ and the film thickness is 150 nm. The material of the second dielectric film 4b is Si ₃ N ₄ and the thickness is 150 nm.

Subsequently, a photoresist was formed by opening only the gate electrode forming portion (FIG. 8C). Using this as a mask, dry etching is performed to substantially completely remove the second dielectric film 4b on the upper surface of the gate electrode 5 (FIG. 8).
(D)).

Next, a 50 nm TiN film, 15n
A Pt film of m and an Au film of 400 nm are sputter-deposited in this order, and a gate metal film 6 is formed again. Then, unnecessary portions are removed by ion milling to form a gate electrode 5 (FIG. 9E).

Next, the first and second dielectric films 4a and 4b formed in regions other than the gate electrode forming portion are removed by etching. Then, an 8 nm Ni film, 50 nm
The AuGe film and the 250 nm Au film are vacuum-deposited in this order to form the source electrode 7 and the drain electrode 8, thereby completing the field effect transistor (FIG. 9F).

In the field effect transistor of this embodiment, Ta ₂ O ₅ and S
Since the dielectric film made of i ₃ N ₄ is formed, good gain characteristics can be obtained while having high withstand voltage characteristics.

Further, the field effect transistor of this embodiment has a structure in which the capacitance formed immediately below the field plate portion gradually decreases toward the drain electrode 8. For this reason, the electric field relaxation effect by the field plate portion is moderated on the drain side, and an ideal electric field distribution can be obtained. Therefore, it is possible to improve the breakdown voltage characteristics while minimizing the deterioration of the high frequency characteristics.

(Embodiment 6) In this embodiment, the gate electrode 5 is formed in various shapes as shown in FIG. FIG.
(A) and (b) show a comb-shaped end on the drain side of the gate electrode 5, and (c) shows a case where a plurality of holes are provided in the drain side portion of the gate electrode 5. is there.
In any of the shapes, the gate is obtained by reducing the drain-side electrode area S in the equation (1) C = εS / d (1) (C: capacitance ε: dielectric constant S: electrode area d: distance between electrodes). The capacitance per unit area immediately below the electrode 5 is smaller on the drain side than on the gate side. By doing so, the electric field relaxation effect of the field plate portion is moderated on the drain side, and an ideal electric field distribution can be obtained.
Therefore, it is possible to improve the breakdown voltage characteristics while minimizing the deterioration of the high frequency characteristics.

Processing for forming the gate electrode into various shapes as shown in FIG. 10 can be performed by using a known etching technique or the like.

(Embodiment 7) The field effect transistor of this embodiment has an electric field control electrode 11 between a drain electrode 8 and a gate electrode 5 as shown in FIG. This further improves the breakdown voltage characteristics.

The field-effect transistor according to the second embodiment
After the gate electrode 5 having the dielectric film 4 just below the field plate portion is formed by the same process as
Is obtained. Electric field control electrode 11
First, a 50 nm Ti film, a 30 nm Pt film,
After vacuum-depositing a 200 nm Au film in this order, the film is formed by removing unnecessary portions by ion milling.

(Embodiment 8) The field-effect transistor of this embodiment includes a sub-electrode 12 between a source electrode 7 and a gate electrode 5 as shown in FIG.

The field-effect transistor according to the second embodiment
By forming the gate electrode 5 having the dielectric film 4 immediately below the field plate portion by the same process as described above, the sub-electrode 12 is formed. The sub-electrode 12 has a 50 nm Ti film, a 30 nm Pt film, and a 200 nm
After vacuum-depositing the Au film in this order, unnecessary portions are removed by ion milling.

The sub electrode 12 is formed, for example, on the drain electrode 8
And apply a positive voltage. As a result, the region immediately below the sub-electrode 12 has a low resistance, which makes it easier for current to flow, thereby increasing the efficiency of the device.

(Embodiment 9) The field-effect transistor of this embodiment includes a float electrode 13 below the field plate 9 as shown in FIG.

This field-effect transistor is similar to that of the first embodiment.
1 (c) (the dielectric film a in FIG. 1 corresponds to the dielectric film a in FIG. 13), and then the metal material and the dielectric film b forming the float electrode 13 are removed. After depositing and etching the gate electrode formation site, a gate metal film 6 is formed on the entire surface. In the subsequent steps, the same steps as those in FIG.
A field effect transistor having a structure as shown in FIG. 13 can be obtained. The material forming the float electrode is, for example, tungsten silicide (WSi), aluminum,
Gold, titanium / platinum / gold, etc. are used.

Since the field-effect transistor of this embodiment is provided with the float electrode as described above, electrons are retained in the float electrode even when the application to the field plate portion is turned off, and the drain-side edge portion of the gate electrode is formed. Electric field concentration is dispersed and alleviated.

In the following example, a semiconductor substrate having a channel layer formed on a surface thereof, a source electrode and a drain electrode formed separately on the semiconductor substrate, and a source electrode and a drain electrode are provided between the source electrode and the drain electrode. A gate electrode that is Schottky-bonded to the channel layer, the gate electrode includes an eaves-shaped field plate portion on the drain electrode side, and a dielectric film is provided between the field plate portion and the channel layer. Provided, the relative dielectric constant of the dielectric film is ε,
When the thickness is t (nm), the following (1) or (2) (1) 1 <ε <5 and 25 <t / ε <70 (2) 5 ≦ ε <8 and 100 This is an example of a field-effect transistor satisfying <t <350.

In the prior art, it has been difficult to achieve both a sufficient effect of alleviating the electric field and prevention of breakdown and current leakage of the dielectric film immediately below the field plate portion. In this regard, according to the above-described transistor, such a problem is solved by focusing on the relative permittivity and the film thickness of the dielectric film and defining the relationship between the two.

When 1 <ε <5, t / ε
Is less than 25, the dielectric film is broken and current leaks. On the other hand, if t / ε exceeds 70, a sufficient electric field relaxation effect cannot be obtained. Note that the relative permittivity and the film thickness refer to an average value of the relative permittivity and the film thickness of the dielectric film immediately below the field plate portion. Here, when a plurality of dielectric films made of different materials are provided immediately below the field plate portion, t / ε
As the value of, a converted value (t / ε) _RED expressed by the following equation is used. (T / ε) _RED = t ₁ / ε ₁ + t ₂ / ε ₂ + ... +
t _n / ε _n (n is an integer of 2 or more) In the case where 5 ≦ ε <8, if t is less than 100, breakdown and current leakage of the dielectric film occurs. On the other hand, if t exceeds 350, a sufficient electric field relaxation effect cannot be obtained. The film thickness is
The average value of the thickness of the dielectric film immediately below the field plate portion.

Example 1 As shown in FIG. 16G, the field-effect transistor of this example has a field plate portion 9 having an eave-like gate electrode, and a gap between the field plate portion 9 and the channel layer. In addition, a dielectric film 4 ′ made of SiO ₂ is formed.

Hereinafter, a method of manufacturing the field-effect transistor of this example will be described with reference to FIGS.

First, the MB is placed on a semi-insulating GaAs substrate 1.
According to the E method, 2 × 10¹⁷cm ^-3Doped N-type G
aAs channel layer 2 (230 nm thick) and Si
5 × 10¹⁷cm^-3Doped N-type GaAs contact layer
3 (thickness: 150 nm) is grown (FIG. 15A).

Next, using a resist (not shown) as a mask, an aqueous solution of sulfuric acid or phosphoric acid is used to form the channel layer 2,
The contact layer 3 is wet-etched to form a recess (FIG. 15B).

Subsequently, a dielectric film 4 'made of SiO ₂ having a thickness of 150 nm is deposited on the entire surface by the CVD method (FIG. 1).
5 (c)). The dielectric film 4 'resist (not shown) is formed on the, the gate electrode forming portion dielectric film 4 as a mask which' is dry-etched using a CHF ₃ or SF _6. Next, using the dielectric film 4 'as a mask, the channel layer 2 at the electrode formation location is etched by about 30 nm (FIG. 15D).

Next, a 100 nm WSi film, 50
nm TiN film, 15 nm Pt film, 400 nm Au
The films are deposited by sputtering in this order to form a gate metal film 6 (FIG. 16E). Thereafter, a photoresist is provided only at the gate electrode forming portion, and unnecessary portions are removed by ion milling to form the gate electrode 5 (FIG. 16).
(F)).

Subsequently, a predetermined portion of the dielectric film 4 'is etched to expose the contact layer 3, and an 8 nm-thick Ni film,
A 50 nm AuGe film and a 250 nm Au film are vacuum-deposited in this order to form a source electrode 7 and a drain electrode 8 to complete a field effect transistor (FIG. 16).
(G)).

The field effect transistor of this example uses SiO ₂ as the material of the dielectric film 4 ′ between the field plate portion and the channel layer. The relative dielectric constant of SiO ₂ is about 3.9, and the thickness of the dielectric film 4 ′ is 150 nm. Therefore, the value of t / ε is about 38, which satisfies the following equations (1) and (2). (1) 1 <ε <5 (2) 25 <t / ε <70 Since the field-effect transistor of this example has the dielectric film 4 ′ that satisfies the above conditions, it exhibits good withstand voltage characteristics,
In addition, breakdown of the dielectric film and occurrence of current leak hardly occur.

(Example 2) SiN was used as the material of the dielectric film 4 '.
A field effect transistor is completed in the same manner as in Example 1 except that a film is used and the film thickness is set to 200 nm (FIG. 16G).

Since the relative dielectric constant of SiN is about 7, and the thickness of the dielectric film 4 ′ is 200 nm, the field-effect transistor of this example satisfies the following equations (1) and (2). (1) 5 ≦ ε <8 (2) 100 <t <350 Therefore, the field-effect transistor of the present example exhibits good withstand voltage characteristics, and is unlikely to cause dielectric film breakdown and current leakage.

[0096]

As described above, in the field-effect transistor of the present invention, a dielectric film having a relative dielectric constant of 8 or more is formed between the field plate portion of the gate electrode and the channel layer. Since a material having such a high dielectric constant is used, the thickness of the dielectric film can be increased while obtaining a sufficient electric field relaxation effect. For this reason, the breakdown of the dielectric film and the occurrence of current leak, which are problems in the conventional technology, are unlikely to occur. Therefore, the withstand voltage characteristic can be effectively improved while suppressing the decrease in the gain characteristic.

Further, the capacitance per unit area formed by the field plate portion, the channel layer, and the dielectric film sandwiched between them becomes smaller as the distance from the gate electrode increases. The electric field relaxation effect of the field plate portion is moderated on the drain side, and an ideal electric field distribution can be obtained.
Therefore, it is possible to improve the breakdown voltage characteristics while minimizing the deterioration of the high frequency characteristics.

Further, by providing the electric field control electrode between the gate electrode and the drain electrode, a synergistic effect with the electric field relaxation effect by the field plate portion is obtained, and the withstand voltage characteristics are further improved.

Further, by providing a sub-electrode between the source electrode and the gate electrode, the efficiency of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a field-effect transistor of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the field-effect transistor of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the field-effect transistor of the present invention.

FIG. 4 is a cross-sectional view of the field-effect transistor of the present invention.

FIG. 5 is a sectional view of a field-effect transistor of the present invention and a top view of a field plate portion.

FIG. 6 is a cross-sectional view of the field-effect transistor of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the field effect transistor of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the field effect transistor of the present invention.

FIG. 9 is a sectional view of a field-effect transistor of the present invention.

FIG. 10 is a sectional view of a field-effect transistor of the present invention.

FIG. 11 is a sectional view of a field-effect transistor of the present invention.

FIG. 12 is a cross-sectional view of a conventional field-effect transistor.

FIG. 13 is a sectional view of a field-effect transistor of the present invention.

FIG. 14 is a diagram for explaining electric field concentration at the lower end of a gate in a conventional field effect transistor.

FIG. 15 is a process sectional view illustrating the method for manufacturing the field effect transistor of the present invention.

FIG. 16 is a process sectional view illustrating the example of the method for manufacturing the field effect transistor.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate 2 channel layer 3 contact layer 4 dielectric film 4 'dielectric film 4a first dielectric film 4b second dielectric film 5 gate electrode 6 gate metal film 7 source electrode 8 drain electrode 9 field plate section 10 Photoresist 11 Electric field control electrode 12 Sub-electrode 13 Float electrode 14 Insulating film 31 GaAs substrate 32 Channel layer 33 Contact layer 34 Dielectric

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasunobu Nashimoto 5-7-1 Shiba, Minato-ku, Tokyo Inside the NEC Corporation (72) Inventor Kazunori Mano 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Yosuke Miyoshi 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Yasunori Mochizuki 5-7-1 Shiba, Minato-ku, Tokyo NEC Inside a stock company

Claims (8)

[Claims] A semiconductor substrate having a channel layer formed on a surface thereof, a source electrode and a drain electrode formed separately on the semiconductor substrate, and disposed between the source electrode and the drain electrode; A gate electrode having a Schottky junction with the channel layer, wherein the gate electrode has an eaves-shaped field plate portion on the drain electrode side, and has a relative dielectric constant of 8 or more between the field plate portion and the channel layer. A field-effect transistor provided with a dielectric film made of a high dielectric material. 2. The high dielectric material includes aluminum oxide (Al ₂ O ₃ ), aluminum nitride, and tantalum oxide (Ta).
₂ O ₅ ), strontium titanate (SrTiO ₃ ), barium titanate (BaTiO ₃ ), barium titanate.
Strontium (Ba _x Sr _1-x TiO ₃ (0 <x <
_2. The field effect transistor according to claim 1, wherein the field effect transistor is any material selected from the group consisting of 1)) and bismuth strontium tantalate (SrBi ₂ Ta ₂ O ₉ ). 3. The semiconductor device according to claim 2, wherein at least a part of a surface of said channel layer is covered with a silicon oxide film, and said dielectric film is provided between said silicon oxide film and said field plate portion. 3. The field-effect transistor according to 1 or 2. 4. The field effect transistor according to claim 1, wherein said dielectric film has a thickness of 100 nm or more and 1500 nm or less. 5. The field effect transistor according to claim 1, wherein said dielectric film is formed only in a region immediately below said field plate portion. 6. An electric field control electrode is further provided between said gate electrode and said drain electrode, above said channel layer via a dielectric film. The field-effect transistor according to any one of the preceding claims. 7. The field effect transistor according to claim 1, wherein said channel layer is made of a group III-V compound semiconductor. 8. The field effect transistor according to claim 1, which has a recess structure.