JP3249446B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a field-effect transistor having a T-shaped electrode.

[0002]

2. Description of the Related Art High mobility field effect transistors (HEMs)
Field effect transistors made of compound semiconductors such as T (High Electron Mobilty Transistor) are being applied to microwave and millimeter wave bands due to their high electron mobility. Narrowing the gate length is the most effective way to achieve higher performance for applications in higher frequency bands. Currently, devices with gate lengths on the order of 0.1 μm are being developed and put into practical use. .

However, if the gate length is simply reduced,
There is a problem that the electrode cross-sectional area in the gate width direction is also reduced and the gate resistance is increased, thereby deteriorating the performance of the device. In order to avoid this problem, a T-shaped gate electrode that can secure a cross-sectional area while keeping the gate length narrow has been widely used.

FIG. 5 shows the structure of a conventional HEMT having a T-shaped gate electrode. 11 is an anti-insulating GaAs
Substrate, 12 is a non-doped GaAs buffer layer, 13 is a non-doped InGaAs channel layer, 14 is n-type AlGa
As electron supply layer, 15 is a non-doped AlGaAs Schottky contact layer, 16 is an n-type GaAs ohmic contact layer, 61 is an insulating film, 62 is a T-shaped gate electrode, 63 is a gap, 22 is a drain electrode, and 23 is a source electrode. It is.

Next, a manufacturing process of the HEMT will be described with reference to a process sectional view of FIG. First, a semi-insulating GaAs substrate 1
1, a buffer layer 12, a channel layer 13, and an electron supply layer 1
4, the Schottky contact layer 15 and the ohmic contact layer 16 are sequentially laminated, and the ohmic contact layer 16 is formed.
An insulating film 61 is formed thereon. Then, on the insulating film 61,
A resist pattern 71 having an opening having a width of 0.1 μm is formed using an electron beam exposure apparatus (FIG. 7A). Next, using the resist pattern 71 as a mask, the insulating film 61 is used.
After etching, the resist pattern 71 is removed to form an opening 72 having the same width as the opening of the resist pattern 71 (FIG. 7B). Next, the insulating film 6
1 on the region including the opening 72 of 0.1 μm.
A resist pattern 73 having an inversely tapered opening 74 having a width of μm is formed (FIG. 7C). Next, the opening 7
The ohmic contact layer 16 exposed at 4 is removed by wet etching to form a recess structure (FIG. 7D). Next, an electrode material 6 serving as a gate electrode is formed on the entire surface.
7 is vapor-deposited using a vacuum vapor deposition method (FIG. 7 (e)), and thereafter, the resist material 73 is dissolved to remove the electrode material 62 other than the part to be the gate electrode. 62 are formed (FIG. 7F).

However, when the T-shaped gate electrode 62 is formed by using the above-described vacuum deposition method, the gap 83 formed in the opening of the insulating film 61 increases as the film thickness increases. Is larger and the opening is smaller, so that the connection between the foot and the head of the T-shaped gate electrode 62 becomes thinner (FIG. 8A).

Therefore, the resistance component 81 in the longitudinal direction of the gate electrode is reduced by increasing the cross-sectional area, but the resistance component 82 in the connection direction between the gate electrode and the semiconductor substrate is reversed. Tend to increase.

In particular, in the case of a transistor having a short gate length, since the resistance component in the connection direction occupies most of the gate resistance, the advantage of shortening the gate length cannot be sufficiently exhibited (FIG. 8B). )).

As a result, even if the gate resistance is reduced by adopting the T-shaped gate electrode, the gate resistance does not become smaller than expected, and the noise figure and the maximum oscillation frequency are reduced. There was a problem.

On the other hand, looking at the conventional method of forming a T-shaped electrode from the viewpoint of a manufacturing method, an electron beam exposure apparatus which is expensive and has low throughput at present to form a fine gate length on the order of 0.1 μm is considered. Is needed. For this reason,
The step of forming the T-shaped gate electrode is a main cause of the cost increase of the transistor. In particular, when drawing is performed using an electron beam exposure apparatus, there is a problem that the cost is further increased due to low throughput, and that the method is not suitable for mass production.

[0011]

As described above, the T-shaped gate electrode has almost no effect on the resistance component in the connection direction between the gate electrode and the semiconductor, and cannot effectively reduce the gate resistance. There was a problem.

Further, it is necessary to use a high-priced and low-throughput electron beam exposure apparatus for processing a conventional fine gate electrode pattern, which hinders cost reduction and mass production of high-performance transistors. There was a problem.

It is an object of the present invention to improve the performance by reducing the resistance component in the connection direction, to form a fine gate length without using an electron beam exposure apparatus, to reduce the cost and mass production. Field effect transformer that can facilitate
An object of the present invention is to provide a method for manufacturing a resistor .

[0014]

[Means for Solving the Problems]

[Configuration] The present invention is configured as described below to achieve the above object. (1) The present invention (claim 1) provides a first method on a semiconductor substrate.
A step of forming an insulating film; and a step of forming an insulating film on a predetermined region on the first insulating film.
Forming a resist pattern;
Isotropic etch of the first insulating film using the mask as a mask
A predetermined dimension from the end face of the resist pattern.
Only retreating the first insulating film, the semiconductor substrate
And forming a second insulating film on the resist pattern,
The semiconductor substrate is exposed and the second insulating film and the first insulating film are exposed.
Forming a hole having a film as a side wall;
Pattern and a second insulating film on the resist pattern
Removing the semiconductor substrate exposed to the hole
A step of isotropically etching the plate;
Edge film, and on the semiconductor substrate exposed to the hole
Forming a gate electrode having a T-shaped cross section.
It is characterized by the following.

[0015]

According to the present invention, after the step of removing the resist pattern and the second insulating film on the resist pattern, the first insulating film forming the side wall of the hole is isotropically etched. Preferably, the upper end of the side wall is rounded.

[Operation] The present invention has the following operation and effects by the above configuration. According to the field-effect transistor of the present invention, the cross-sectional area of the pillar portion of the gate electrode decreases toward the semiconductor substrate. That is, the opening diameter of the hole formed in the insulating film and in which the pillar portion of the gate electrode is buried becomes smaller toward the semiconductor substrate. Therefore, the void formed in the hole when depositing the gate electrode material is reduced, and the resistance component in the connection direction between the gate electrode and the semiconductor is greatly reduced. Such a structure has a great effect in a transistor having a small gate width, and the gate resistance can be reduced as compared with a conventional T-shaped gate electrode structure. As a result, the noise figure and the maximum oscillation frequency are improved as the performance of the transistor.

Further, since the upper end of the insulating film on the drain side is rounded, it is possible to prevent disconnection of the electrode material when depositing the gate electrode material, and it is possible to prevent defects such as open defects. No more occurrences are seen.

Further, according to the method of manufacturing a field effect transistor according to the present invention, a high performance field effect transistor having a T-shaped electrode having a narrow gate length can be realized using only an optical exposure apparatus. .

Further, since the insulating film on the drain side and the insulating film on the source side are formed in different steps, the thickness and the material of each can be freely selected. In particular, by increasing the thickness of the drain-side insulating film and embedding a material having a low dielectric constant, it is possible to reduce a parasitic capacitance generated between the eaves portion of the T-shaped electrode and the semiconductor layer. This leads to a reduction in the feedback capacitance of the transistor, and high performance such as improvement in power gain can be realized.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view showing a configuration of a HEMT according to a first embodiment of the present invention.

On an anti-insulating GaAs substrate 11, a non-doped GaAs buffer layer 12, a non-doped InGaAs channel layer 13, an n-type AlGaAs electron supply layer 14, a non-doped AlGaAs Schottky contact layer 15, n
Type GaAs ohmic contact layers 16 are sequentially stacked. The GaAs substrate 11, the buffer layer 12, the channel layer 12, the electron supply layer 14, and the Schottky contact layer 15 are the semiconductor substrates in the claims.

An SiO ₂ film (first insulating film) 17 is formed in a predetermined region on the ohmic contact layer 16. An SiO film (second insulating film) 18 is formed on the ohmic contact layer 16 in a region different from the region where the SiO ₂ film 17 is formed. Then, a hole having the SiO ₂ film 17 and the SiO film 18 as side walls is formed, and the Schottky contact layer 15 exposed to the hole and i
A gate electrode 19 having a T-shaped cross section is formed on the O ₂ film 17 and the SiO film 18. It should be noted that the gate electrode 19 is separated from the ohmic contact
And insulated.

The hole surrounded by the SiO ₂ film 17 and the SiO film 18 is formed to extend upward, and the cross-sectional shape is different between the SiO ₂ film 17 and the SiO film 18.
Then, a drain electrode 20 and a source electrode 21 are formed on the ohmic contact layer 16.

Since the hole is formed in a forward tapered shape, the gate electrode 19 in the hole and the gate electrode 19 on the hole are connected at an obtuse angle. Accordingly, the component of the gate resistance in the connection direction between the ohmic contact layer 16 and the gate electrode 19 is reduced.

Next, a manufacturing process of the HEMT according to the present embodiment will be described with reference to FIGS. First, FIG.
As shown in (a), a non-doped GaAs buffer layer 12 and a non-doped InGaAs are formed on an anti-insulating GaAs substrate.
s channel layer 13, n-type AlGaAs electron supply layer 14,
Non-doped AlGaAs Schottky contact layer 15
Then, a HEMT structure compound semiconductor substrate in which an n-type GaAs ohmic contact layer 16 is sequentially laminated using a metal organic chemical vapor deposition method is prepared. Then, a 200 nm thick Si is formed on the ohmic contact layer 16 by using the CVD method.
An O ₂ film 17 is deposited.

Next, as shown in FIG.
A photoresist is applied on the _second film 17, and a resist pattern 31 is formed using an optical exposure apparatus so as to have an end on the source side of a gate electrode to be formed later.

Next, as shown in FIG. 2C, the SiO ₂ film 17 is isotropically etched using an ammonium fluoride solution with the resist pattern 31 as a mask,
The side surface of the _second film 17 is receded from the side surface of the resist pattern 31 to form a gap 32. At this time, since the SiO ₂ film 17 is etched using isotropic etching,
The side surface of the SiO ₂ film 17 is formed with a slope.

When depositing a SiO film in a later step, the side surface of the SiO ₂ film 17 is receded so that the exposed width of the exposed ohmic contact layer 16 becomes 0.1 μm corresponding to the gate length.

Next, as shown in FIG. 2D, an SiO film 18 is deposited to a thickness of 150 nm on the entire surface by using a vacuum evaporation method. At this time, the SiO film 18 is deposited on the resist pattern 31 and the ohmic contact layer 16, and the SiO film 16 on the resist pattern 31 is formed to protrude like an eaves according to the deposition. Therefore, the SiO film 18 on the ohmic contact layer 16 is formed to have a forward tapered slope. Then, in the previous step, S
Since the side surface of the iO ₂ film 17 is receded,
_The hole 33 exposing the ohmic contact layer 16 is formed with the _second film 17 and the SiO film 18 serving as side walls.

Next, as shown in FIG. 2E, the resist pattern 31 is dissolved, and the resist 31 and the SiO film 18 on the resist 31 are removed. Next, FIG.
As shown in FIG. 5, on the SiO ₂ film 17 and the SiO film 18,
A resist pattern having an inverted tapered opening in a region including the hole 33 is formed.

Next, as shown in FIG.
The GaAs ohmic contact layer 16 is etched by wet etching using the film 18 and the SiO ₂ film 17 as a mask.

Next, as shown in FIG. 3 (h), Ti, Pt, and Au are deposited at 10 nm and 10 nm, respectively, by a vacuum evaporation method.
and a gate electrode 19 is formed.
Next, as shown in FIG.
4 is dissolved to remove unnecessary portions of the gate electrode 19.

Then, as shown in FIG. 3J, the SiO ₂ film 17 and the SiO
8 is etched, and then AuGe is deposited using a vacuum deposition method.
(12%), an electrode material composed of Ni and Au is deposited and patterned to form a drain electrode 20 and a source electrode 2.
Form one. Then, by performing a heat treatment at 390 ° C. for 2 minutes, the drain electrode 20 and the source electrode 21 are formed.
And the ohmic contact layer 16 are ohmic-joined to complete the HEMT.

The transistor of this embodiment (with a gate width of 10
(0 μm), the gate resistance is 2.2Ω, which is about 40% lower than the gate resistance of a conventional transistor having the same size T-shaped electrode. In addition, due to effects such as a decrease in gate / drain capacitance,
The noise figure at 20 GHz is reduced from 1.5 dB in the past to 0.97 dB, and f _max is 130 dB in the past.
Those were GHz is improved to 165GHz, f _t is seen improvement in performance such that what was conventionally 86GHz is improved 95 GHz.

In addition, since an inexpensive and high-throughput optical exposure apparatus can be used instead of an electronic exposure apparatus to form a pattern with a short gate length, the throughput can be increased and the cost can be reduced.

[Second Embodiment] FIG. 4 is a sectional view showing the structure of a HEMT according to a second embodiment of the present invention. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The feature of this embodiment is that the upper end 41 of the hole in the SiO ₂ film 17 is rounded. In this HEMT, after depositing and lift-off of the SiO film 18 (FIG. 2E), the SiO ₂ film 17 is again formed over the entire surface.
Is isotropically wet-etched, and the upper end of the SiO ₂ film 17 is rounded.

In this structure, the thickness of the SiO ₂ film 17 on the drain side is reduced by wet etching, so that there is a problem that the capacity is increased. However, the sharp shape existing at the upper end portion of the SiO ₂ film 17 formed at the time of side etching is rounded and becomes a smooth shape.
Therefore, when depositing the gate electrode 19 thereafter, it is possible to avoid occurrence of a problem such as a step break at an acute angle portion.

The present invention is not limited to the above embodiment. For example, the present invention can be applied to a field effect transistor having a T-shaped electrode without being limited to the HEMT.

In the above embodiment, the semiconductor substrate in which the multilayer film is formed on the GaAs substrate is used, but a bulk semiconductor substrate can be used. FIG.
As shown in FIG. 7, a gap 52 may be formed between the insulating film 51 and the gate electrode 19. When the gap 52 is formed, the capacity is reduced, and the feedback capacity can be reduced. This structure is
The second insulating film can be formed by stacking two insulating films, forming a gate electrode, and then removing an upper insulating film. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0042]

As described above, according to the present invention, the gate area, which is a parasitic resistance for a field effect transistor, is reduced by reducing the opening area of a hole in which a gate electrode is buried toward a semiconductor substrate. And performance can be improved. Also, 0.1
A fine pattern on the order of μm can be formed only by an optical exposure apparatus, and a low-cost transistor that can be mass-produced can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a HEMT according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the HEMT shown in FIG. 1;

FIG. 3 is a process cross-sectional view showing a manufacturing process of the HEMT shown in FIG. 1;

FIG. 4 is a sectional view showing a configuration of a HEMT according to a second embodiment.

FIG. 5 is a sectional view showing a modification of the present invention.

FIG. 6 is a cross-sectional view showing a configuration of a conventional HEMT.

FIG. 7 is a process cross-sectional view showing a manufacturing process of the HEMT shown in FIG. 6;

FIG. 8 is a diagram for explaining a conventional problem.

[Explanation of symbols]

11 ... semi-insulating GaAs substrate 12: a non-doped GaAs buffer layer 13 ... undoped InGaAs channel layer 14 ... n-type AlGaAs electron supply layer 15 ... undoped AlGaAs Schottky contact layer 16 ... n-type GaAs ohmic contact layer 17 ... SiO ₂ film (first 18 insulating film) 18 SiO film (second insulating film) 19 gate electrode 20 drain electrode 21 source electrode 22 air gap 31 first resist pattern 32 air gap 33 hole 34 second resist Pattern 41: Upper end

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812 H01L 21/28

Claims (1)

(57) [Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of forming a resist pattern in a predetermined region on the first insulating film, and a first insulating film using the resist pattern as a mask Subjecting the first insulating film to a predetermined dimension from an end face of the resist pattern by recessing the first insulating film, and forming a second insulating film on the semiconductor substrate and the resist pattern; Forming a hole in which the substrate is exposed and the second insulating film and the first insulating film are sidewalls; removing the resist pattern, and removing the second insulating film on the resist pattern; A step of isotropically etching the semiconductor substrate exposed to the hole; forming a first and second insulating films, and a gate electrode having a T-shaped cross section on the semiconductor substrate exposed to the hole. Method of manufacturing a field effect transistor which comprises the step of forming.