JP2001085670A - Field effect type transistor and its manufacturing method - Google Patents
Field effect type transistor and its manufacturing methodInfo
- Publication number
- JP2001085670A JP2001085670A JP25968199A JP25968199A JP2001085670A JP 2001085670 A JP2001085670 A JP 2001085670A JP 25968199 A JP25968199 A JP 25968199A JP 25968199 A JP25968199 A JP 25968199A JP 2001085670 A JP2001085670 A JP 2001085670A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- effect transistor
- metal
- field
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 239000010407 anodic oxide Substances 0.000 claims 2
- 238000002161 passivation Methods 0.000 abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 125000005842 heteroatom Chemical group 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 241000981595 Zoysia japonica Species 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- BTBUEUYNUDRHOZ-UHFFFAOYSA-N Borate Chemical compound [O-]B([O-])[O-] BTBUEUYNUDRHOZ-UHFFFAOYSA-N 0.000 description 1
- 102100021943 C-C motif chemokine 2 Human genes 0.000 description 1
- 102100031102 C-C motif chemokine 4 Human genes 0.000 description 1
- 101000897480 Homo sapiens C-C motif chemokine 2 Proteins 0.000 description 1
- 101000777471 Homo sapiens C-C motif chemokine 4 Proteins 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- WNLRTRBMVRJNCN-UHFFFAOYSA-L adipate(2-) Chemical compound [O-]C(=O)CCCCC([O-])=O WNLRTRBMVRJNCN-UHFFFAOYSA-L 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電界効果型トランジ
スタ及びその製造方法に関し、特にＧａＮを用いる電界
効果型トランジスタの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly, to a structure of a field effect transistor using GaN.
【０００２】[0002]
【従来の技術】従来、ＧａＮを用いた電界効果型トラン
ジスタにおいては、キャリア移動度が高くまた破壊電圧
が高いことから、高周波高出力トランジスタとして開発
が進められている。2. Description of the Related Art Conventionally, field effect transistors using GaN have been developed as high-frequency high-output transistors because of their high carrier mobility and high breakdown voltage.
【０００３】現在は、エッチング技術の未発達からソー
スからドレインまで全く同じ表面を用いるデバイスが多
く報告されている。この場合には表面準位の影響が非常
に大きく、ヒステリシス等の問題が研著である。これを
回避するためにＧａＡｓ系の電界効果型トランジスタで
用いられるリセス構造が開発されている。At present, many devices using the same surface from the source to the drain have been reported since the etching technology was not developed. In this case, the influence of the surface state is very large, and problems such as hysteresis are well known. In order to avoid this, a recess structure used in a GaAs field effect transistor has been developed.
【０００４】図６は従来のリセス構造の電界効果型トラ
ンジスタの断面模式図である。ＧａＡｓでのリセス領域
１３は低いＯＮ抵抗と高耐圧を両立させるために、両者
のバランスで設計されており、ＯＮ抵抗と耐圧とには相
反する関係がある。FIG. 6 is a schematic sectional view of a conventional recessed field effect transistor. The recess region 13 of GaAs is designed to balance low ON resistance and high withstand voltage, and there is an opposite relationship between ON resistance and withstand voltage.
【０００５】しかしながら、ＧａＮではバンドギャップ
が３．９ｅＶと大きいため、アバランシェ破壊がしにく
く、同じ構造でもＧａＡｓに比べて５倍の耐圧があると
いわれている。However, since GaN has a large band gap of 3.9 eV, avalanche breakdown is unlikely to occur, and it is said that the same structure has a breakdown voltage five times that of GaAs.
【０００６】図７は従来のＧａＡｓ系のデバイスで用い
られていた側壁構造の電界効果型トランジスタの断面模
式図である。１４はキャップ層と呼ばれる低抵抗ｎ型層
である。本構造を用いることで、７のパッシベーション
膜との界面の界面準位に電荷が溜まっても、その影響は
低抵抗ｎ型層１４の全伝導度に比べればわずかな変化し
か及ぼさないので、ヒステリシス等の問題は小さく押さ
えられる。FIG. 7 is a schematic sectional view of a field-effect transistor having a side wall structure used in a conventional GaAs-based device. Reference numeral 14 denotes a low-resistance n-type layer called a cap layer. By using this structure, even if charges accumulate at the interface state at the interface with the passivation film 7, the effect of the charges has only a slight change compared to the total conductivity of the low-resistance n-type layer 14, and therefore, the hysteresis And other problems are kept small.
【０００７】しかしながら、キャップ層の抵抗を小さく
すると、ゲートの端部に高電界が加わることになるので
耐圧低下の問題を起こす。そのため、このような構造は
電源電圧が低いディジタルＩＣ（集積回路）でしか使え
ない。そのため、高周波アナログ回路のようなある程度
高い電圧の信号まで使うためには、キャップ層の不純物
濃度に関しては無制限に下げれば良いというものではな
かった。この技術については、特開平１１−１９１６１
９号公報に開示されている。However, when the resistance of the cap layer is reduced, a high electric field is applied to the end of the gate, which causes a problem of reduction in withstand voltage. Therefore, such a structure can be used only for a digital IC (integrated circuit) having a low power supply voltage. Therefore, in order to use a signal of a somewhat high voltage such as a high-frequency analog circuit, the impurity concentration of the cap layer need not be reduced without limitation. This technique is disclosed in Japanese Patent Application Laid-Open No. 11-19161.
No. 9 discloses this.
【０００８】尚、図６及び図７において、１はサファイ
アまたはＳｉＣ基板、２はＡｌＧａＮバッファ層、３は
チャネルの形成されるＧａＮまたはＩｎＧａＮ層、４は
ｎ型ＡｌＧａＮ電荷供給層、５はドレイン電極金属、６
はソース電極金属、８はゲート電極をそれぞれ示してい
る。In FIGS. 6 and 7, 1 is a sapphire or SiC substrate, 2 is an AlGaN buffer layer, 3 is a GaN or InGaN layer in which a channel is formed, 4 is an n-type AlGaN charge supply layer, and 5 is a drain electrode. Metal, 6
Indicates a source electrode metal, and 8 indicates a gate electrode.
【０００９】[0009]
【発明が解決しようとする課題】上述した従来の電界効
果型トランジスタでは、ＧａＡｓパワートランジスタで
用いたリセス構造においても、ＧａＡｓで問題となった
表面準位の問題をやはり回避することができない。In the above-mentioned conventional field-effect transistor, even in the recess structure used in the GaAs power transistor, the problem of the surface level, which has been a problem in GaAs, cannot be avoided.
【００１０】特に、バンドギャップが大きいため、表面
電位の変化量も大きくなることが予測され、ＧａＡｓ以
上に深刻となる可能性がある。また、リセス部の抵抗で
ＯＮ抵抗や高周波特性が損なわれる可能性も有る。In particular, since the band gap is large, the amount of change in the surface potential is also expected to be large, which may be more serious than GaAs. Further, there is a possibility that the ON resistance and the high-frequency characteristics are impaired by the resistance of the recessed portion.
【００１１】そこで、本発明の目的は上記の問題点を解
消し、ＧａＮ系電界効果型トランジスタにおいてＯＮ抵
抗を下げ、高周波特性を向上させ、かつ表面準位の問題
を回避する構造を得ることができる電界効果型トランジ
スタ及びその製造方法を提供することにある。It is therefore an object of the present invention to solve the above-mentioned problems and to obtain a structure that reduces the ON resistance, improves high-frequency characteristics, and avoids the surface level problem in a GaN-based field-effect transistor. An object of the present invention is to provide a field-effect transistor and a method of manufacturing the same.
【００１２】[0012]
【課題を解決するための手段】本発明による電界効果型
トランジスタは、ＧａＮ層及びＩｎＧａＮ層の一方をチ
ャネルとする電界効果型トランジスタであって、チャネ
ル層の上にｎ型及びノンドープＡｌＧａＮ層の一方を、
その上に金属層を、さらにその上に絶縁体層を形成し、
該絶縁膜層と前記金属層とを１回のパターニングで開口
し、その開口部側壁に絶縁膜を形成してから該開口部に
金属を埋め込んでゲートを形成するようにしている。A field effect transistor according to the present invention is a field effect transistor having one of a GaN layer and an InGaN layer as a channel, and one of an n-type and a non-doped AlGaN layer on the channel layer. To
Form a metal layer on it, and further form an insulator layer on it,
The insulating film layer and the metal layer are opened by a single patterning, an insulating film is formed on the side wall of the opening, and a metal is buried in the opening to form a gate.
【００１３】本発明による電界効果型トランジスタの製
造方法は、ＧａＮ層及びＩｎＧａＮ層の一方をチャネル
とする電界効果型トランジスタの製造方法であって、チ
ャネル層の上にｎ型及びノンドープＡｌＧａＮ層の一方
を形成する工程と、その上に金属層を形成する工程と、
さらにその上に絶縁体層を形成する工程と、該絶縁膜層
と前記金属層とを１回のパターニングで開口する工程
と、その開口部側壁に絶縁膜を形成してから該開口部に
金属を埋め込んでゲートを形成する工程とを備えてい
る。A method for manufacturing a field-effect transistor according to the present invention is a method for manufacturing a field-effect transistor using one of a GaN layer and an InGaN layer as a channel, wherein one of an n-type and a non-doped AlGaN layer is provided on the channel layer. And forming a metal layer thereon,
Forming an insulating layer thereon; opening the insulating film layer and the metal layer by one patterning; forming an insulating film on the side wall of the opening; And forming a gate by embedding the same.
【００１４】すなわち、本発明の電界効果型トランジス
タは、ＧａＮ層またはＩｎＧａＮ層をチャネルをとする
電界効果型トランジスタにおいて、チャネル層の上にｎ
型またはノンドープＡｌＧａＮ層の上に金属層または超
格子よりなる低抵抗半導体層を設け、その上に絶縁体層
を設け、この絶縁膜層と金属層または低抵抗半導体層と
を１回のパターニングで開口し、さらに開口部側壁に絶
縁膜を形成し、該開口部に金属を埋めこむことでゲート
を形成することで構成されている。That is, the field-effect transistor of the present invention is a field-effect transistor having a channel of a GaN layer or an InGaN layer.
A low-resistance semiconductor layer made of a metal layer or a superlattice is provided on a mold or non-doped AlGaN layer, an insulator layer is provided thereon, and the insulating film layer and the metal layer or the low-resistance semiconductor layer are formed by one patterning. An opening is formed, an insulating film is formed on the side wall of the opening, and a metal is buried in the opening to form a gate.
【００１５】従来のリセス構造の電界効果型トランジス
タにおいては、上記のように、ＧａＡｓでのリセス領域
が低いＯＮ抵抗と高耐圧とを両立させるために、両者の
バランスで設計されており、ＯＮ抵抗と耐圧とには相反
する関係がある。しかしながら、ＧａＮではバンドギャ
ップが３．９ｅＶと大きいため、アバランシェ破壊がし
にくく、同じ構造でもＧａＡｓに比べ５倍の耐圧がある
といわれている。そこで、ＧａＡｓと同じ程度の電源電
圧を想定した場合には、耐圧の観点からはリセス領域を
形成する必要性は無くなる。In the conventional field effect transistor having the recess structure, the recessed region of GaAs is designed to have both a low ON resistance and a high withstand voltage, as described above. And the withstand voltage have an opposite relationship. However, since GaN has a large band gap of 3.9 eV, avalanche breakdown is unlikely to occur, and it is said that the same structure has a withstand voltage five times that of GaAs. Therefore, when a power supply voltage of the same level as that of GaAs is assumed, there is no need to form a recess region from the viewpoint of withstand voltage.
【００１６】本発明の電界効果型トランジスタにおいて
は、ソース電極やドレイン電極をゲートに極限まで近く
持って来ているが、その耐圧は半導体中のアバランシェ
破壊では決まらず、ゲートとドレインやソースとの間に
置かれた側壁膜の絶縁耐圧で決まることになる。側壁膜
をＳｉＯ2 とすると、２０Ｖの耐圧は４００Å程度の厚
さで十分である。In the field effect transistor of the present invention, the source electrode and the drain electrode are brought as close as possible to the gate, but the breakdown voltage is not determined by avalanche destruction in the semiconductor. It is determined by the withstand voltage of the interposed sidewall film. Assuming that the sidewall film is made of SiO 2 , a withstand voltage of 20 V is sufficient at a thickness of about 400 °.
【００１７】４００Åの抵抗層は、もしチャネルのシー
ト抵抗が比較的高めの１０００Ω／□としても０．０４
Ω／ｍｍと非常に小さく、例えそこの伝導度が数倍変わ
っても大きな影響は起きない。さらに、このような短い
距離ではわずかのバイアスでも表面の状態によらず半導
体に電流が流れるパンチスルーという現象が起きるた
め、表面状態に依存せずに低抵抗となる。The 400 ° resistive layer has a resistance of 0.04 even if the sheet resistance of the channel is relatively high at 1000Ω / □.
Ω / mm, which is very small, and even if the conductivity there changes several times, no significant effect occurs. Further, at such a short distance, a phenomenon of punch-through in which a current flows through the semiconductor regardless of the state of the surface even with a slight bias occurs, so that the resistance becomes low irrespective of the surface state.
【００１８】本発明の電界効果型トランジスタでは、ソ
ースからドレインまでの途中で、パッシベーション膜が
伝導度に影響を与えるのがこの部分のみなので、表面準
位の影響を全く受けないといえる。In the field-effect transistor of the present invention, the passivation film affects only the conductivity of the passivation film halfway from the source to the drain, so it can be said that the passivation film is not affected by the surface state at all.
【００１９】また、従来のＧａＡｓ系のデバイスで用い
られていた側壁構造の電界効果型トランジスタにおいて
は、上記のように、本構造を用いることで、パッシベー
ション膜との界面の界面準位に電荷が溜まっても、その
影響が低抵抗ｎ型層の全伝導度に比べればわずかな変化
しか及ぼさないので、ヒステリシス等の問題が小さく押
さえられる。Further, in the field effect transistor having the side wall structure used in the conventional GaAs-based device, as described above, by using this structure, electric charges are generated in the interface state at the interface with the passivation film. Even if it accumulates, the influence thereof has only a slight change as compared with the total conductivity of the low-resistance n-type layer, so that problems such as hysteresis are suppressed to a small extent.
【００２０】しかしながら、キャップ層の抵抗を小さく
すると、ゲートの端部に高電界が加わることになるの
で、耐圧低下の問題を起こす。そのため、このような構
造は電源電圧が低いディジタルＩＣでしか使えない。そ
のため、高周波アナログ回路のようなある程度高い電圧
の信号まで使うためにはキャップ層の不純物濃度に関し
ては無制限に下げれば良いというものではない。However, when the resistance of the cap layer is reduced, a high electric field is applied to the end of the gate, which causes a problem of reduction in withstand voltage. Therefore, such a structure can be used only for a digital IC having a low power supply voltage. Therefore, in order to use a signal of a somewhat high voltage such as a high-frequency analog circuit, it is not necessary to lower the impurity concentration of the cap layer without limit.
【００２１】[0021]
【発明の実施の形態】次に、本発明の一実施例について
図面を参照して説明する。図１は本発明の一実施例によ
る電界効果型トランジスタの断面模式図である。図１に
おいて、ドレイン電極金属５及びソース電極金属６は金
属で形成され、ゲート電極８との間にはパッシベーショ
ン膜７が存在する。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view of a field effect transistor according to one embodiment of the present invention. In FIG. 1, a drain electrode metal 5 and a source electrode metal 6 are formed of a metal, and a passivation film 7 exists between the drain electrode metal 5 and the source electrode metal 6.
【００２２】このパッシベーション膜７をＳｉＯ2 で形
成し、その厚さを４００Åとした場合、ＳｉＯ2 の耐圧
は５ＭＶ／ｃｍの２０Ｖ程度である。一方、ｎ型ＡｌＧ
ａＮ電荷供給層４は３００Å程度であるが、ドレイン電
極金属５に高電圧が加わった場合には空乏化が起こるの
で、耐圧は膜厚では決まらず、半導体中でのアバランシ
ェ破壊で決まる。When the passivation film 7 is formed of SiO 2 and its thickness is set to 400 °, the withstand voltage of SiO 2 is about 20 V of 5 MV / cm. On the other hand, n-type AlG
The aN charge supply layer 4 has a thickness of about 300 °. However, when a high voltage is applied to the drain electrode metal 5, depletion occurs. Therefore, the breakdown voltage is not determined by the film thickness but by avalanche breakdown in the semiconductor.
【００２３】ゲート長が０．２μｍ程度とした場合、ソ
ース，ドレイン間耐圧はＧａＡｓでは４Ｖ程度まで低下
するが、ＧａＮ系ではその５倍の２０Ｖ程度まで安定に
動作する。そのため、ドレイン電極金属５をこのように
ゲート直近まで持ってきても耐圧の問題は起きない。When the gate length is set to about 0.2 μm, the breakdown voltage between the source and the drain decreases to about 4 V in GaAs, but operates stably to about 20 V, which is five times that in GaN. Therefore, even if the drain electrode metal 5 is brought close to the gate in this way, the problem of the withstand voltage does not occur.
【００２４】図１に示す構造の場合、ドレイン電極金属
５からＧａＮまたはＩｎＧａＮ層３まではｎ型ＡｌＧａ
Ｎ電荷供給層４を通るが、ｎ型ＡｌＧａＮ電荷供給層４
のＡｌ組成を低く、かつドナーの濃度を１０18ｃｍ-3以
上にしておけば、電極抵抗は低く押さえられる。In the case of the structure shown in FIG. 1, an n-type AlGa
Pass through the N charge supply layer 4, but pass through the n-type AlGaN charge supply layer 4
If the Al composition is low and the donor concentration is 10 18 cm −3 or more, the electrode resistance can be kept low.
【００２５】図２（ａ）及び（ｂ）は本発明の一実施例
による電界効果型トランジスタの製造工程を示す断面図
である。これら図１と図２（ａ）と図２（ｂ）とを参照
して本発明の一実施例による電界効果型トランジスタの
製造工程について説明する。FIGS. 2A and 2B are cross-sectional views showing the steps of manufacturing a field effect transistor according to one embodiment of the present invention. With reference to FIGS. 1, 2A and 2B, a description will be given of a manufacturing process of the field-effect transistor according to one embodiment of the present invention.
【００２６】まず、サファイアまたはＳｉＣ基板１の上
にＡｌＧａＮバッファ層２を介してノンドープＧａＮま
たはＧａＩｎＮ層３と、１００〜４００Å程度のｎ型Ａ
ｌＧａＮ電荷供給層４とをエピタキシャル成長法で形成
する。First, a non-doped GaN or GaInN layer 3 is placed on a sapphire or SiC substrate 1 via an AlGaN buffer layer 2 and an n-type A
The lGaN charge supply layer 4 is formed by an epitaxial growth method.
【００２７】この基板に蒸着法を用いて電極用金属層１
５（例えば、Ｔｉ，Ａｌ等の膜）を形成する。厚さは所
望の抵抗値、ドレイン電極までの距離等によるが、導電
性の高いアルミニウム等では１０００Å程度でよい。The metal layer 1 for an electrode is formed on the substrate by vapor deposition.
5 (for example, a film of Ti, Al, etc.). The thickness depends on the desired resistance value, the distance to the drain electrode, etc., but may be about 1000 ° for highly conductive aluminum or the like.
【００２８】続いて、ソース，ドレインの電極となる金
属（ドレイン電極金属５及びソース電極金属６）とゲー
ト金属とを絶縁するための絶縁膜となるパッシベーショ
ン膜１６（パッシベーション膜７）を堆積する。例え
ば、ＳｉＯ2 を堆積するが、その厚さは耐圧の観点から
は４００Å程度で良い。しなしながら、むしろ高周波動
作での寄生容量の観点から３０００Å程度と厚く堆積す
る［図２（ａ）参照］。Subsequently, a passivation film 16 (passivation film 7) serving as an insulating film for insulating a metal serving as source and drain electrodes (a drain electrode metal 5 and a source electrode metal 6) and a gate metal is deposited. For example, SiO 2 is deposited, and its thickness may be about 400 ° from the viewpoint of withstand voltage. However, rather, it is deposited as thick as about 3000 ° from the viewpoint of parasitic capacitance in high frequency operation [see FIG. 2 (a)].
【００２９】次に、フォトレジスト１７でゲートを開口
してゲート開口部１８を形成し、反応性ドライエッチン
グによって、ＣＦ4 でＳｉＯ2 を、Ｃｌ2 でアルミニウ
ムを、ＳＦ6 でチタンを、ＢＣｌ3 でＡｌＧａＮをエッ
チングする。続いて、前面にＳｉＯ2 膜を成長させ、再
びＣＦ4 で方向性エッチングをすることで、先のゲート
開口部１８に絶縁膜の側壁を形成する。さらに、スパッ
タリングでＮｉとＡｕとを蒸着し、ゲート電極８とする
［図２（ｂ）参照］。Next, a gate is opened with a photoresist 17 to form a gate opening 18, and SiO 2 with CF 4 , aluminum with Cl 2 , titanium with SF 6 , and BCl 3 by reactive dry etching. Is used to etch AlGaN. Subsequently, a SiO 2 film is grown on the front surface, and directional etching is performed again with CF 4 to form a sidewall of the insulating film in the gate opening 18. Further, Ni and Au are deposited by sputtering to form a gate electrode 8 (see FIG. 2B).
【００３０】素子分離はこれらの工程の後に金属層をエ
ッチングで落とし、半導体層をＢ等のイオン注入で半絶
縁化する方法で行う。これ以外にも、金属膜蒸着前にア
イソレーション工程を済ませ、金属膜を後から除去する
ことも可能である。他の工程は通常のＧａＮデバイスの
作製工程と同様であるので、その説明は省略する。The element isolation is performed by a method of removing the metal layer by etching after these steps and semi-insulating the semiconductor layer by ion implantation of B or the like. In addition, it is also possible to complete the isolation step before depositing the metal film and remove the metal film later. The other steps are the same as the steps for manufacturing a normal GaN device, and a description thereof will be omitted.
【００３１】図３は本発明の他の実施例による電界効果
型トランジスタの断面模式図である。図３において、本
発明の他の実施例による電界効果型トランジスタは本発
明の一実施例による電界効果型トランジスタの金属層
（ドレイン電極金属５及びソース電極金属６）を５０Å
程度の薄いチタン層９と数千Åのアルミニウム層１０と
している。この場合、６００℃程度の融点以下の温度で
良好なオーミック電極が形成できる。FIG. 3 is a schematic sectional view of a field effect transistor according to another embodiment of the present invention. In FIG. 3, a field effect transistor according to another embodiment of the present invention has a metal layer (drain electrode metal 5 and source electrode metal 6) of the field effect transistor according to one embodiment of the present invention of 50 °.
A thin titanium layer 9 and an aluminum layer 10 of several thousand Å are formed. In this case, a good ohmic electrode can be formed at a temperature lower than the melting point of about 600 ° C.
【００３２】その結果、ソース，ドレイン電極周囲での
余分な寄生抵抗を大幅に削減することができ、パワーデ
バイスで問題となるＯＮ抵抗が低減され、また高周波特
性の改善にも役立つ。As a result, the extra parasitic resistance around the source and drain electrodes can be greatly reduced, the ON resistance which is a problem in the power device is reduced, and the high frequency characteristics are improved.
【００３３】ソース，ドレイン電極用の金属（チタン層
９及びアルミニウム層１０）としては、ＷＳｉ等のシリ
サイドがオーミック形成のためのアロイや開口部形成の
際のドライエッチングダメージの回復アニールを高温で
できるので、好都合である。しかしながら、Ｔｉ／Ａ
ｌ、とりわけＴｉを２０Åから１００Å程度に薄くした
場合には、６００℃程度のアルミニウムが溶けない低温
でも良好なオーミックを形成することができる。As the metal for the source and drain electrodes (titanium layer 9 and aluminum layer 10), silicide such as WSi can be used to form an alloy for ohmic formation or dry annealing damage recovery at the time of forming an opening at a high temperature. So it is convenient. However, Ti / A
When l, especially Ti is reduced to about 20 ° to 100 °, a good ohmic can be formed even at a low temperature of about 600 ° C. where aluminum does not melt.
【００３４】図４は本発明の別の実施例による電界効果
型トランジスタの断面模式図である。図４において、本
発明の別の実施例による電界効果型トランジスタは本発
明の別の実施例による電界効果型トランジスタのチタン
層９及びアルミニウム層１０とゲート電極８との間に陽
極酸化法で絶縁膜（陽極酸化アルミニウム酸化物１１）
を形成したものである。FIG. 4 is a schematic sectional view of a field effect transistor according to another embodiment of the present invention. In FIG. 4, a field effect transistor according to another embodiment of the present invention is insulated between the titanium layer 9 and the aluminum layer 10 and the gate electrode 8 of the field effect transistor according to another embodiment of the present invention by anodic oxidation. Film (anodized aluminum oxide 11)
Is formed.
【００３５】例えば、ホウ酸塩、リン酸塩、アジピン酸
塩等を含む中性溶液中でアルミニウム層１０に電極を取
り、正電圧を加えると、バリア皮膜といわれる稠密な膜
ができる。この膜厚は液組成とバイアス条件とで決まる
ので、比較的均一な厚さになる。この膜を後でアニール
処理することで、良質な絶縁膜（陽極酸化アルミニウム
酸化物１１）を形成することができる。For example, when an electrode is taken on the aluminum layer 10 in a neutral solution containing borate, phosphate, adipate and the like and a positive voltage is applied, a dense film called a barrier film is formed. Since this film thickness is determined by the liquid composition and the bias condition, the thickness is relatively uniform. By annealing this film later, a high-quality insulating film (anodized aluminum oxide 11) can be formed.
【００３６】この方法を用いれば、ＳｉＯ2 を堆積して
エッチングするという面倒な工程が入らず、かつ加工精
度も高くなり、より微細なトランジスタを制御良く作成
することが可能である。By using this method, a troublesome step of depositing and etching SiO 2 is not required, the processing accuracy is increased, and a finer transistor can be manufactured with good control.
【００３７】陽極酸化では金属層（チタン層９及びアル
ミニウム層１０）に電極を取るため、分離されているこ
とが好ましくない。そのため、ｎ型ＡｌＧａＮ電荷供給
層４やチタン層９及びアルミニウム層１０が全面に存在
する状態で行うか、電流パスを残して処理を行い、後で
電流パスを除去する。In the anodic oxidation, since the electrodes are formed on the metal layers (the titanium layer 9 and the aluminum layer 10), it is not preferable that the electrodes are separated. Therefore, the process is performed in a state where the n-type AlGaN charge supply layer 4, the titanium layer 9, and the aluminum layer 10 are present on the entire surface, or the process is performed while leaving the current path, and the current path is removed later.
【００３８】さらに、電流パスを選択的に形成すれば、
ソース側とドレイン側との陽極酸化の膜厚を変えること
ができる。こうすれば、高耐圧と低寄生容量とが特に必
要なドレイン側のみに厚い膜を形成することができる。Further, if the current path is selectively formed,
The thickness of the anodic oxidation on the source side and the drain side can be changed. This makes it possible to form a thick film only on the drain side where high breakdown voltage and low parasitic capacitance are particularly required.
【００３９】図５は本発明のさらに別の実施例による電
界効果型トランジスタの断面模式図である。図５におい
て、本発明のさらに別の実施例による電界効果型トラン
ジスタでは低抵抗のソース，ドレイン層（ドレイン電極
金属５及びソース電極金属６）をゲート電極８近傍まで
持ってくるために、低抵抗領域を半導体（ＧａＮ／Ａｌ
ＧａＮ超格子層１２，２２）としている。むしろ、製造
工程的には上記のように構成することで、複雑なエッチ
ングを簡略化することができる。FIG. 5 is a schematic sectional view of a field effect transistor according to still another embodiment of the present invention. In FIG. 5, in the field-effect transistor according to still another embodiment of the present invention, the low-resistance source and drain layers (the drain electrode metal 5 and the source electrode metal 6) are brought close to the gate electrode 8, so that the low-resistance The region is semiconductor (GaN / Al
GaN superlattice layers 12, 22). Rather, with the above-described configuration in the manufacturing process, complicated etching can be simplified.
【００４０】従来のＧａＡｓではキャップ層としてｎ型
半導体を用いている。しかしながら、ＧａＮのｎ型層は
移動度が極めて低いといわれている。そのため、本発明
のさらに別の実施例による電界効果型トランジスタでは
ヘテロ構造を導入し、ヘテロ界面の不純物散乱を受けな
い電子をチャネルで利用している。In conventional GaAs, an n-type semiconductor is used as a cap layer. However, it is said that the n-type layer of GaN has extremely low mobility. Therefore, in the field-effect transistor according to still another embodiment of the present invention, a hetero structure is introduced, and electrons which are not subjected to impurity scattering at the hetero interface are used in the channel.
【００４１】ＧａＡｓでも似た状況であるが、ＧａＡｓ
のｎ型層は２×１０18ｃｍ-3程度しかドナー濃度が上げ
られないので、チャネルに１０12ｃｍ-2台のキャリアを
発生させるには、ＡｌＧａＡｓ層が１層で３００Å程度
は必要で、多層のヘテロ層を導入して低抵抗化を図るこ
とができない。The situation is similar in GaAs, but GaAs
Since the n-type layer can only increase the donor concentration by about 2 × 10 18 cm −3 , an AlGaAs layer of about 300 ° is necessary for one carrier to generate 10 12 cm −2 carriers in the channel. The resistance cannot be reduced by introducing a multi-layer hetero layer.
【００４２】しかしながら、ＧａＮ／ＡｌＧａＮ超格子
層１２，２２ではドナー濃度を１桁高くすることができ
るので、層厚が１００Å以下ですむこと、さらにピエゾ
効果でもっと薄いＡｌＧａＮ層でも多量の電荷が発生す
るので、ヘテロ層を多層化して、層数の分だけ伝導度の
向上が可能となる。However, in the GaN / AlGaN superlattice layers 12 and 22, the donor concentration can be increased by one digit, so that the layer thickness can be 100 ° or less, and a large amount of electric charge is generated even in a thinner AlGaN layer due to the piezo effect. Therefore, it is possible to improve the conductivity by the number of layers by increasing the number of hetero layers.
【００４３】本発明のさらに別の実施例による電界効果
型トランジスタではヘテロ層を３層としている。これに
よって、１層が２００Ω程度のシート抵抗を持つので、
７０Ωのシート抵抗となり、ゲート，ドレイン間の距離
が１．５μｍでも、ドレイン抵抗を０．１Ωｍｍと非常
に小さくすることができる。A field effect transistor according to still another embodiment of the present invention has three hetero layers. As a result, since one layer has a sheet resistance of about 200Ω,
The sheet resistance is 70 Ω, and the drain resistance can be extremely reduced to 0.1 Ωmm even when the distance between the gate and the drain is 1.5 μm.
【００４４】上述した構造を用いることで、高い耐圧を
維持しながらソース，ゲート間、ドレイン，ゲート間の
寄生抵抗を極めて小さくすることができる。これによっ
て、高効率なパワーＦＥＴ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ
Ｔｒａｎｓｉｓｔｏｒ）が作製可能となる。By using the above-described structure, the parasitic resistance between the source and the gate and between the drain and the gate can be extremely reduced while maintaining a high breakdown voltage. Thereby, a highly efficient power FET (Field Effect) can be obtained.
Transistor) can be manufactured.
【００４５】また、短チャネル化した場合でも高耐圧、
低寄生抵抗なので、他の半導体では実現できないような
極めて高速のトランジスタを実現することができる。さ
らに、化合物半導体で問題となる表面準位の影響もほと
んど発生しないという利点もある。Even if the channel is shortened, a high withstand voltage,
Since the parasitic resistance is low, an extremely high-speed transistor which cannot be realized by another semiconductor can be realized. Further, there is an advantage that the influence of the surface level which is a problem in the compound semiconductor hardly occurs.
【００４６】[0046]
【発明の効果】以上説明したように本発明によれば、Ｇ
ａＮ層及びＩｎＧａＮ層の一方をチャネルとする電界効
果型トランジスタにおいて、チャネル層の上にｎ型及び
ノンドープＡｌＧａＮ層の一方を、その上に金属層を、
さらにその上に絶縁体層を形成し、該絶縁膜層と金属層
とを１回のパターニングで開口し、その開口部側壁に絶
縁膜を形成してから該開口部に金属を埋め込んでゲート
を形成することによって、ＧａＮ系電界効果型トランジ
スタにおいてＯＮ抵抗を下げ、高周波特性を向上させ、
かつ表面準位の問題を回避する構造を得ることができる
という効果がある。As described above, according to the present invention, G
In a field-effect transistor having one of an aN layer and an InGaN layer as a channel, one of an n-type and non-doped AlGaN layer is provided on a channel layer, and a metal layer is provided thereon.
Further, an insulator layer is formed thereon, the insulating film layer and the metal layer are opened by one patterning, an insulating film is formed on the side wall of the opening, and a metal is buried in the opening to form a gate. By forming the GaN-based field-effect transistor, the ON resistance is reduced, the high-frequency characteristics are improved,
In addition, there is an effect that a structure that avoids the problem of surface states can be obtained.
【図１】本発明の一実施例による電界効果型トランジス
タの断面模式図である。FIG. 1 is a schematic cross-sectional view of a field-effect transistor according to one embodiment of the present invention.
【図２】（ａ）及び（ｂ）は本発明の一実施例による電
界効果型トランジスタの製造工程を示す断面図である。FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a field-effect transistor according to an embodiment of the present invention.
【図３】本発明の他の実施例による電界効果型トランジ
スタの断面模式図である。FIG. 3 is a schematic sectional view of a field-effect transistor according to another embodiment of the present invention.
【図４】本発明の別の実施例による電界効果型トランジ
スタの断面模式図である。FIG. 4 is a schematic sectional view of a field-effect transistor according to another embodiment of the present invention.
【図５】本発明のさらに別の実施例による電界効果型ト
ランジスタの断面模式図である。FIG. 5 is a schematic cross-sectional view of a field-effect transistor according to still another embodiment of the present invention.
【図６】従来のリセス構造の電界効果型トランジスタの
断面模式図である。FIG. 6 is a schematic cross-sectional view of a conventional field-effect transistor having a recess structure.
【図７】従来の側壁構造の電界効果型トランジスタの断
面模式図である。FIG. 7 is a schematic cross-sectional view of a conventional field-effect transistor having a side wall structure.
１ サファイアまたはＳｉＣ基板 ２ ＡｌＧａＮバッファ層 ３ チャネルの形成されるＧａＮまたはＩｎＧａＮ層 ４ ｎ型ＡｌＧａＮ電荷供給層 ５ ドレイン電極金属 ６ ソース電極金属 ７ パッシベーション膜 ８ ゲート電極 ９ チタン層 １０ アルミニウム層 １１ 陽極酸化アルミニウム酸化物 １２，２２ ＧａＮ／ＡｌＧａＮ超格子層 １５ 電極用金属層 １６ パッシベーション膜 １７ フォトレジスト １８ ゲート開口部 Reference Signs List 1 sapphire or SiC substrate 2 AlGaN buffer layer 3 GaN or InGaN layer on which channel is formed 4 n-type AlGaN charge supply layer 5 drain electrode metal 6 source electrode metal 7 passivation film 8 gate electrode 9 titanium layer 10 aluminum layer 11 anodized aluminum Oxide 12,22 GaN / AlGaN superlattice layer 15 Metal layer for electrode 16 Passivation film 17 Photoresist 18 Gate opening
───────────────────────────────────────────────────── フロントページの続き (72)発明者 国弘 和明 東京都港区芝五丁目７番１号 日本電気株 式会社内 (72)発明者 高橋 裕之 東京都港区芝五丁目７番１号 日本電気株 式会社内 (72)発明者 中山 達峰 東京都港区芝五丁目７番１号 日本電気株 式会社内 (72)発明者 羽山 信幸 東京都港区芝五丁目７番１号 日本電気株 式会社内 Ｆターム(参考） 5F102 FA01 FA03 GJ02 GJ10 GL04 GM04 GN08 GQ01 GR04 GT02 GT03 GV07 HC01 HC11 HC15 HC21 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuaki Kunihiro 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Hiroyuki Takahashi 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (72) Inventor Tatsumine Nakayama 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Nobuyuki Hayama 5-7-1 Shiba, Minato-ku, Tokyo Japan F-term (reference) 5F102 FA01 FA03 GJ02 GJ10 GL04 GM04 GN08 GQ01 GR04 GT02 GT03 GV07 HC01 HC11 HC15 HC21
Claims (8)
ネルとする電界効果型トランジスタであって、チャネル
層の上にｎ型及びノンドープＡｌＧａＮ層の一方を、そ
の上に金属層を、さらにその上に絶縁体層を形成し、該
絶縁膜層と前記金属層とを１回のパターニングで開口
し、その開口部側壁に絶縁膜を形成してから該開口部に
金属を埋め込んでゲートを形成するようにしたことを特
徴とする電界効果型トランジスタ。1. A field-effect transistor having one of a GaN layer and an InGaN layer as a channel, wherein one of an n-type and non-doped AlGaN layer is provided on a channel layer, a metal layer is provided thereon, and a further metal layer is provided thereon. An insulating layer is formed, the insulating film layer and the metal layer are opened by one patterning, an insulating film is formed on the side wall of the opening, and a metal is buried in the opening to form a gate. A field-effect transistor characterized by the following.
の２層膜で形成するようにしたことを特徴とする請求項
１記載の電界効果型トランジスタ。2. The field effect transistor according to claim 1, wherein said metal layer is formed of a two-layer film of titanium and aluminum.
化膜を用いるようにしたことを特徴とする請求項１記載
の電界効果型トランジスタ。3. The field effect transistor according to claim 1, wherein the metal layer contains aluminum, and an anodic oxide film of aluminum is used as a method of forming the side wall of the opening.
層とノンドープＧａＮ層及びノンドープＩｎＧａＮ層の
一方とを交互に複数並べた層を用いるようにしたことを
特徴とする請求項１記載の電界効果型トランジスタ。4. An n-type AlGaN instead of the metal layer
2. The field effect transistor according to claim 1, wherein a plurality of layers are alternately arranged with one of a non-doped GaN layer and a non-doped InGaN layer.
ネルとする電界効果型トランジスタの製造方法であっ
て、チャネル層の上にｎ型及びノンドープＡｌＧａＮ層
の一方を形成する工程と、その上に金属層を形成する工
程と、さらにその上に絶縁体層を形成する工程と、該絶
縁膜層と前記金属層とを１回のパターニングで開口する
工程と、その開口部側壁に絶縁膜を形成してから該開口
部に金属を埋め込んでゲートを形成する工程とを有する
ことを特徴とする電界効果型トランジスタの製造方法。5. A method for manufacturing a field-effect transistor using one of a GaN layer and an InGaN layer as a channel, comprising: forming one of an n-type and a non-doped AlGaN layer on a channel layer; Forming a layer, further forming an insulator layer thereon, opening the insulating film layer and the metal layer by one patterning, forming an insulating film on the side wall of the opening. Forming a gate by burying a metal in the opening and then forming a gate.
の２層膜で形成するようにしたことを特徴とする請求項
５記載の電界効果型トランジスタの製造方法。6. The method according to claim 5, wherein the metal layer is formed of a two-layer film of titanium and aluminum.
化膜を用いるようにしたことを特徴とする請求項５記載
の電界効果型トランジスタの製造方法。7. The method according to claim 5, wherein the metal layer contains aluminum, and an anodic oxide film of aluminum is used as a method of forming the side wall of the opening.
層とノンドープＧａＮ層及びノンドープＩｎＧａＮ層の
一方とを交互に複数並べた層を用いるようにしたことを
特徴とする請求項５記載の電界効果型トランジスタの製
造方法。8. An n-type AlGaN instead of the metal layer
6. The method for manufacturing a field-effect transistor according to claim 5, wherein a layer in which a plurality of layers and one of a non-doped GaN layer and a non-doped InGaN layer are alternately arranged.
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|---|---|---|---|
| JP25968199A JP2001085670A (en) | 1999-09-14 | 1999-09-14 | Field effect type transistor and its manufacturing method |
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Family
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