JP2001185968A - Variable gain amplifying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent distortion characteristics from deteriorating by lowering base impedance. SOLUTION: The bias voltage of a 1st bias power source 41 is applied to the bases of 1st and 4th transistors 1 and 4 through a 5th transistor 5 which constitutes an emitter follower circuit and the bias voltage of a variable bias power source 43 is applied to the bases of 2nd and 3rd transistors 2 and 3 through a 6th transistor 6 which constitutes the emitter follower circuit. A 1st capacitor 21 is connected between the base of the 5th transistor 5 and a DC power source 30 and a 2nd capacitor 22 is connected between the base of the 6th transistor 6 and the DC power source 30. Consequently, a large- capacity capacitor is equivalently connected to the bases of the 1st to 4th transistors 1 to 4 and then the impedance becomes low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifying circuit for amplifying a signal in a high frequency band in a so-called TV tuner or BS tuner, and more particularly to a circuit for improving distortion characteristics.

[0002]

2. Description of the Related Art Conventionally, as this type of amplifying circuit, for example, a variable gain amplifying circuit having a configuration as shown in FIG. That is, the variable gain amplifier circuit will be described with reference to FIG.
First, this variable gain amplifier circuit includes two differential amplifier circuits 1
01 and 102. The first differential amplifier circuit 101 has first and second transistors 1 and 2 of npn type. The first and second transistors 1 and 2 have their emitters connected to each other. It is connected to the first constant current source 31 and the first input terminal 51. The collector of the first transistor 1 is connected to the DC power supply 30 via the first collector resistor 11a and to the first output terminal 53, while the collector of the second transistor 2 is It is directly connected to DC power supply 30. The second differential amplifier circuit 102 includes npn-type third and fourth transistors 3,
And third and fourth transistors 3, 4
Are connected to the second constant current source 32 and the second input terminal 52 while their emitters are connected to each other. The collector of the fourth transistor 4 is connected to the second
Is connected to the DC power supply 30 via the collector resistor 12a of the
Of the transistor 3 is directly connected to the DC power supply 30.

Further, first and fourth transistors 1, 4
The voltage divided by the first and second voltage dividing resistors 61 and 62 connected in series between the DC power supply 30 and the ground is applied to the
And the bases of the third transistors 2 and 3 are connected to a voltage of a variable bias power supply 43 configured such that an output voltage changes according to the magnitude of an input signal to the first and second input terminals 51 and 52. Is applied via a bias resistor 63. In the variable gain amplifying circuit having such a configuration, when the input signals at the first and second input terminals 51 and 52 are small, the voltage from the variable bias power supply 43 is applied to the first and second voltage dividing resistors 61. , 62, the first and fourth divided voltages are smaller.
The collector current of the transistors 1 and 4 flows. On the other hand, when the input signal becomes large, the voltage from the variable bias power supply 43 becomes the first and second voltage dividing resistors 61,
62, so that the first
And the collector currents of the fourth and fourth transistors 1 and 4 become smaller, while the collector currents of the second and third transistors 2 and 3 flow. When the input signal is large as described above, the current of the first and fourth transistors 1 and 4 becomes small, and the configuration is such that the amplification gain is controlled.

[0004]

However, in the above-described conventional circuit, the first to fourth transistors 1 to 4 are used.
4 has resistors 61, 62, 6 on its base.
3, the respective bias voltages are applied, so that the impedance with respect to the input signal from the emitter side is relatively high, so that the base bias of the first to fourth transistors 1-4 is reduced. There is a problem that the bias balance is easily lost and high frequency distortion is increased. The present invention has been made in view of such a situation, and has a low base impedance,
An object of the present invention is to provide a variable gain amplifying circuit having better distortion characteristics than the conventional one. Another object of the present invention is to provide a variable gain amplifier circuit having stable output characteristics regardless of the frequency of an input signal.

[0005]

In order to achieve the object of the present invention, a variable gain amplifier circuit according to the present invention has first and second transistors, each having an emitter connected to each other. A first differential amplifier circuit, a second differential amplifier circuit having third and fourth transistors, and having respective emitters connected to each other, wherein the first and second differential amplifier circuits are provided.
An input signal is applied between the emitter of the third transistor and the emitter of the third and fourth transistors. The collector of each of the first and fourth transistors is connected to the collector of each of the first and fourth transistors via an impedance element. 2nd and 3rd
The DC power supply voltage is directly applied to the collectors of the transistors, respectively. , A second bias voltage is applied to each of the first and fourth transistors, and an output signal is obtained between the collectors of the first and fourth transistors. The first bias voltage from the first bias power supply is applied to the base of the fourth transistor via a first base bias supply circuit configured as an emitter follower circuit. The second bias voltage from the second bias power supply is applied to the base via a second base bias supply circuit configured as an emitter follower circuit. The first base bias supply circuit, a first capacitor is connected between a base of a transistor constituting an emitter follower circuit and a DC power supply for outputting the DC power supply voltage, In the base bias supply circuit of
A second power supply is provided between the base of the transistor constituting the emitter follower circuit and the DC power supply for outputting the DC power supply voltage.
Are connected.

In such a configuration, the base bias supply circuit for supplying the base bias voltage of the transistors constituting the differential amplifier circuit is constituted by an emitter follower circuit. Since a capacitor is connected between the power supply and the power supply, the base of the transistor that constitutes the differential amplifier circuit has the capacitance represented by the capacitance C of the capacitor and the current amplification factor of the transistor in the emitter follower circuit. As a result, the base impedance of the transistors constituting the differential amplifier circuit is reduced as compared with the conventional case, and stable supply of the base bias is realized.

Further, a variable gain amplifier circuit according to the present invention
A first differential amplifier circuit having first and second transistors, each having an emitter connected to each other; and having a third and fourth transistor having each emitter connected to each other. A second differential amplifier circuit, and a balanced amplifier circuit for balancedly amplifying an input signal and outputting the amplified signal to the first and second differential amplifier circuits, and an emitter of the first and second transistors, , An input signal is applied between the emitters of the third and fourth transistors and the first and fourth transistors are applied.
The DC power supply voltage is directly applied to the collector of each of the transistors through the impedance element, and the DC power supply voltage is directly applied to the collectors of the second and third transistors, respectively. A first bias voltage is applied to the bases of the second and third transistors, and a second bias voltage is applied to the bases of the second and third transistors, respectively, between the collectors of the first and fourth transistors. A variable gain amplifier circuit configured to obtain an output signal, wherein a base of the first and fourth transistors is connected via a first base bias supply circuit configured as an emitter follower circuit. The first bias voltage from the first bias power supply is
And a second bias voltage from a second bias power supply is applied to a base of the third transistor via a second base bias supply circuit configured as an emitter follower circuit, and the first bias voltage is applied to the first transistor. In the base bias supply circuit, a first capacitor is connected between a base of a transistor forming an emitter follower circuit and a DC power supply that outputs the DC power supply voltage, and in the second base bias supply circuit, It is also preferable that a second capacitor is connected between the base of the transistor that forms the emitter follower circuit and the DC power supply that outputs the DC power supply voltage.

In such a configuration, except that the input signal is applied to the first and second differential amplifier circuits via the balanced amplifier circuit, differential operation is performed by the same operation as that of the variable gain amplifier circuit. The base impedance of the transistor constituting the amplifier circuit is low, and stable supply of the base bias is realized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. The same components as those in the conventional circuit shown in FIG. 6 are denoted by the same reference numerals. First, the basic circuit configuration of the variable gain amplifier circuit S1 according to the first invention will be described with reference to FIG. The variable gain amplifying circuit S1 includes first and second differential amplifying circuits 101 and 102 and first and second base bias supply circuits 201 and 202. That is, the first differential amplifier circuit 101
The first and second transistors 1 and 2 have npn-type first and second transistors 1 and 2. The first and second transistors 1 and 2 have emitters connected to each other, and have a first constant current source 31 and a first constant current source 31. Are connected to the input terminal 51 of the first embodiment. The collector of the first transistor 1 is connected to the DC power supply 30 via the first impedance element 11 and to the first output terminal 53, while the collector of the second transistor 2 is connected to the DC It is directly connected to the power supply 30.

The second differential amplifier circuit 102 has an np
It has n-type third and fourth transistors 3 and 4. The third and fourth transistors 3 and 4 have emitters connected to each other, and have a second constant current source 32 and a second Are connected to the input terminal 52 of the first embodiment. The collector of the fourth transistor 4 is connected to the DC power supply 30 via the second impedance element 12 and to the second output terminal 54, while the collector of the third transistor 3 is connected to the DC It is directly connected to the power supply 30.

The first base bias supply circuit 201 comprises:
A so-called emitter follower circuit is formed by using the npn-type fifth transistor 5, the first capacitor 21, and the first bias power supply 41 as a first fixed bias power supply as main components. I have. That is, the collector of the fifth transistor 5 is connected to the DC power supply 30.
, While the emitter is connected to the third constant current source 33 together with the bases of the first and fourth transistors 1, 4. The base of the fifth transistor 5 is connected to a first bias power supply 41 that outputs a predetermined first bias voltage, and a first capacitor 21 is connected between the first bias power supply 41 and the DC power supply 30. It has become something.

The second base bias supply circuit 20
Reference numeral 2 denotes a device in which a so-called emitter follower circuit is formed using the npn-type sixth transistor 6, the second capacitor 22, and the variable bias power supply 43 as main components. That is, the collector of the sixth transistor 6 is directly connected to the DC power supply 30, while the emitter is connected to the fourth constant current source 34 together with the bases of the second and third transistors 2 and 3. Also, the sixth
The base of the transistor 6 is connected to the variable bias power supply 43, and the second capacitor 22 is connected to the DC power supply 30. Here, the variable bias power supply 43 includes first and second input terminals 51,
The configuration is such that the output voltage changes according to the magnitude of the input signal applied to 52.

In the above configuration, the first capacitor 21 is provided between the DC power supply 30 and the base of the fifth transistor 5, and the second capacitor 22 is provided between the DC power supply 30 and the base of the sixth transistor 6. And the first capacitor 21 is connected to the fifth transistor 5
And the second capacitor 22 may be connected between the base of the sixth transistor 6 and the ground.

Next, the operation of this configuration will be described. The gain control of the first and second differential amplifier circuits 101 and 102 is performed in accordance with the magnitude of the input signal. The same is true. That is, first, when the input signals at the first and second input terminals 51 and 52 are small, the voltage of the variable bias power supply 43 becomes
The voltage becomes lower than the voltage of the first bias power supply 41, so that the collector currents of the first and fourth transistors 1 and 4 flow. In this case, the first bias voltage from the emitter of the fifth transistor 5 by the first bias power supply 41 is applied to the bases of the first and fourth transistors 1 and 4. , A second bias voltage from the variable bias power supply 43 is applied from the emitter of the sixth transistor 6.

On the other hand, when the input signal becomes large, the voltage of the variable bias power supply 43 becomes larger than the voltage of the first bias power supply 41, so that the collector currents of the first and fourth transistors 1 and 4 become small. The amplification gain is controlled according to the magnitude of the input signal. Here, when the emitter side of the fifth transistor 5 is viewed from the base side of the first and fourth transistors 1 and 4, the fifth transistor 5 is configured as a so-called emitter follower circuit. The grounded emitter current amplification factor of the transistor 5 is hfe1, the first capacitor 21
Let C1 be the capacitance of the capacitance, the capacitance appears to be approximately hfe1 times. That is, in other words, a state equivalent to a capacitor having a capacitance of hfe1 × C1 is connected between the bases of the first and fourth transistors 1 and 4 and the DC power supply 30. On the other hand, the sixth transistor 6 from the base side of the second and third transistors 2 and 3
The same applies to the case where the emitter side is viewed. That is, the sixth
Transistor 6 constitutes an emitter follower circuit, and is equivalent to a capacitor having a capacitance of hfe2 × C2 connected between the bases of the second and third transistors 2 and 3 and the DC power supply 30. It becomes a state. Here, hfe2 is the grounded emitter current amplification factor of the sixth transistor 6, and C2 is the capacitance of the second capacitor 22.

As described above, the base impedance of each of the first to fourth transistors 1 to 4 is equivalent to a state in which a large-capacity capacitor is connected to the base. Lower,
As a result, the bias applied to the base is stabilized, unlike the related art.

Next, a more specific circuit configuration example of the variable gain amplifier circuit S1 will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Hereinafter, different points will be mainly described. This figure 2
1 uses a first collector resistor 11a as the first impedance element 11 and a second collector resistor 12a as the second impedance element 12 in FIG. Otherwise, the circuit configuration is the same as that shown in FIG. Therefore, such a variable gain amplifier circuit S
The operation of 1a is basically the same as the example of the basic circuit configuration shown in FIG. 1, and therefore, the repeated explanation here will be omitted.

A typical distortion characteristic of the variable gain amplifier circuit S1a will be described in comparison with a conventional circuit with reference to FIGS. First, in FIG. 5 and FIG. 7, the gain control voltage on the horizontal axis corresponds to the variable gain amplifier s1.
a and the conventional circuit (see FIG. 6)
And the vertical axis indicates the level of the output voltage obtained between the first and second output terminals 53 and 54, and the vertical axis indicates the voltage applied by the variable bias power supply 43 applied to the bases of the third transistors 2 and 3. It is. In each of the characteristic diagrams, the characteristic line described as “received signal” indicates the level of the input signal applied to the first and second input terminals 51 and 52, and is described as “distortion signal”. The resulting characteristic line is
It shows the level of the output signal of the third-order intermodulation distortion component with respect to the input signal indicated by the characteristic line described as “received signal”. A comparison of the level of the distortion signal between the variable gain amplifier circuit S1a according to the present invention and the conventional circuit shows that the level of the distortion signal in the variable gain amplifier circuit S1a according to the present invention is particularly low in the range where the gain control voltage is small. Can be confirmed to be improved by about 20 dB compared to the conventional circuit, and it can be understood that the variable gain amplifier circuit S1a according to the present invention is effective in improving the distortion characteristics.

Next, the basic circuit configuration of the variable gain amplifier circuit S2 according to the second invention will be described with reference to FIG. The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. The variable gain amplifier circuit S2 includes first and second differential amplifier circuits 101 and 102, a balanced amplifier circuit 103, and first to third base bias supply circuits 201 to 203. It has become. That is, the first differential amplifier circuit 101 includes npn-type first and second transistors 1 and 2, and the first and second transistors 1 and 2 have emitters connected to each other. At the same time, it is connected to the collector of the seventh transistor 7 of the balanced amplifier circuit 103. The collector of the first transistor 1 is connected to the DC power supply 30 via the first impedance element 11 and to the first output terminal 53, while the collector of the second transistor 2 is connected to the DC It is directly connected to the power supply 30.

The second differential amplifier circuit 102 has an np
It has n-type third and fourth transistors 3 and 4. The third and fourth transistors 3 and 4 have emitters connected to each other and an eighth transistor 8 of the balanced amplifier 103. Connected to the collector. The collector of the fourth transistor 4 is connected to the DC power supply 30 via the second impedance element 12 and to the second output terminal 54, while the third transistor 4 is connected to the third output terminal 54.
Of the transistor 3 is directly connected to the DC power supply 30.

The balanced amplifying circuit 103 includes npn seventh and eighth transistors 7, 8, and the collectors of the seventh and eighth transistors 7, 8 are, as described above, the first and eighth transistors. While the emitters of the seventh transistor 7 are connected to the first constant current source 31 and the first input terminal 51, respectively. The emitter of the eighth transistor 8 is connected to the second constant current source 32 and the second input terminal 52. Further, the bases of the seventh and eighth transistors 7 and 8 are connected to each other, and are connected to a third base bias supply circuit 203 described later.

The first base bias supply circuit 201 comprises:
A so-called emitter follower circuit is formed by using the npn-type fifth transistor 5, the first capacitor 21, and the first bias power supply 41 as main components. That is, the collector of the fifth transistor 5 is directly connected to the DC power supply 30, while the emitter is connected to the third constant current source 33 together with the bases of the first and fourth transistors 1 and 4. The base of the fifth transistor 5 is connected to a first bias power supply 41 that outputs a predetermined first bias voltage,
The first capacitor 21 is connected between the DC power supply 30.

The second base bias supply circuit 20
Reference numeral 2 denotes a device in which a so-called emitter follower circuit is formed using the npn-type sixth transistor 6, the second capacitor 22, and the variable bias power supply 43 as main components. That is, the collector of the sixth transistor 6 is directly connected to the DC power supply 30, while the emitter is connected to the fourth constant current source 34 together with the bases of the second and third transistors 2 and 3. Also, the sixth
The base of the transistor 6 is connected to the variable bias power supply 43, and the second capacitor 22 is connected to the DC power supply 30. Here, the variable bias power supply 43 includes first and second input terminals 51,
The configuration is such that the output voltage changes according to the magnitude of the input signal applied to 52.

Further, a third base bias supply circuit 2
03 denotes an npn-type ninth transistor 9, a third capacitor 23, and a second fixed bias power source
A so-called emitter follower circuit is formed using the bias power supply 42 as a main component. That is, the collector of the ninth transistor 9 is directly connected to the DC power supply 30, while the emitter is connected to the fifth constant current source 35 together with the bases of the seventh and eighth transistors 7 and 8. The base of the ninth transistor 9 is connected to a second bias power supply 42 that outputs a predetermined third bias voltage, and the DC power supply 3
The third capacitor 23 is connected between 0 and 0.

In the above configuration, the first capacitor 21 is provided between the DC power supply 30 and the base of the fifth transistor 5, and the second capacitor 22 is provided between the DC power supply 30 and the base of the sixth transistor 6. And the third capacitor 23 is connected between the DC power supply 30 and the base of the ninth transistor 9, respectively, but the first capacitor 21 is connected between the base of the fifth transistor 5 and the ground. In the meantime, the second capacitor 22 is connected between the base of the sixth transistor 6 and the ground, and the third capacitor 23 is connected to the ninth transistor 6.
May be connected between the base of the transistor 9 and the ground.

In this configuration, except that the input signal is subjected to balanced amplification by the balanced amplifier circuit 103 and input to the first and second differential amplifier circuits 101 and 102, the basic operation is as shown in FIG. Since it is the same as the basic circuit configuration example shown in FIG. 1, a repeated description here will be omitted. Accordingly, the seventh and eighth transistors 7 and 8 also have the third base bias supply circuit 203 forming an emitter follower circuit as described above with reference to FIG. This is equivalent to a state in which a capacitor having a capacitance of hfe3 × C3 is connected to the bases of the seventh and eighth transistors 7, 8. Here, hfe3 is the grounded emitter current amplification factor of the ninth transistor 9, and C3 is the capacitance of the third capacitor 23.

As described above, a state equivalent to a state in which a large-capacity capacitor is connected to the base of each of the first to fourth transistors 1 to 4 and the seventh and eighth transistors 7 and 8 is achieved. Not only at a low frequency but also at a low frequency, the base impedance is low, so that the bias applied to the base is stabilized unlike the related art.

Next, a more specific circuit configuration example of the variable gain amplifier circuit S2 will be described with reference to FIG.
Note that the same components as those shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Hereinafter, different points will be mainly described. This figure 4
3 uses the first collector resistor 11a as the first impedance element 11 and the second collector resistor 12a as the second impedance element 12 in FIG. Other than that, the other circuit configuration is the same as that shown in FIG. Therefore, such a variable gain amplifier circuit S
The operation of 2a is basically the same as that of the basic circuit configuration example shown in FIG. 3, so that the description here will not be repeated.

In the configuration example described above, a fixed bias is applied to the first and fourth transistors 1 and 4, and a variable bias is applied to the second and third transistors 2 and 3, respectively. And vice versa. That is, the variable bias power supply 43 may be connected to the base of the fifth transistor 5, and the first bias power supply 41 may be connected to the base of the sixth transistor 6.

[0030]

As described above, according to the present invention,
By adopting a configuration in which the base impedance of the transistor constituting the variable gain amplifying circuit is lowered, unlike the related art, the instability of the base bias due to the high base impedance is eliminated, so that regardless of the frequency change of the input signal. As a result, a stable bias supply is performed, and therefore, unlike the related art, the deterioration of the distortion characteristic of the output signal is reduced, and an effect is provided that a variable gain amplifier circuit with good output characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic circuit configuration of a variable gain amplifier circuit according to a first invention.

FIG. 2 is a circuit diagram showing a more specific circuit configuration example of the variable gain amplifier circuit shown in FIG.

FIG. 3 is a circuit diagram showing a basic circuit configuration of a variable gain amplifier circuit according to a second invention.

FIG. 4 is a circuit diagram showing a more specific circuit configuration example of the variable gain amplifier circuit shown in FIG.

FIG. 5 is a characteristic diagram showing a level change of a distortion signal with respect to a gain control voltage of the variable gain amplifier circuit according to the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional circuit.

FIG. 7 is a characteristic diagram showing a level change of a distortion signal with respect to a gain control voltage of the conventional circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... 1st differential amplifier circuit 102 ... 2nd differential amplifier circuit 103 ... Balanced amplifier circuit 201 ... 1st base bias supply circuit 202 ... 2nd base bias supply circuit 203 ... 3rd base bias supply circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C026 BA11 5J100 AA14 BA06 BB01 BB11 BB21 BC02 CA01 CA20 CA33 DA06 EA03 FA04

Claims (9)

[Claims] 1. A first differential amplifier circuit having first and second transistors, each having an emitter connected to each other, and third and fourth transistors, each having an emitter. A second differential amplifier circuit connected to each other is provided; an input signal is applied between emitters of the first and second transistors and emitters of the third and fourth transistors; A DC power supply voltage is directly applied to the collectors of the first and fourth transistors, respectively, via the impedance element, and to the collectors of the second and third transistors, respectively. A first bias voltage is applied to the base of the fourth transistor, and a second bias voltage is applied to the bases of the second and third transistors, respectively. A variable gain amplifier circuit configured to obtain an output signal between respective collectors of a transistor, wherein a first follower circuit configured as an emitter follower circuit is provided at a base of the first and fourth transistors. The first bias voltage from the first bias power supply is applied to the bases of the second and third transistors via a base bias supply circuit.
The second bias voltage is applied by a second bias power supply via the base bias supply circuit of the first embodiment. In the first base bias supply circuit, the base of a transistor constituting an emitter follower circuit and the DC power supply A first capacitor is connected between the DC power supply that outputs a voltage, and in the second base bias supply circuit, a base of a transistor that forms an emitter follower circuit and a DC power supply that outputs the DC power supply voltage. Wherein a second capacitor is connected between the first and second capacitors. 2. A first constant current source is connected to emitters of the first and second transistors, a second constant current source is connected to emitters of the second and third transistors, One base bias supply circuit includes a fifth transistor having the same polarity as the first and fourth transistors, and an emitter of the fifth transistor is connected to a base of the first and fourth transistors. And a DC power supply connected to a third constant current source, a DC power supply voltage is applied to a collector of the fifth transistor, and a DC power supply for outputting the base of the fifth transistor and the DC power supply voltage. , A first capacitor is connected, a first fixed bias power supply for outputting a predetermined voltage is connected, and a second base bias supply circuit includes second and third transistors. And a sixth transistor having the same polarity as that of the sixth transistor. An emitter of the sixth transistor is connected to bases of the second and third transistors and connected to a fourth constant current source. A DC power supply voltage is applied to the collector of the sixth transistor, and a second capacitor is connected between the base of the sixth transistor and the DC power supply that outputs the DC power supply voltage. 2. The variable gain amplifier circuit according to claim 1, wherein a variable bias power supply whose output voltage changes according to the magnitude of the input signal is connected. 3. The variable gain amplifier according to claim 2, wherein the first fixed bias power supply is connected to the base of the sixth transistor, and the variable bias power supply is connected to the base of the fifth transistor. circuit. 4. A first differential amplifier circuit having first and second transistors, each having an emitter connected to each other, and a third and fourth transistor, each having an emitter. A second differential amplifying circuit connected to each other, and a balanced amplifying circuit for performing balanced amplification of an input signal and outputting the amplified signal to the first and second differential amplifier circuits; An input signal is applied between the emitter of the third transistor and the emitter of the third and fourth transistors. The collector of each of the first and fourth transistors is connected to the collector of each of the first and fourth transistors via an impedance element. A DC power supply voltage is directly applied to the collectors of the second and third transistors, respectively, and a first bias voltage is applied to the bases of the first and fourth transistors, respectively, to the second and third transistors. A variable gain amplifier circuit configured to apply a second bias voltage to a base of the first transistor and obtain an output signal between respective collectors of the first and fourth transistors. The first and second transistors receive the first and second bias voltages at the bases of the first and fourth transistors via a first base bias supply circuit configured as an emitter follower circuit. The base of the third transistor is connected to a second transistor configured as an emitter follower circuit.
The second bias voltage is applied by a second bias power supply via the base bias supply circuit of the first embodiment. In the first base bias supply circuit, the base of a transistor constituting an emitter follower circuit and the DC power supply A first capacitor is connected between the DC power supply that outputs a voltage, and in the second base bias supply circuit, a DC power supply that outputs the DC power supply voltage and a base of a transistor that forms an emitter follower circuit. Wherein a second capacitor is connected between the first and second capacitors. 5. The first base bias supply circuit according to claim 1, wherein:
And a fifth transistor having the same polarity as the fourth transistor, wherein the emitter of the fifth transistor is connected to the bases of the first and fourth transistors and to the third constant current source. On the other hand, a DC power supply voltage is applied to the collector of the fifth transistor, and a first capacitor is provided between the base of the fifth transistor and the DC power supply that outputs the DC power supply voltage. Is connected, a first fixed bias power supply that outputs a predetermined voltage is connected, and the second base bias supply circuit has a sixth transistor having the same polarity as the second and third transistors, The emitter of the sixth transistor is connected to the bases of the second and third transistors and connected to a fourth constant current source, while the sixth transistor A DC power supply voltage is applied to the collector of the DC power supply. A second capacitor is connected between the base of the sixth transistor and the DC power supply that outputs the DC power supply voltage. A balanced amplifying circuit to which a variable bias power source whose output voltage changes according to the magnitude is connected, has seventh and eighth transistors whose bases are connected to each other, and the collector of the seventh transistor is a first transistor. And the emitter of the second transistor, the collector of the eighth transistor is connected to the emitter of a third and fourth transistor, respectively, while the emitter of the seventh transistor is connected to a first constant current source. The emitter of the eighth transistor is connected to a second constant current source, and the emitter of the seventh transistor is connected to the eighth transistor. An input signal is applied between the first and second transistors, and a third bias voltage is applied to the bases of the seventh and eighth transistors via a third base bias supply circuit. The circuit includes a ninth transistor having the same polarity as the seventh and eighth transistors, and the emitter of the ninth transistor has:
While connected to the bases of the seventh and eighth transistors and to the fifth constant current source, a DC power supply voltage is applied to the collector of the ninth transistor, A third capacitor is connected between the base of the transistor and the DC power supply that outputs the DC power supply voltage, and a second fixed bias power supply that outputs a predetermined voltage is connected. The variable gain amplifier circuit according to claim 4, wherein 6. The variable gain amplifier according to claim 2, wherein the first fixed bias power supply is connected to the base of the sixth transistor, and the variable bias power supply is connected to the base of the fifth transistor. circuit. 7. The variable gain according to claim 2, wherein the first capacitor is connected between the base of the fifth transistor and the ground. Amplifier circuit. 8. The variable gain according to claim 2, wherein the second capacitor is connected between the base of the sixth transistor and ground. Amplifier circuit. 9. The variable gain amplifier circuit according to claim 5, wherein a third capacitor is connected between the base of the ninth transistor and ground.