JPH06232654A - Operational amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit configuration of a full differential amplifier circuit capable of fixing an in-phase potential at an output terminal to a desired value, low in the sensitivity against dispersion in the elements and high in in-phase gain. CONSTITUTION:Transistors(TRs) 10, 11, 33 form a differential pair and drains are respectively connected to drains of constant current source TRs 31, 32. Furthermore, drains of TRs 19, 20 whose gates are connected respectively to output terminals 72, 73 are connected in common and to a TR 17 in cascade and connected to a mirror circuit comprising TRs 16, 12 and 16, 6, drains of the TRs 6, 12 are connected respectively to drains of the differential pair and the drains are connected to drains of TRs 9, 15 whose gates connect to a reference potential point via TRs 8, 14 in cascode connection. TRs 22, 24 form an output stage and TRs 1-5 and a constant current source 50 form a bias circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit, and more particularly to an integrated circuit fully differential operational amplifier circuit.

[0002]

2. Description of the Related Art A conventional fully differential operational amplifier circuit has an input stage of a differential circuit, an output stage and a common mode feedback circuit connected in cascade as shown in FIG. 3 (for example, IEEE J.S.
solid-State Circuits. SC-1
7,969-982).

The circuit shown in FIG. 3 has a transistor 10
A differential circuit composed of 7, 108 and 111, an output stage of a cascode circuit composed of transistors 130 to 139 and an in-phase feedback circuit. Here, the transistor 103 and the constant current source 150 are a bias circuit.

Next, the operation will be described. Input terminal 1
The differential input signal applied to 60 and 161 is converted into a differential current by the input differential circuit and input to the output circuit of the next stage. Transistors 131 and 138, transistor 1
The gates of 32 and 137 and the transistors 133 and 136 are led to terminals 165, 166 and 167, respectively, and are biased to a constant voltage. Transistors 131 and 138,
The transistors 132 and 137 form a cascode circuit and have a high output impedance to obtain a large voltage amplification factor. Transistors 134 and 135
Since the drain-source voltage of is smaller than the gate-source voltage of each, it operates in the triode region.

For some reason, the output terminals 162,
If the common-mode potential of 163 increases, the ON resistances of the transistors 134 and 135 increase, and the current flowing through the transistors 132 and 137 decreases. Therefore, the potential of the output terminal tends to decrease. That is, it can be seen that it operates as a common-mode feedback circuit. Since this circuit has a differential input and a differential output, it is possible to suppress the influence on common-mode noise. Also, the dynamic range of the output signal is double that of the single-ended circuit, and the S / N
Against.

[0006]

In the conventional full differential operational amplifier circuit described above, it is difficult to fix the in-phase potential of the output terminals to a desired potential, and the sensitivity to element variation is high. Further, since the gain for the in-phase signal is low, there is a drawback that the degree of suppression of the in-phase noise is insufficient depending on the application.
Further, since the output portion has a structure in which transistors are vertically stacked in multiple stages, it is not suitable when the power supply voltage is low.

The object of the present invention is to eliminate these drawbacks.
An object of the present invention is to provide an operational amplifier circuit with high stability against element variations.

[0008]

According to a first operational amplifier circuit of the present invention, a differential pair having a gate led to an input terminal is provided, and a drain or a source of the differential pair is a source or a source. The first with the drain connected to the first power supply,
Connected to the drain or source of the second transistor,
The first and second transistors form a current mirror circuit with a third transistor whose source or drain is connected to the first power supply, and the gate and drain or source of the third transistor are cascode-connected. Via the fourth transistor, the drain or source is connected in common and the gates are connected to the drain or source of the fifth and sixth transistors respectively connected to the output terminal, the output of the differential pair, The gate is connected to the gates of the ninth and tenth output transistors via the cascode-connected seventh and eighth transistors, respectively, and the gate is connected to the third via the cascode-connected eleventh and twelfth transistors. It is connected to the drains or sources of the thirteenth and fourteenth transistors connected to the power source.

According to a second operational amplifier circuit of the present invention, in addition to the first operational amplifier circuit, the first and second operational amplifier circuits are further provided.
Fifteenth and sixteenth transistors are connected in parallel with the transistor of FIG. 5, and the gates of the fifteenth and sixteenth transistors are both connected to the fourth power supply.

[0010]

1 is a circuit diagram showing an operational amplifier circuit according to a first embodiment of the present invention. In FIG. 1, in the operational amplifier circuit according to the first embodiment, transistors 10, 11, 33 form a differential pair, and the drains of the differential pair respectively serve as drains of transistors 31, 32 which serve as constant current sources. It is connected to the. Further, transistors 16 and 12 and transistors 16 and 6 are formed via a transistor 17 in which the drains of the transistors 19 and 20 whose output terminals are connected to the gates are commonly connected and the drains are cascode-connected. Connected to the mirror circuit,
The drains of the transistors 6 and 12 of the mirror circuit are connected to the drains of the differential pair, respectively. Further, the drains of the differential pair are connected to the drains of the transistors 9 and 15 whose gates are connected to the reference potential via the cascode-connected transistors 8 and 14. The transistors 22 and 24 form an output stage, and the transistors 1 to 5 and the constant current source 50 form a bias circuit. A series body of resistors 60 and 62 and capacitors 61 and 63 is connected to the transistors 22 and 24, respectively.

With the configuration having the above characteristics, it is possible to perform in-phase feedback so that the in-phase potential of the output becomes the same potential as that of the third power source.

Next, the normal operation of this structure will be described. Transistors 10 and 11 forming the differential pair
The input terminals 70 and 71, and the input terminal 7
The input differential signals applied to 0 and 71 are amplified through the grounded-gate transistors 7 and 13 and the load transistors 8 and 14, and are further amplified by the output transistors 22 and 24 in the next stage, and the differential output terminals 72 and It is output from 73.

Next, the operation during in-phase feedback will be described. First, consider the case where the in-phase signal component of the differential output increases for some reason. At this time, the transistor 19,
If the drain potential of 20 is set low enough,
Since each operates in the triode region, the ON resistance of the transistor is small. Therefore, the transistors 19, 2
The zero drain current increases. The increased current is fed back to the output of the differential pair via the current mirror circuit composed of the transistors 6, 12 and 16.
The current fed back in this way is applied to the transistors 8, 14,
Since the currents of 9, 15, 33, 31, and 32 are fixed, they are superimposed on the signal to the output stage composed of the transistors 22 and 24, pushing up the gate potentials of the transistors 22 and 24, and The drain current, which is the output current, can be increased to lower the common mode potential of the differential output. At this time, the feedback is stable
The sum of the currents from the transistors 6 and 12 that give in-phase feedback to the currents from the transistors 31 and 32 that are responsible for the constant current source,
Load transistors 9 and 1 whose gates are fixed to the reference potential
It is when it is balanced with the current of 5. Transistor 9,
The fact that the gate of 15 is connected to the reference potential means that its current refers to the reference potential, that is, the common mode potential of the differential output can be uniquely determined by the reference potential. it can.

FIG. 2 is a circuit diagram showing an operational amplifier circuit according to the second embodiment of the present invention. In the second embodiment shown in FIG. 2, a transistor for supplying a bias current to the output of the differential pair and a transistor for supplying a feedback current are separately provided in the first embodiment. In the above embodiment, this is made common in order to suppress the influence of variations in elements.

That is, the transistors 31, 32, 3 of FIG.
3 is omitted and transistors 41 and 42 are added.
The other circuit parts are the same as those in FIG.

Therefore, the constant current source connected to the sources of the transistors 10 and 11 forming the differential pair is the transistor 42 whose gate is connected to the reference potential via the cascode-connected transistor 41. Book second
The operation of the second embodiment is the same as that of the first embodiment, and will be omitted.

[0017]

As described above, according to the present invention, the common mode signal of the fully differential operational amplifier circuit can be accurately fixed to a desired potential, and a sufficiently high common mode feedback gain can be easily obtained. Have.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an operational amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional operational amplifier circuit.

[Explanation of symbols]

1-42, 103, 107, 108, 111, 130-
139 transistor 60,62 resistance 61,63 capacitance 50,150 constant current source 70,71,160,161 input terminal 72,73,162,163 output terminal

Claims (2)

[Claims] 1. A first and second differential pair in which gates are respectively led to input terminals are provided, and a drain or a source of the differential pair has a source or a drain connected to a first power supply, respectively.
Connected to the drain or source of the second transistor,
The first and second transistors form a current mirror circuit with a third transistor whose source or drain is connected to the first power supply, and the gate and drain or source of the third transistor are cascode-connected. Via the fourth transistor, the drain or source is connected in common and the gates are connected to the drain or source of the fifth and sixth transistors respectively connected to the output terminal, the output of the differential pair, The gate is connected to the gates of the ninth and tenth output transistors via the cascode-connected seventh and eighth transistors, respectively, and the gate is connected to the third via the cascode-connected eleventh and twelfth transistors. An operational amplifier characterized by being connected to the drains or sources of the thirteenth and fourteenth transistors connected to the power supply of Circuit. 2. The operational amplifier circuit according to claim 1, wherein fifteenth and sixteenth transistors are connected in parallel with the first and second transistors, respectively, and gates of the fifteenth and sixteenth transistors are both gates. An operational amplifier circuit characterized by being connected to a fourth power supply.