JP2000298536A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power by properly reducing the frequency of a VRAM controlling clock without exerting visual influence upon the quality of display reproduction. SOLUTION: The information processor is provided with a clock control function for reducing the frequency of a VRAM control clock to a value capable of executing a display access when an access to a VRAM 24 is continued for fixed time and only a display access is executed or switching to a power down mode is generated by a power management function included in an operating system. Thus the control of the VRAM controlling clock can reduce the power consumption of the whole device while securing display quality for video reproduction or the like at a fixed level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a personal computer, and more particularly to a portable information processing apparatus which can be driven by a battery and requires power saving.

[0002]

2. Description of the Related Art In an information processing apparatus such as a personal computer, power management for power saving is performed by an operating system. In the power management by the operating system, for example, when no event occurs for a certain period of time, for example, the frequency of the operation clock of the CPU is reduced or the rotation of the hard disk is stopped, thereby realizing power saving.

However, a display processing system such as a video RAM is not subject to power management by an operating system, and is always supplied with a constant clock signal regardless of whether the display processing system operates. Therefore, it can be seen that very wasteful power consumption occurs here.
In particular, there is a strong demand for improving the power use efficiency of personal information devices such as PDA (Personal Digital Assistant) in which the length of battery operation time is one of the important specifications.

[0004]

As described above, reduction of power consumption is not sufficient only by conventional power management for power saving by an operating system in an information processing apparatus such as a personal computer. The display processing system is not a target, and always receives a constant clock signal and generates large power consumption.

The present invention has been made to solve such a problem, and provides an information processing apparatus capable of realizing optimal power management of a display control system including a VRAM and achieving further power saving. With the goal.

Another object of the present invention is to provide an information processing apparatus capable of appropriately reducing the frequency of a VRAM control clock without visually affecting the quality of display reproduction, thereby saving power.

[0007]

According to one aspect of the present invention, there is provided a memory for storing display data, and a clock for controlling a frequency of a control clock for the memory based on a state of a system. And control means.

According to a second aspect of the present invention, there is provided a memory for storing display data, monitoring means for monitoring an access state to the memory, and a control clock for the memory based on a monitoring result obtained by the monitoring means. Clock control means for switching the frequency.

According to the first and second aspects of the present invention, the status of the system and the status of access to the display memory include:
When a situation where a high-speed memory control clock is not required occurs, by controlling the frequency of the memory control clock to a value lower than the value in normal operation, the clock can be controlled without deteriorating the display quality. It is possible to realize power saving by the frequency reduction.

According to a third aspect of the present invention, there is provided an information processing apparatus comprising: a memory for storing display data; and means for stopping supply of a control clock for the memory during a blanking period of screen scanning. It is.

According to the present invention, the supply of the memory control clock is stopped during the screen retrace period during which the access to the display memory is interrupted, thereby realizing power saving for the clock supply stop time. Can be.

Further, the invention of claim 4 includes a memory for storing display data, and means for changing a frame rate for displaying the display data stored in the memory based on a state of the system. Features.

According to the present invention, when a situation where a high frame rate is not required occurs as a system state, power is saved by controlling the display frame rate to be switched to a value lower than a value in a normal operation. Can be realized.

According to a fifth aspect of the present invention, there is provided a memory for storing display data, and means for changing a frame rate for displaying the display data stored in the memory in accordance with the type of the started application. It is characterized by the following.

According to the present invention, when an application that does not require a high frame rate is started, power saving is realized by controlling the display frame rate to be switched to a value lower than a value in a normal operation. Can be.

According to a sixth aspect of the present invention, there is provided a memory for storing display data, input means for arbitrarily inputting an instruction to change a frame rate when displaying the display data stored in the memory, and input means for providing the instruction. Means for changing the frame rate in accordance with a given instruction.

According to the present invention, it is possible to switch between selection of a high-definition display at a high frame rate and selection of a display in consideration of power saving at a low frame rate, depending on selection from a user. Therefore,
For example, when the remaining capacity of the battery is low and the display considering power saving by the low frame rate is selected, the operable time of the battery can be extended.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a PDA according to an embodiment of the present invention.
1 shows an overall configuration of an information processing apparatus such as (Personal Digital Assistant).

As shown in FIG.
System memory (DRAM) 20, Processor (Proces)
sor) 21, power control circuit (Power Control) 22, M
It comprises a ROM 23, a VRAM 24, a keyboard controller (KBC) 25, and a device controller 26.

The system memory 20 is a memory that stores programs and data and is used as a work area of the processor 21. The processor 21 is a device that interprets and executes program instructions. The power supply control circuit 22 is a circuit for controlling a system power supply. The MROM 23 is a memory in which basic software of the system is stored. VRA
M24 is a memory for storing data to be displayed on the display device. The keyboard controller 25 is a device that controls a connected keyboard.

The device controller 26 includes a bus controller (Bus Controller) 1 and a display controller (LC).
D / CRT Controller 2, Graphics Accelerator 3, USB (Universal Serial Bu
s) Host controller 4, VRAM controller (V
RAM Controller) 5, PCMCIA Controller (P
CMCIA Controller 6, SmartMedia® controller 7, I / O bus controller 8, register interface bus 9, VRAM interface bus 10, clock controller A clock controller 11 and an interrupt controller 12 are provided.

The bus controller 1 is a device for controlling the internal bus of the device controller 26. The display controller 2 is a device that controls display on a display device such as an LCD panel or a CRT. The graphics accelerator 3 is a device that performs an auxiliary operation for speeding up a drawing process. The USB host controller 4 is a device that controls a connected USB device. VRAM controller 5
Is a device for controlling the VRAM 24. The PCMCLA controller 6 is a PCMCLA (Personal Computer Memo).
This is a controller that handles an interface with a PC card conforming to the ry Card International Association (ry Card). The smart media controller 7 is a controller that controls a connected flash memory. The I / O bus controller 8 is a controller that controls the keyboard controller 25 and connected expansion devices. The register interface bus 9 is an internal bus used for accessing internal registers. The VRAM interface bus 10 connects devices that access the VRAM 24. The clock controller 11 is a controller that selects a clock source and performs clock gating. The interrupt controller 12 is a controller that identifies an interrupt factor and controls its enable / disable.

FIG. 2 shows the configuration of the display controller 2 shown in FIG.

As shown in FIG.
Is an LCD (Liquid Crystal Display) controller 2
-1, DSTN (Dual Scan STN) controller 2-
2, a CRT controller 2-3, an LCD interface circuit 2-4, and a CRT interface circuit 2-5. The LCD controller 2-1 is a device that controls display on an LCD panel. The DSTN controller 2-2 is a device that controls display on a DSTN panel. The CRT controller 2-3 is a device that controls display on the CRT. The LCD interface circuit 2-4 is a device that changes the output format according to the type of LCD. The CRT interface circuit 2-5 is a device for converting a digital image signal into an analog image signal.

Next, the configuration of the LCD controller 2-1 will be described with reference to FIG.

As shown in FIG.
-1, display buffer 2-1-1, FIFO buffer memory 2-1-2, color palette 2-1-3, display address generation circuit 2-1-4, display timing generation circuit 2-
1-5, and a display data number counting circuit 2-1-6.

The display buffer 2-1-1 is a buffer for temporarily storing display data read from the VRAM 24. The FIFO buffer memory 2-1-2 is a memory for synchronizing display data from a clock signal used in the VRAM 24 to a clock signal for display.

The color palette 2-1-3 is a circuit for converting an index color into an RGB signal. The display address generation circuit 2-1-4 is a circuit for generating an address for reading display data from the VRAM 24. The display timing generation circuit 2-1-5 is a circuit that generates a display timing signal and a horizontal synchronization signal. Display data number counting circuit 2-
Reference numeral 1-6 denotes a circuit for counting the number of display data in units of horizontal scanning.

The configuration of the CRT controller 2-3 is the same as that of FIG.

Next, the operation of this embodiment will be described focusing on the control of the clock signal introduced to the display processing system.

In the present embodiment, the clock of monitoring the state of the system and lowering the frequency of the VRAM control clock to a value at which display access is possible when access to the VRAM 24 continues only for display for a certain period of time. It has a control function. This clock control function can be provided by, for example, basic software in the MROM 23. That the access to the VRAM 24 is only the display access means that the write access to the VRAM 24 does not occur. At the time of write access to the VRAM 24, such as during video playback, the clock speed directly affects the playback quality. However, when the access to the VRAM 24 is only display access, the clock speed is not required as much as during video playback.

The clock control function may be provided as a function of the operating system, or may be incorporated in the system as dedicated software stored in a storage device other than the MROM 23. A routine for lowering the frequency of the VRAM control clock to a value at which display access is possible by confirming by the basic software or the dedicated software that switching to the power down mode has occurred by the power management function of the operating system. May be adopted. Further, the clock control function may be provided as dedicated hardware.

When the clock control function determines that the access to the VRAM 24 has been a display access only for a certain period of time, the display controller 2 and the VRAM
The control is performed so that the VRAM control clock supplied to the controller 5 is changed to a preset power saving value lower than the normal value.

The VRAM control clock is supplied to the clock controller 11 inside the device controller 26, for example.
Generated by In this case, the frequency of the VRAM control clock is switched by giving a change command of the VRAM control clock to the clock controller 11 from the clock control function. Although a detailed description of the method of adjusting the clock frequency inside the clock controller 11 is omitted here,
There are various known systems using LL, dividers, and the like.

The present clock control function performs write access to the VRAM 24 while the VRAM control clock is down.
When an access other than the display access occurs (when the power down mode is released and the mode returns to the normal mode when linked with the power management function of the operating system), the down mode of the VRAM control clock is released and the normal mode is released. Return to clock frequency.

By controlling the VRAM control clock as described above, it is possible to reduce the power consumption of the entire apparatus while maintaining a constant display quality during video reproduction or the like.

Whether to enable the clock control function of the above embodiment may be selected depending on the state of the power supply of the information processing apparatus, that is, whether the power is supplied from a battery or supplied from a commercial power supply. That is, when power is supplied from the battery, the clock control function described above is made effective in order to extend the battery drive time.

Next, a second embodiment of the present invention will be described.

Usually, access to the VRAM 24 is substantially suspended during the horizontal retrace period of the screen scanning. Therefore, during the horizontal retrace period, the display buffer 2-1-1 of the LCD controller 2-1 and the display address generation circuit 2-1-4 are used.
May be stopped.

In order to realize such clock control, as shown in FIG. 3, a counting circuit 2-1-6 for counting the number of display data in units of horizontal scanning is added to the LCD controller 2-1. The counting circuit 2-1-6 reads out the data from the display buffer 2-1-1, and
The display data written in the buffer memory 2-1-2 during one horizontal scanning period is counted, and when the counted value becomes 0, that is, the last display data of one horizontal scanning is stored in the FIFO buffer memory 2-1-2. Is written, the VRAM control clock used in the display buffer 2-1-1 and the display address generation circuit 2-1-4 is stopped.
In this way, it is possible to reduce the power consumption of the VRAM control clock supplied to the LCD controller 2-1 during the horizontal retrace period. Here, the horizontal flyback period has been described, but the supply of the VRAM control clock to the LCD controller 2-1 may be stopped during the vertical flyback period.

Next, as a third embodiment of the present invention, a case in which a VRAM capable of dynamically switching a power-down state is used will be described with reference to FIG.

FIG. 4 is a diagram showing the configuration of the VRAM controller 5 for controlling such a VRAM 24. As shown in FIG. 1, the VRAM controller 5 includes a VRAM arbiter 5-1 and a VRAM control circuit 5-2.
Here, the VRAM arbiter 5-1 has a function of monitoring the access status to the VRAM 24 and notifying the result to the VRAM control circuit 5-2. VRAM control circuit 5
-2, when a monitoring result from the VRAM arbiter 5-1 is received and the monitoring result satisfies a certain condition, for example,
When only display access continues for a certain period of time, VR
The operation state of the AM 24 is controlled to be switched to the power down mode. At this time, the VRAM control circuit 5-2 outputs VR
By stopping the VRAM control clock supplied to the AM 24, it is possible to reduce the power consumption of the entire apparatus while maintaining a constant display quality during video reproduction or the like.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 5 shows the DSTN controller 2 of FIG.
2 illustrates the configuration of the -2. As shown in FIG.
The STN controller 2-2 includes an off-screen read buffer 2-2-1 for reading off-screen data from the VRAM 24 and an off-screen write buffer 2-2-2 for writing off-screen data of the next frame to the VRAM 24. And the dither pattern is VR
Dither pattern buffer 2 for reading from AM24
-2-3 and off-screen read buffer 2-2-1
From the off-screen data stored in the dither pattern buffer 2-2-3 and the dither pattern stored in the dither pattern buffer 2-2-3.
DSTN interface 2 for creating STN data
-2-4 and display data 2 input from the LCD controller 2-1 or the CRT controller 2-3 in FIG.
-10, 2-11 and a dither pattern controller 2-2-5 for performing dithering processing.

Here, a method for reducing power consumption by changing the frame rate will be described. The dither pattern is a pattern in which the gradation of a color (luminance) that cannot be expressed by one pixel is expressed by a combination of several pixels. The display quality of the dither pattern depends on the number of frames per second. That is, when displaying a dither pattern with high definition, it is necessary to increase the number of frames per second (frame rate). Conversely, when displaying coarsely, the frame rate is reduced. Generally, as the frame rate increases, the display quality improves, but the power consumption required for display increases.

Therefore, several selectable frame rates are prepared. For example, two frame rates are prepared, and the high frame rate and the low frame rate are switched according to the state of the system. When a high frame rate is used during a normal operation and the high frame rate is changed to a low frame rate, the state of the system may be such that when the access to the VRAM 24 is only a display access for a certain period of time and only the display access is performed, For example, when a power down mode is entered by the power management function, or when power is supplied from a battery.

As a method of setting the frame rate in the LCD controller 2-1, a display timing generation circuit 2-1-5 for generating a synchronizing signal for displaying on a display panel has a length of the horizontal retrace period of the video signal. How to change the setting value of a register (not shown)
There is a method of changing the frequency of the display clock signal used in the color pallet 2-1-3 for converting the index color into the RGB signal. This color palette 2
The frequency of the clock signal for display used in -1-3 is changed by a PLL circuit, a frequency dividing circuit and the like (not shown) inside the clock controller 11 of FIG. It is also possible to use these two methods in combination.

Further, as a method of switching the frame rate, there is a method of switching by activating or terminating a specific application software related to display quality, for example, an image viewer. There is also a method of switching a frame rate by operating a specific key on a keyboard by a user.

When a low frame rate is selected, the quality of the screen deteriorates, but the power consumption of the information processing apparatus can be reduced.

[0051]

As described above, according to the present invention, the status of the system and the status of access to the display memory are described as follows.
When a situation where a high-speed memory control clock is not required occurs, by controlling the frequency of the memory control clock to a value lower than the value in normal operation, the clock can be controlled without deteriorating the display quality. It is possible to realize power saving by the frequency reduction.

Further, according to the present invention, the supply of the memory control clock is stopped during the blanking period of the screen scanning in which the access to the display memory is interrupted, thereby saving power by the clock supply stop time. Can be realized.

Further, according to the present invention, when a situation in which a high frame rate is not required occurs as a system state, control is performed so that the display frame rate is switched to a value lower than the value in the normal operation. As a result, power saving can be realized.

Further, according to the present invention, when an application that does not require a high frame rate is activated, the display frame rate is controlled to be switched to a value lower than the value in the normal operation, thereby saving power. Can be realized.

In addition, according to the present invention, it is possible to switch between a high-definition display with a high frame rate and a display with consideration for power saving with a low frame rate, depending on the selection from the user. . Therefore, for example, when the remaining capacity of the battery becomes low, by selecting a display in consideration of power saving by the low frame rate, the operable time of the battery can be extended.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an entire information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a display controller of FIG. 1;

FIG. 3 is a diagram showing a configuration of the LCD controller of FIG. 2;

FIG. 4 is a diagram illustrating a configuration of a VRAM controller in FIG. 1;

FIG. 5 is a diagram illustrating a configuration of a DSTN controller of FIG. 2;

[Explanation of symbols]

 2 Display Controller 5 VRAM Controller 11 Clock Controller 20 System Memory 21 Microprocessor 24 Video RAM (VRAM) 2-1 LCD Controller 2-3 CRT Controller 2-4 LCD Interface Circuit 2-6 Video RAM Interface 2-1-1 Display Buffer 2-1-2 FIFO buffer memory 2-1-3 Color pallet circuit 2-1-6 Horizontal scanning counting circuit 5-1 Video RAM arbiter circuit 5-2 Video RAM control circuit

Claims (6)

[Claims] 1. An information processing apparatus comprising: a memory for storing display data; and clock control means for controlling a frequency of a control clock of the memory based on a system state. 2. A memory for storing display data, a monitoring unit for monitoring an access status to the memory, and a clock control for switching a frequency of a control clock of the memory based on a monitoring result obtained by the monitoring unit. And an information processing apparatus. 3. An information processing apparatus comprising: a memory for storing display data; and means for stopping supply of a control clock to the memory during a blanking period of screen scanning. 4. An information processing apparatus comprising: a memory for storing display data; and means for changing a frame rate for displaying the display data stored in the memory based on a system state. 5. An information comprising: a memory for storing display data; and means for changing a frame rate for displaying the display data stored in the memory in accordance with a type of an activated application. Processing equipment. 6. A memory for storing display data, input means for arbitrarily inputting an instruction for changing a frame rate when displaying the display data stored in the memory, and an instruction given by the input means. Means for changing a frame rate.