JP2006259240A - Liquid crystal display apparatus, drive circuit, drive method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid programming from becoming complicated, in a master device 20 for supplying data or signals to a display unit 40 including a liquid crystal panel. <P>SOLUTION: When a clock signal Clk-a is supplied, a drive control circuit 401 receives display data supplied from the master device 20, on the basis of a clock signal Clk-b from a PLL circuit 409 and controls the drive of a liquid crystal panel 420, in accordance with the clock signal Clk-b, as to become the display content specified by the received display data; and if the supply of the clock signal Clk-a is stopped, supplies display data for turning off all the pixels to the liquid crystal panel 420, at least over one vertical scanning period in accordance with a self-traveling signal from the PLL circuit 409. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a technique for controlling driving of a liquid crystal panel according to display data supplied together with a clock signal from a host device such as a main computer.

Since the liquid crystal element has a voltage holding property, a direct current component may be applied to the liquid crystal when the operation of the liquid crystal display device is stopped regardless of the display content. Since the liquid crystal deteriorates when a direct current component is applied, the voltage applied to the liquid crystal is zero (including a value near zero) in the liquid crystal display device.
After that, it is necessary to stop or interrupt the operation.
On the other hand, the gradation (brightness) of each pixel in the liquid crystal panel is defined by the display data,
The display data is supplied from a host device together with a clock signal for synchronization.

Here, when the host device stops or interrupts the display operation, in order to prevent the deterioration of the liquid crystal, after issuing a stop command to stop (or interrupt) the liquid crystal, it is applied to the liquid crystal of all pixels at least. It is necessary to continue supplying display data (off display data) that makes the voltage to be zero with the clock signal. For this reason, when issuing a stop command on the host device side, after issuing the stop command, from what timing and for what period, it is necessary to continue supplying the OFF display data and the clock signal. It becomes complicated because it has to be programmed.
For this reason, an oscillation circuit for generating an internal clock signal is provided on the liquid crystal display device side, and when the supply of the clock signal from the host device is interrupted for some reason, the internal clock signal is switched to display according to the internal clock signal. A technique for continuing the operation has been proposed (see Patent Document 1).
JP-A-8-254969

However, this technique requires an oscillation circuit separately, which not only complicates the configuration but also becomes an impediment to reducing power consumption by the power consumed by the oscillation circuit.
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display device having a simplified configuration while avoiding complicated programming on the host device side. A driving circuit, a driving method, and an electronic apparatus using the liquid crystal display device are provided.

In order to achieve the above object, according to the present invention, a synchronization signal generation circuit that generates a synchronization signal so as to be synchronized with a clock signal supplied from a host device, and the host device when the clock signal is supplied The display data supplied from the display device is received based on the synchronization signal, and the drive of the liquid crystal panel is controlled according to the synchronization signal so that the display content specified by the received display data is obtained, while the clock signal A drive control circuit that supplies display data for turning off all pixels to the liquid crystal panel when the supply is stopped according to a free-running signal in the synchronization signal generation circuit for at least one vertical scanning period; It is characterized by that. According to the present invention, since the driving of the liquid crystal panel is controlled according to the free-running signal of the synchronization signal generation circuit, a separate oscillation circuit is unnecessary. For this reason, in the present invention, it is possible to simplify the configuration while avoiding complicated programming on the host device side.

In the present invention, the drive control circuit supplies display data for turning off all pixels to the liquid crystal panel over at least one vertical scanning period according to a free-running signal in the synchronous new synthesis circuit. A configuration in which the self-running state of the synchronization signal generation circuit is stopped is preferable.
Further, in the present invention, a storage circuit that stores display data that defines display contents of a part of the display area of the liquid crystal panel, and the liquid crystal panel drive is stopped or interrupted from the host device. A clock signal generation circuit that generates an alternative clock signal that substitutes for the synchronization signal when an instruction is received, and the drive control circuit includes the self-running signal when the supply of the clock signal is stopped Instead, in accordance with the alternative clock signal, display data for turning off all pixels is supplied for at least one vertical scanning period, and thereafter
A configuration may be adopted in which the driving of the liquid crystal panel is controlled in accordance with the alternative clock signal so that the display content specified by the display data stored from the storage circuit is obtained.
The present invention is conceptualized not only as a driving circuit for a liquid crystal display device but also as a driving method for the liquid crystal display device, and further as the liquid crystal display device itself and an electronic apparatus having the liquid crystal display device. Is possible.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.
As shown in this figure, the liquid crystal display device 10 includes a host device 20 and a display unit 40.
It is divided roughly into. Among these, the host device 20 includes a CPU 21, a PS conversion circuit 23, transmission circuits 25 and 27, and a PLL circuit 29.

The CPU 21 executes various programs and outputs in parallel various commands, display data for defining pixel gradations, and the like. Here, the CPU 21 outputs various commands to the bus 56, and the display data and the synchronization signal for the PS conversion circuit 23.
To supply.
The PLL circuit 29 controls the signal frequency generated by the internal voltage controlled oscillation circuit so that the phase difference from the clock signal Clk-a input from the outside is eliminated. Therefore, P
The signal output from the LL circuit 29 can be regarded as the clock signal Clk-a itself.
The PS conversion circuit 23 is a circuit that converts display data and a synchronization signal output in parallel from the CPU 21 to serial in synchronization with a clock signal from the PLL circuit 29. The transmission circuit 25 differentially outputs serially converted display data and the like to the two lines 52. The transmission circuit 27 differentially outputs the clock signal output from the PLL circuit 29 to the two lines 54.

On the other hand, the display unit 40 is divided into a driver unit 400 and a liquid crystal panel 420. Among these, the driver unit 400 includes a drive control circuit 401 and an SP conversion circuit 403.
, Receiving circuits 405 and 407, PLL circuit 409, Y driver 430 and X driver 44
Contains zero.
The reception circuit 405 receives display data and the like that are differentially output, and the reception circuit 407 receives a clock signal that is differentially output.
The PLL circuit 409 controls the frequency of the signal Clk-b generated by the internal voltage controlled oscillation circuit so that the phase difference from the clock signal received by the receiving circuit 407 is eliminated. Therefore, the signal Clk-b output from the PLL circuit 409 can be regarded as the clock signal Clk-a as long as the clock signal Clk-a is received by the receiving circuit 407, but the reception of the clock signal Clk-a is interrupted. And a signal of a free-running frequency (free-running frequency) determined in advance in the internal voltage controlled oscillation circuit. Further, the PLL circuit 409 has a signal Off of H
When the level is reached, the oscillation of the signal Clk-b by the internal voltage controlled oscillation circuit is stopped.

The SP conversion circuit 403 separates the serial signal received by the receiving circuit 405 into the display data Data and the synchronization signal Sync, and converts the display data Data into the PLL circuit 409.
In parallel with the clock signal Clk-b.
In the present embodiment, the drive control circuit 401 mainly has the following four functions. That is, the drive control circuit 401 firstly displays the display data Data on the basis of the synchronization signal Sync and the X driver 4.
40, and secondly, the vertical scanning by the Y driver 430 and the horizontal scanning by the X driver 440 are controlled based on the synchronization signal Sync and the clock signal Clk-b, respectively.
Third, when various commands are received via the bus 56, and fourth, when a stop command for stopping the display operation is received among the various commands, the vertical belonging to the timing at which the stop command is received. The signal Off is set to the H level after two vertical scanning periods have elapsed since the end of the scanning period.

The Y driver 430 performs vertical scanning of the liquid crystal panel 420 under the control of the drive control circuit 401, and the X driver 440 performs horizontal scanning of the liquid crystal panel 420 under the control of the drive control circuit 401. is there. Note that the X driver 440 performs horizontal scanning.
Display data Data supplied from the drive control circuit 401 is converted into an analog voltage so as to be suitable for driving the liquid crystal.
In the liquid crystal panel 420, pixels are arranged in a matrix, and each pixel is a TFT (Thin
A method of switching by a film transistor (thin film transistor). The liquid crystal panel 420 is not limited to a TFT, and may be a method of switching pixels with a TFD (Thin Film Diode), or a passive matrix method that does not use these TFTs and TFDs. Also good. In any case, the types of the Y driver 430 and the X driver 440 are selected so as to be suitable for driving the liquid crystal panel 420.

Next, the operation of the liquid crystal display device 10 having such a configuration will be described. FIG. 2 is a timing chart for explaining the operation in the liquid crystal display device 10.
In the normal display state, the CPU 21 in the host device 20 outputs display data corresponding to the display content together with a synchronization signal. The display data and the synchronization signal are serially converted by the PS conversion circuit 23 in synchronization with the clock signal Clk-a, and the serial signal is differentially output to the two lines 52 by the transmission circuit 25, while the clock signal Clk-a is differentially output to the two lines 54 by the transmission circuit 27.

In the display unit 40, the receiving circuit 405 receives the serial signal differentially output to the two lines 52, and the receiving circuit 405 receives the clock signal differentially output to the two lines 54. Therefore, the clock signal Clk-b output from the PLL circuit 409 is the clock signal Clk.
The clock signal Clk-a used for serial conversion in the host device 20 is reproduced in the display unit 40. The SP conversion circuit 403 separates the received serial signal into display data Data and a synchronization signal Sync, and converts the display data Data into parallel in synchronization with the clock signal Clk-b.

The drive control circuit 401 outputs the display data Data based on the synchronization signal Sync and the clock signal Clk-b, and performs vertical scanning by the Y driver 430 and the X driver 44.
Horizontal scanning by 0 is controlled based on the synchronization signal Sync and the clock signal Clk-b, respectively (normal display). As a result, the liquid crystal panel 420 performs display based on the display data Data.
The synchronization signal Sync includes a horizontal synchronization signal. For convenience, FIG. 2 (FIG. 4 described later) is used.
However, only the vertical synchronization signal Vsync is shown in FIG. In addition, the number of display data Data during normal display is actually supplied in one-to-one correspondence with the pixels of the liquid crystal panel 420. In FIG. 2 (the same applies to FIG. 4 described later), this is the case. It has been simplified.

In the case of a normal display operation, a stop command Cmd that the CPU 21 stops the display operation as shown in FIG.
1, when issuing at a timing t _1, at time t ₂ after the genus to one vertical scanning period of the timing t ₁ is terminated, stops the clock signal Clk-a, the output of the display data Data and synchronizing signals. Therefore, in the display unit 40, the clock signal Clk-b by the PLL circuit 409, the timing t ₂ after the synchronization between the clock signal Clk-a becomes the signal of the free-running frequency off.

In the next vertical scanning period of one vertical scanning period belonging to the timing t ₁ to stop command Cmd1 is issued, the drive control circuit 401 in accordance with a clock signal Clk-b became free-running frequency, forcing all the pixels Supply OFF display data to the X driver 440 to turn it OFF (
Off-image display).
Here, since the off display data is uniquely determined in the liquid crystal panel 420, the host device 2
It is not necessary to supply from zero. For this reason, the drive control circuit 401, for example, displays the display data Dat.
All bits of a are forcibly fixed to “0” or “1”. For example, when the display data Data is 6 bits and 64 gradations can be displayed from “0” to “63”, the decimal value “
“0” defines the highest gradation white color, and as the decimal value increases, the gradation becomes darker.
63 ”defines the black of the lowest gradation, and when the liquid crystal panel 420 is in a normally white mode in which white display is performed with no voltage applied, the drive control circuit 401 sets“ 000000 ”(two Data in decimal notation) is supplied as off display data Data. By supplying such off-display data Data, in the liquid crystal panel 420, the voltage applied to the liquid crystal of each pixel is set to near zero.
Note that the frequency of the free-running state of the clock signal Clk-b is lower than that in synchronization with the clock signal Clk-a, and the frequency at which off-display data for all pixels can be supplied. Designed to be

When one vertical scanning period off display data is written to all the pixels is completed at a timing t _3, the drive control circuit 401 stops the supply of the display data to the liquid crystal panel 420 (stop operation). However, since the self-running state in the PLL circuit 409 is continued, the drive control circuit 401, the vertical scanning period for off the image display, further, a signal Off at timing t ₄ when after one vertical scanning period L Level. As a result, the oscillation operation of the internal voltage controlled oscillation circuit in the PLL circuit 409 is stopped, so that the clock signal Clk-b is not output thereafter. Thereby, the operation of the liquid crystal panel 420 is completely stopped (stopped).

Thus, in the present embodiment, when issuing the stop instruction Cmd1, the host device 20
End timing t ₂ of one vertical scanning period issuing timing t ₁ belongs the stop instruction Cmd1
Thus, the supply of the clock signal Clk-a may be stopped, and the off-image display operation for the liquid crystal panel 420 is executed based on the signal in which the PLL circuit 409 is in a free-running state in the display unit 40. For this reason, in the programming of the host device 20, the stop command C
After issuing md1, there is no need to specify the supply stop timing of the clock signal Clk-a in consideration of the off-image display operation, so that the programming in the host device side is avoided.
Furthermore, according to the present embodiment, since the off-image display is executed using the free-running clock signal in the PLL circuit 409, a separate oscillation circuit is unnecessary, which contributes to simplification of the configuration. it can. In addition, in the present embodiment, the timing t ₄ later, since stopping the oscillating operation of the internal voltage controlled oscillator in the PLL circuit 409, it also becomes possible to reduce power consumption up to resume the display operation.

Next, an application example of the above-described embodiment will be described. This application example is the liquid crystal display device 10.
In FIG. 3, so-called partial display driving is performed, and the configuration thereof is as shown in FIG.
In the liquid crystal display device 10 shown in FIG. 3, an OSC, an oscillation circuit (clock signal generation circuit) 411 that generates a clock signal Clk-c, and a RAM 413 are added to the configuration shown in FIG. In addition, the drive control circuit 401 includes a switch between the clock signal Clk-b and the clock signal Clk-c.
Here, the partial display drive is a drive in which, for example, as shown in FIG. 5, the liquid crystal panel 420 displays only a part of the region A and does not display in the other region B. Note that not displaying means that no voltage is applied to the liquid crystal, and in the normally white mode, white display is performed.

Further, display data defining the display contents in this area A is stored in the RAM 413. The RAM 413 has a storage area corresponding to each pixel in the area A. For this reason, R
The display data stored in the AM 413 is read from the corresponding storage area in accordance with the horizontal scanning of the area A and supplied to the X driver 440. In addition, this area A is an area where a slow display close to a still image is performed, and the stored contents of the RAM 413 are rewritten at a rate of once every 0.5 seconds, and the displayed contents Since the pixel content is binary content of pixel on or off (black or white), the transfer rate of the display data defining the display content of the area A can be low.
For this reason, the CPU 21 determines the display data that defines the contents to be displayed in the area A.
The data is supplied to the drive control circuit 401 via the bus 56, and the drive control circuit 401 is configured to write the display data in a corresponding storage area in the RAM 413.

The operation of the liquid crystal display device 10 according to the application example will be described with reference to FIG.
Since the operation in the display state is the same as that shown in FIG. 1, here, the operation when the partial display drive instruction is given in the display state will be mainly described.
CPU21 is, the instruction Cmd2 to the effect that the partial display driving, issuing at a timing _{t 11,} the drive control circuit 401, the instruction Cmd2, and received via the bus 56, the clock signal to the oscillator circuit 411 Instructs generation start of Clk-c.
Thereafter, CPU 21 at the timing t ₁₂ after the genus to one vertical scanning period of the timing t ₁₁ is finished, stops outputting the clock signal Clk-a and a synchronization signal. Therefore, in the display unit 40, the clock signal Clk-b by the PLL circuit 409, timing t ₁₂ after synchronization with the clock signal Clk-a becomes the signal of the free-running frequency off.
Also, CPU 21 sets the signal Enb to the H level at a timing _{t 12.} The signal Enb designates the use of the clock signal Clk-b if it is at the L level, and designates the use of the clock signal Clk-c if it is the H level. Therefore, the signal E at the timing _{t 12}
When nb becomes H level, the signal used for driving the liquid crystal panel 420 is switched from the clock signal Clk-b to the clock signal Clk-c.

In the next vertical scanning period of one vertical scanning period belonging to the timing t _11, the drive control circuit 401 in accordance with a clock signal Clk-c became free-running frequency, off display data in order to forcibly turn off all the pixels Is supplied to the X driver 440 (off-image display).
At the timing t ₁₃ to one vertical scanning period for the off-image display is completed, the drive control circuit 401, and a signal Off to H level, and stops the oscillating operation of the internal voltage controlled oscillator in the PLL circuit 409.
Further, at timing t ₁₃ , the drive control circuit 401 controls the Y driver 430 and the X driver 440 to scan only the region A based on the clock signal Clk-c, while the pixel to be scanned in the RAM 413. The display data is read from the storage area corresponding to, and supplied to the X driver 440 (RAM display). Thereafter, such an operation is repeated in each vertical scanning period (same as left).

In the liquid crystal display device 10 according to such an application example, a command Cmd for instructing partial display driving.
When issuing 2, the host device 20 may stop the supply of the clock signal Clk-a at the end timing t ₁₂ of one vertical scanning period to which the issue timing t _{11 of the} instruction Cmd 2 belongs. For this reason, in the programming of the host device 20, it is not necessary to specify the supply stop timing of the clock signal Clk-a in consideration of the operation for making the area B non-display after the instruction Cmd2 is issued. The complexity of side programming is avoided.
Further, the oscillation circuit 411 is separately required, but the state in which the oscillation with the PLL circuit 409 is simultaneously engaged is from the issue of the command Cmd2 to the start of the RAM display, and any one other than that. Further, the oscillation circuit 411 only has to generate the clock signal Clk-c at a frequency lower than that of the clock signal Clk-a, so that the power consumption does not increase so much.

In the liquid crystal display device 10 described above, the off-image display is performed in one vertical scanning period. The reason for the off-image display is to clear the state in which the voltage is applied to the liquid crystal according to the display contents so far. Since the voltage applied to the liquid crystal over all the pixels is zero or near zero, the off-image display may be performed over two vertical scanning periods or more.

Next, an electronic apparatus having the above-described liquid crystal display device 10 will be described. FIG. 6 is a perspective view showing a configuration of a mobile phone 1200 using the liquid crystal display device 10.
As shown in this figure, the cellular phone 1200 includes the liquid crystal panel 420 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. In the liquid crystal display device 10, components other than the liquid crystal panel 420 are built in the telephone, so that they do not appear as appearance.

Electronic devices to which the liquid crystal display device 10 is applied include digital still cameras, laptop computers, liquid crystal televisions, viewfinder type (or monitor direct view type) video recorders in addition to the mobile phone shown in FIG. , Car navigation device, pager, electronic notebook,
Examples include calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. And it cannot be overemphasized that the liquid crystal display device 10 mentioned above is applicable as a display apparatus of these various electronic devices.

1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to an embodiment of the present invention. 3 is a timing chart showing an operation of the liquid crystal display device. It is a block diagram which shows the application structure of the liquid crystal display device which concerns on embodiment. It is a timing chart which shows operation | movement of the liquid crystal display device which concerns on an application structure. It is a figure for demonstrating partial display drive. It is a figure which shows the structure of the mobile telephone using the liquid crystal display device which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 20 ... Host apparatus, 21 ... CPU, 40 ... Display unit, 401 ...
Drive control circuit 409 ... PLL circuit 420 ... Liquid crystal panel 430 ... Y driver 440
... X driver, 1200 ... mobile phone

Claims (6)

A synchronization signal generation circuit that generates a synchronization signal so as to be synchronized with a clock signal supplied from a host device;
When the clock signal is supplied, display data supplied from the host device is received based on the synchronization signal, and the display content specified by the received display data is set according to the synchronization signal. While controlling the drive of the LCD panel,
Drive control for supplying display data for turning off all pixels to the liquid crystal panel over at least one vertical scanning period according to a free-running signal in the synchronization signal generation circuit when the supply of the clock signal is stopped And a circuit for driving the liquid crystal display device. The drive control circuit includes:
Supplying the display data for turning off all pixels to the liquid crystal panel over at least one vertical scanning period in accordance with a free-running signal in the synchronization signal generation circuit, and then stopping the operation of the synchronization signal generation circuit. The drive circuit of the liquid crystal display device according to claim 1, wherein the drive circuit is a liquid crystal display device. A storage circuit for storing display data defining display contents of a partial area of the display area of the liquid crystal panel;
A clock signal generation circuit that generates an alternative clock signal that substitutes for the synchronization signal when an instruction to stop or interrupt the driving of the liquid crystal panel is received from the host device;
The drive control circuit includes:
When the supply of the clock signal is stopped, instead of the free-running signal, according to the alternative clock signal, supply display data for turning off all pixels over at least one vertical scanning period,
After this, the display content specified by the display data stored from the storage circuit is obtained.
The driving circuit of the liquid crystal display device according to claim 1, wherein driving of the liquid crystal panel is controlled according to the alternative clock signal. A method of driving a liquid crystal display device having a synchronization signal generation circuit that generates a synchronization signal so as to be synchronized with a clock signal supplied from a host device,
When the clock signal is supplied, display data supplied from the host device is received based on the synchronization signal, and the display content specified by the received display data is set according to the synchronization signal. While controlling the drive of the LCD panel,
When the supply of the clock signal is stopped, display data for turning off all pixels is supplied to the liquid crystal panel over at least one vertical scanning period according to a free-running signal in the synchronization signal generation circuit. A driving method of a liquid crystal display device. A liquid crystal display device comprising the drive circuit for the liquid crystal display device according to claim 1. A CPU for outputting display data;
A clock output circuit for outputting a clock signal for synchronizing with the display data;
A drive control circuit;
A liquid crystal display device comprising: a liquid crystal panel driven by the drive control circuit;
A synchronization signal generation circuit that generates a synchronization signal to synchronize with the clock signal output from the clock output circuit;
The drive control circuit includes:
When the clock signal is supplied, the display data supplied from the CPU is received based on the synchronization signal, and the display content specified by the received display data is set according to the synchronization signal. While controlling the drive of the LCD panel,
When the supply of the clock signal is stopped, display data for turning off all pixels is supplied to the liquid crystal panel over at least one vertical scanning period according to a free-running signal in the synchronization signal generation circuit. Features electronic equipment.

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