JP2000296655A - Image recorder and method for image recording - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make influence due to transferring delay inconspicuous when transferring of image data is delayed in the case of image recording. SOLUTION: An image recording comprises an image bus I/F controller 2021 for inputting image data by each line, a print buffer 2025 for storing the image data inputted from the image bus I/F controller 2021 and a printer 2095 that records an image by each line in accordance with the image data read from the print buffer 2025. When the image data in a line is not inputted from the image bus I/F controller 2021 within a determined time period, the image data in the line is invalidated and the image data in the line already outputted to the printer 2095 is reread from the print buffer 2025 to be outputted to the printer 2095.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus and an image recording method for inputting image data and recording an image based on the image data.

[0002]

2. Description of the Related Art There has been proposed an image processing apparatus capable of sharing a scanner, a printer, and a file system on a network by using a network interface.

In this case, devices such as a scanner, a printer, a memory, and a network interface for satisfying a user's request of the image processing apparatus are connected to a common system bus via dedicated interfaces, respectively, to meet user needs. In general, a configuration is used in which each device can be shared by selecting a function to be operated from a user interface and controlling data transfer on a system bus between devices realizing the selected function.

[0004]

In the above configuration, a common system bus is used for a plurality of device operations. Therefore, while any of the devices is using the system bus, other devices use the same system bus. This means that the device cannot perform data transfer via the system bus even if the device is accessed. If the data access cannot be performed, the access to the device is repeated until the data access is performed.

In such a system configuration, there is no problem in a configuration in which the time until data transfer is performed for an access does not affect the operation of the subsequent stage. For example,
This corresponds to an operation in which data read from a memory is processed in the system and then written in the memory again, or an operation in which data is transferred to a memory of an external device of the system through a network.

However, such as a printing operation using a printer that cannot be stopped halfway such as a laser beam printer,
When the operation of reading data from the memory via the system bus needs to be performed in real time without interruption, the data is read from the memory within a predetermined time in which the real time operation is possible in response to the access from the printer device. Need to come. Therefore, in such a case,
In such a configuration, there is a possibility that the accessed data is not output in accordance with the operation of the printer.

In this case, as a result of the printer output, not only a portion that is not printed out due to the delay of the data, but also the data transferred when the printer becomes accessible after that, is originally output. The data is output at a position shifted from the intended position, and the subsequent data is also output at the shifted position.

For example, let us consider a case where a shift (delay) of data of a plurality of pixels occurs during the output of a certain line when a printing operation for one page is performed. In this case, for that line, the original full line data is not output, and the latter half of the shifted pixels is output from the beginning of the next line, and the output of all subsequent lines is also output. The output of the line is shifted.

The present invention has been made in view of the above points, and has a configuration in which a common system bus is used. In contrast to a real-time operation for outputting an image from a memory to a printer, a read operation from a memory cannot be performed in time and a data transfer delay occurs. When the delay occurs, the effect of the transfer delay is made inconspicuous by performing the same data output as the previous line on the line on which the delay has occurred.

[0010]

That is, the image recording apparatus of the present invention comprises: an input unit for inputting image data line by line;
Storage means for storing image data input from the input means, and recording means for recording an image for each line based on the image data read from the storage means; If is not input within a predetermined time, invalidate the image data of the line,
The image data of the line already output to the recording means is read out again from the storage means and output to the recording means.

Further, in the image recording method according to the present invention, an inputting step of inputting image data line by line, a storing step of storing the image data input in the inputting step in a buffer memory, and reading out the image data from the buffer memory A recording step of recording an image on a line-by-line basis based on the received image data, and, if the image data of a certain line is not input within a predetermined time in the inputting step, the image data of the line is invalidated and already read out from the buffer memory. Reading out the image data of the line again from the buffer memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

[Overall Configuration] FIG. 1 shows the overall configuration.

The controller unit 2000 is connected to a scanner 2070 serving as an image input device and a printer 2095 serving as an image output device, while being connected to a local area network (LAN) 2011 and a public line (WAN) 2051. And a controller for inputting and outputting image information and device information.

The CPU 2001 is a controller for controlling the entire system. The RAM 2002 is a CPU 20
01 is a system work memory for operation, and is also an image memory for temporarily storing image data. The ROM 2003 is a boot ROM, and stores a system boot program. HDD 2004
Is a hard disk drive for storing system software and image data.

An operation unit I / F 2006 includes an operation unit (UI).
An interface unit with 2012 outputs image data to be displayed on the operation unit to the operation unit 2012. Also,
It plays a role of transmitting information input by the system user from the operation unit 2012 to the CPU 2001.

NETWORK 2010 is a LAN 201
1 to input and output information. MODEM2050
Is connected to a public line 2051 and inputs and outputs information.

The above devices are arranged on a system bus 2007.

The IMAGE BUS I / F 2005 is a bus bridge that connects the system bus 2007 and the image bus 2008 that transfers image data at high speed, and converts the data structure.

The image bus 2008 is a PCI bus or an I bus.
Connected by EEE1394. The following devices are arranged on the image bus 2008.

Raster image processor (RIP) 2
060 expands the PDL code into a bitmap image.

A device I / F unit 2020 connects the controller 2000 with a scanner 2070 or a printer 2095, which is an image input / output device, and generates a synchronous system for image data.
Perform asynchronous conversion.

The scanner image processing section 2080 corrects, processes, and edits input image data. The printer image processing unit 2090 performs printer correction, resolution conversion, and the like on print output image data.

The image rotation unit 2030 performs rotation processing on image data, and the image compression unit 2040 performs JPEG compression / expansion processing on multi-valued image data and JBIG compression or MMR on binary image data. , MH compression / decompression processing.

[Image Input Unit] FIG. 2 shows an image input / output device.
Shown in

A scanner 2070 as an image input device
Illuminates an image on paper serving as a document and scans it with a CCD line sensor (not shown), thereby converting the document image into electrical signals as raster image data 2071. After the document is set on the tray 2073 of the document feeder 2072, when the apparatus user gives an instruction to start reading from the operation unit 2012, the controller CPU 2001 gives an instruction to the scanner 2070 (2071).
Reference numeral 072 feeds the documents one by one, and an operation of reading an image of the fed document is performed.

Printer 2095 which is an image output device
Is a part for converting raster image data 2096 into an image on recording paper. The image forming method is an electrophotographic method using a photosensitive drum or a photosensitive belt. There is an ink-jet system for directly printing an image, and an arbitrary system is adopted.

The printing operation is started by the controller CP.
This is performed according to an instruction 2096 from U2001. The printer 2095 is provided with a plurality of paper feed stages so that different paper sizes or different paper orientations can be selected, and the corresponding paper cassettes 2101, 2102, 210
3, 2104 are mounted. Also, a paper discharge tray 2111
Is a portion for receiving the printed paper.

[Operation Unit] The structure of the operation unit 2012 is shown in FIG.

The LCD display unit 2013 is a display having a touch panel sheet affixed on a liquid crystal display panel. The LCD display unit 2013 displays an operation screen of the system, and when a displayed key is pressed, the position information is displayed on the controller. CPU2
Tell 001.

A start key 2014 is used for instructing, for example, starting a reading operation of a document image. In the center of the start key 2014, a two-color LED 2018 of green and red is provided.
Is provided, and the color indicates whether the start key is valid or invalid. A stop key 2015 is used to instruct to stop the operation in operation. An ID key 2016 is used to input a user ID of a user. A reset key 2017 is used to initialize various settings from the operation unit.

[Scanner Image Processing Unit] The configuration of the scanner image processing unit 2080 is shown in FIG.

The image bus I / F controller 2081 includes:
It is connected to the image bus 2008 to control the bus access sequence, and generates a control signal and a timing signal for controlling each device in the scanner image processing unit 2080.

The filter processing unit 2082 performs a convolution operation on the input image data using a spatial filter.

The editing unit 2083 recognizes, for example, a closed area surrounded by a marker pen on the document from the input image data, and performs shading, shading, negative / positive inversion, and the like on the image data in the closed area. Perform image processing.

When changing the resolution of the read image, the scaling unit 2084 enlarges or reduces the image in the main scanning direction by performing interpolation in the main scanning direction of the raster image. The magnification in the sub-scanning direction is changed by changing the scanning speed of the image reading CCD line sensor provided in the scanner 2070 in the sub-scanning direction.

The table 2085 is a table for converting image data, which is read luminance data, into density data.

The binarizing section 2086 binarizes the multi-value gray scale image data by error diffusion processing or screen processing.

The image data having undergone these processes meets the bus controller 2081 again, and the image bus 2008
Transferred on.

[Printer Image Processing Unit] FIG. 5 shows the configuration of the printer image processing unit 2090.

The image bus I / F controller 2091 includes:
It is connected to the image bus 2008 to control the bus access sequence, and generates a control signal and a timing signal for controlling each device in the scanner image processing unit 2090.

The resolution conversion unit 2092 has a NETWORK
The resolution conversion for converting the image data input from 2011 or the public line 2051 into the resolution of the printer 2095 is performed.

The smoothing processing unit 2093 performs a process of smoothing jaggies (roughness of an image appearing at a black-and-white boundary such as an oblique line) of the image data after resolution conversion.

[Image Compression Unit] FIG. 6 shows the configuration of the image compression unit 2040.

The image bus I / F controller 2041 is
It is connected to the image bus 2008 and controls the bus access sequence, the input buffer 2042 and the output buffer 204
5, timing control for exchanging data with
In addition, it controls the image compression processing unit 2043 such as mode setting.

The processing procedure of the image compression unit 2040 will be described below.

The CPU 200 via the image bus 2008
1 to the image bus I / F controller 2041 for setting for image compression control. With this setting, the image bus I /
The F controller 2041 provides the image compression processing unit 2043 with settings necessary for image compression (for example, MMR compression, J
BIG extension).

After making necessary settings, the CPU 20
From 01, the transfer of image data is permitted to the image bus I / F controller 2041. In accordance with this permission, the image bus I / F controller 2041 starts transferring image data from the RAM 2002 or each device on the image bus 2008.

The received image data is stored in the input buffer 20.
42 and temporarily stored in the image compression processing unit 20 at a constant speed in response to an image data request from the image compression processing unit 2043.
Image data is transferred to 43. At this time, the input buffer 2042 determines whether image data can be transferred between the image bus I / F controller 2041 and the image compression processing unit 2043, reads image data from the image bus 2008, and If writing of image data to the compression processing unit 2043 is impossible, control is performed so as not to transfer image data (hereinafter, such control is referred to as handshake).

The image compression processing unit 2043 temporarily stores the received image data in the RAM 2044. When performing image compression, image data for a plurality of lines may be required depending on the type of image compression processing to be performed. In such a case, compression of the image data for the first line is performed subsequently. This is because the operation cannot be started until image data for several lines is prepared.

The image data subjected to the image compression is immediately sent to the output buffer 2045. Output buffer 204
In 5, handshaking with the image bus I / F controller 2041 and the image compression processing unit 2043 is performed, and the compressed image data is transferred to the image bus I / F controller 204.
Transfer to 1. The image bus I / F controller 2041 transfers the transferred compressed (or decompressed) image data to the RAM 2002 or each device on the image bus 2008.

Such a series of processing is performed until there is no processing request from the CPU 2001 (when processing of the required number of pages is completed) or the image compression processing unit 204
3 is repeated until a stop request is issued (for example, when an error occurs during compression and decompression).

[Image Rotation Unit] The structure of the image rotation unit 2030 is shown in FIG.

The image bus I / F controller 2031 includes:
It is connected to the image bus 2008 and controls the bus sequence, controls the image rotation processing unit 2032 to set a mode and the like, and performs timing control for transferring image data to the image rotation processing unit 2032.

The processing procedure of the image rotation unit 2030 will be described below.

The CPU 200 via the image bus 2008
1 to the image bus I / F controller 2031 to make settings for image rotation processing. With this setting, the image bus I
/ F controller 2041 is an image rotation processing unit 2032
The user makes settings necessary for image rotation (for example, image size, rotation direction, angle, etc.).

After making the necessary settings, the CPU 20
01 permits image data transfer to the image bus I / F controller 2041. In accordance with this permission, the image bus I / F controller 2031 starts transfer of image data from each device on the RAM 2002 or the image bus 2008.

Here, the size of the image to be rotated in one process is set to 32 × 32 (bit), and when the image data is transferred to the image bus 2008, the size is set to 32 bi.
Image transfer is performed in units of t (the image to be handled is assumed to be binary).

As described above, in order to obtain a 32 × 32 (bit) image, image data must be transferred 32 times in the above-described unit, and image data must be transferred from a discontinuous address. is there.

The image data transferred by the discontinuous addressing is written to the RAM 2033 so that the image data is rotated at a desired angle at the time of reading. For example, if the rotation is 90 degrees counterclockwise, the first transmitted 32 bits
Is written in the Y direction and read out in the X direction at the time of reading, whereby the image is rotated.

Image rotation of 32 × 32 (bit) (RAM
After writing to the image bus I / F controller 232, the image rotation processing unit 2032 reads the image data from the RAM 2033 by the above-described reading method, and
The image is transferred to 031. The image bus I / F controller 2031 that has received the rotated image data transfers the image data to the RAM 2002 or each device on the image bus 2008 with continuous addressing.

Such a series of processing is repeated until there is no processing request from the CPU 2001 (when processing of the required number of pages is completed).

[Device I / F Unit] Device I / F Unit 2
020 is shown in FIG.

The image bus I / F controller 2021 is
It is connected to the image bus 2008, controls the bus access sequence, and generates a control signal and a timing signal for controlling each device in the device I / F unit 2020. Also, it generates control signals to external scanner 2070 and printer 2095.

The scan buffer 2022 is connected to the scanner 2
070 is temporarily stored, and the image data is output in synchronization with the image bus 2008.

The serial / parallel / parallel / serial converter 2023 arranges or decomposes the image data stored in the scan buffer 2022 in order, and converts it into a data width of image data that can be transferred to the image bus 2008.

The parallel-serial-to-serial / parallel converter 2024 decomposes or arranges the image data transferred from the image bus 2008 into a data width that can be stored in the print buffer 2025.

The print buffer 2025 is connected to the image bus 2
008 is temporarily stored, and the image data is output in synchronization with the printer 2095.

The processing procedure at the time of image scanning will be described below.

The image data sent from the scanner 2070 is stored in the scan buffer 2022 in synchronization with the timing signal sent from the scanner 2070.

In the case where the image bus 2008 is a PCI bus, when image data enters the scan buffer 2022 by 32 bits or more, the image data is stored in the scan buffer 2 by 32 bits in a first-in first-out (FIFO) manner.
022 to the serial / parallel / parallel / serial conversion unit 2023 to convert the image data into 32-bit image data.
008.

The image bus 2008 is connected to the IEEE 139
In the case of 4, the image data in the buffer is sent from the scan buffer 2022 to the serial / parallel / parallel / serial conversion unit 2023 on a first-in first-out (FIFO) basis.
The image data is converted into serial image data and transferred to the image bus 2008 via the image bus I / F controller 2021.

The procedure for printing an image is described below.

When the image bus 2008 is a PCI bus, 32-bit image data sent from the image bus 2008 is received by the image bus I / F controller 2021 and the parallel serial / serial / parallel converter 20
24, the image data is decomposed into image data of the number of input data bits of the printer 2095, and stored in the print buffer 2025.

The image bus 2008 is connected to the IEEE 139
In the case of No. 4, the serial image data sent from the image bus 2008 is transferred to the image bus I / F controller 2021.
And sends it to a parallel / serial / serial / parallel conversion unit 2024 to convert it into image data of the number of input data bits of the printer 2095,
To save.

The print buffer 20 is synchronized with the timing signal sent from the printer 2095.
The printer 209 stores the image data in the printer 25 in a first-in first-out manner.
Send to 5.

[Printer Operation] The configuration of the printer operation will be described below.

FIG. 9 is a block diagram of the print buffer 2025 shown in FIG.

The print buffer 2025 has two FIFOs (referred to as FIFO1 and FIFO2, respectively). As control signals, an input enable signal (WEN1) and an output enable signal (REN) for FIFO1 are provided.
1), the input reset signal (WRST1), the output reset signal (RRST1), and the corresponding signals WEN2, REN2, WRST2, R
RST2 is prepared.

FIFOs 1 and 2 have parallel serial
Output data of the serial / parallel converter 2024 is input, and output data of the FIFOs 1 and 2 are sent to the printer 2095.

Along with the output of the image data from the parallel / serial / serial / parallel conversion unit 2024, a signal having the same width as the section in which the image data is being output is output at the same timing. These signals are used as input enable signals WEN1 and WEN2 of the FIFOs 1 and 2, and input control is performed.

As shown in FIG. 10A, the FIFO
The output of image data from the printers 1 and 2 corresponds to VCLK (Video Clock) output from the printer 2095 and H
This is performed according to SYNC. VCLK is continuously output, and HSYNC is given in synchronization with the start of recording of one line of the printer 2095.

One line of image data read out from the FIFOs 1 and 2 is data of an image width or the number of pixels (WIDTH) that can record one line of image set in advance for each printer. Output to the printer 2095. The timing of WIDTH is FIFO
1 and 2 correspond to the output enable signal REN.

As shown in FIG. 10 (2), after this read operation is repeated for a specified number of lines (LINES),
The reading is completed.

The FIFO1 and FIFO2 switch the read / write operation in accordance with HSYNC. Therefore, WRST1, RRST1, WRST2, RRS
The HSYNC signal is used as the T2 signal.

By alternately outputting the REN signal by the selector or the like at the timing of HSYNC, the REN signal shown in FIG.
The REN1 and REN2 signals are as shown in FIG.

Similarly, the WEN1 and WEN2 signals are
The signals are generated by alternately outputting the signals at the timing shown in FIG. Since the waveform of the WEN signal cannot be specified, it is not shown in the figure.

In FIG. 9, the FIFO1 signal is output by the WEN1 signal.
Is input by REN1 after 1 HSYNC. H when FIFO1 is performing input operation
In the SYNC period, FIFO2 performs an output operation by REN2, and switches to an input operation by the next HSYNC.
Thereafter, the operation of the FIFO is repeated until the lines for the LINES section are output to the printer 2095.

Also, since FIFOs 1 and 2 are configured to output only in the width of WIDTH, WI in the HSYNC section
When data exceeding the DTH width is input to the FIFOs 1 and 2, the excess data is not output. Therefore, by providing the pixel count circuit shown in FIG. 12, the operation of counting the number of pixels input to the FIFOs 1 and 2 is performed, and control is performed so that data exceeding the WIDTH width is not input to the FIFOs 1 and 2.

That is, in the configuration shown in FIG. 12, the clock input of VCLK, WEN as an enable signal, and HSYNC as a reset signal are input to the counter 501. You. Further, the output value of the counter 501 and the WI
The value of DTH is compared, and the value of counter 501> WIDT
When the signal becomes H, the input operation to the FIFO is stopped, and the parallel / serial / serial / parallel conversion unit 202 is stopped.
The control for stopping the output operation of No. 4 is performed.

On the other hand, the FIFO performing the write operation
If data for WIDTH is not input to the first and second HSYNC sections, data for WIDTH cannot be output due to REN in the next HSYNC section. WID
As a result of not outputting the data for TH, the transfer of data for the number of pixels less than the WIDTH width occurs for the line.

The situation in which data for WIDTH is not input in such an HSYNC section is caused by the image bus I / F shown in FIG.
When the controller 2021 accesses the memory via the image bus 2008 and the system bus 2007,
This is due to a delay in data transfer from the memory due to the influence of other devices.

FIG. 14 shows an output example. The grids in the figure indicate the pixels constituting the image, and one grid corresponds to one pixel. FIG. 14A shows an image to be originally output.
FIG. 14 (2) shows an example of an undesired output when the above-mentioned transfer shift occurs, and 141 indicates a transfer shift (delay).
, And in this example, an output shift of four pixels has occurred. Reference numeral 142 denotes a state in which pixels corresponding to the transfer deviation in the latter half of all lines are output to the next line due to the influence of transfer deviation of all lines.

To cope with such a problem, the image bus I / F controller 2021 operates the counter 501 by the comparator 502 when reading data from a certain FIFO.
Is monitored and the result of comparison between WIDTH and WIDTH is monitored to determine whether or not image data for one line has been input within a predetermined time. In other words, at the end of the HSYNC section, if the output of the comparator 502 satisfies the value of the counter 501 <WIDTH, it is recognized that the image data for one line has not been input within the predetermined time, and in the next HSYNC, FIFO
1. The same FIFO is used again without switching the operation of FIFO2.
An output operation is performed from O, and an input operation is performed to the same FIFO in which data has been written in the previous HSYNC interval.

At the same time, the address for outputting the image data from the RAM 2002 is changed from the address of the data of the line which has been accessed so far to the head address of the data of the next line, and the next FIFO is used for the input operation. Input data of the line.

With the above configuration, with respect to the real-time operation of the printer 2095, regarding the line in which the data transfer from the memory (RAM 2002) has been delayed, the data of the line with the delayed data transfer is invalidated.
Using the same data as the previous line, the printer 209
5 is output, and for subsequent lines, the line output of the original image is performed. When such a data transfer delay occurs again, the same operation is repeated to avoid the data transfer deviation shown in the present embodiment and to minimize the influence of the transfer delay as the output result of the entire page. It can be made less noticeable.

FIG. 14C shows an output example when the above output correction is performed. In the figure, reference numeral 143 denotes a line to which the same data as the previous line has been output by the above control.

FIG. 13 is a flowchart showing the operation of the image bus I / F controller 2021 in the printer operation described above.

When the operation of the printer 2095 becomes possible,
An HSYNC signal is output from the printer 2095 (step 601). Image bus I / F controller 2021
When receiving the HSYNC signal, the memory (RAM 200
From 2), reading of image data is started from the start address of the first line of the image (step 602). RAM
The image data read from the memory 2002 is stored in the FIFO buffer 2025 shown in FIG.
(Step 603). At this time, FIFO
It is optional whether the signal is input to the FIFO1 or the FIFO2.

When the input of image data to the FIFO is started, the count of the number of input pixels is started by the counter 501, and the counter 5 is output before HSYNC = "H" is output.
If the output of 01 becomes larger than the predetermined value WIDTH (step 604), the input operation to the FIFO is stopped (step 605), and the read operation from the memory 2002 is also stopped (step 606).

When HSYNC = “H” is received (step 607), the reading of image data from the memory 2002 is started from the head address of the next line (step 608), and the F which has been input data up to that point is read out.
A data read operation is started from the IFO,
The operation of writing data from the memory 2002 to the other FIFO is started (step 609) (step 61).
4).

At step 604, if the value of the counter 501 is equal to or less than WIDTH, after receiving HSYNC = “H” (step 610), reading of image data from the memory 2002 starts from the head address of the next line. At this point, if the value of the counter 501 is the same as the value of WIDTH, the process proceeds to step 60.
Move to operation 9.

If the value of the counter 501 is smaller than WIDTH, the image data is again input to the FIFO that has been input up to that point, and the image data is output again from the FIFO from which the image data was output. Is output (step 613).

With the above configuration, the input / output operation of the FIFO is started (step 614), and the predetermined number of lines (LI
(NES) is repeated (step 61).
5) The read operation from the memory 2002 is stopped (step 616), and after the output operation from the FIFO is stopped (step 617), when all the data is printed out by the printer 2095, the print operation is stopped. .

Although the present embodiment has been described using the double buffer configuration, the input can recognize the delay of the data transfer based on the count and output the previous line to avoid the problem. Needless to say, any buffer configuration may be adopted.

[0106]

As described above, according to the present invention,
When image data is input for each line, the input image data is stored, and an image is recorded for each line based on the read image data, if image data of a certain line is not input within a predetermined time, the line Is invalidated, and the image data of the already output line is read out again. Therefore, if the transfer of the image data is delayed, the data output of the delayed line is the same as that of the previous line. , The effect of the transfer delay can be made inconspicuous.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a system to which the present invention is applied.

FIG. 2 is a schematic view of a scanner unit and a printer unit.

FIG. 3 is a schematic view of an operation unit.

FIG. 4 is a block diagram of a scanner image processing unit.

FIG. 5 is a block diagram of a printer image processing unit.

FIG. 6 is a block diagram of an image compression unit.

FIG. 7 is a block diagram of an image rotation processing unit.

FIG. 8 is a block diagram of a device I / F.

FIG. 9 is a block diagram of a print buffer.

FIG. 10 is a timing chart illustrating transmission timing of image data in the printer.

FIG. 11 is a timing chart showing the timing of FIFO read / write.

FIG. 12 is a block diagram of a pixel number counting circuit.

FIG. 13 is a flowchart showing the operation of the image bus I / F controller;

FIG. 14 is a diagram showing an example of image output.

[Explanation of symbols]

 Reference numeral 501 Counter 502 Comparator 2002 Memory RAM 2008 Image bus 2020 Device I / F 2095 Printer 2021 Image bus I / F controller 2025 Print buffer 2095 Printer

Claims (12)

[Claims] An input unit for inputting image data for each line; a storage unit for storing the image data input from the input unit; and an image recording unit for each line based on the image data read from the storage unit. Recording means,
If image data of a certain line is not input within a predetermined time by the input unit, the image data of the line is invalidated, and the image data of the line already output to the recording unit is read out again from the storage unit, and An image recording apparatus for outputting to an image recording apparatus. 2. An apparatus according to claim 1, further comprising a recognition unit configured to recognize whether or not image data of each line is input within a predetermined time by said input unit, wherein image data of a certain line is not input within a predetermined time by said recognition unit. 2. The method according to claim 1, wherein when it is recognized that the image data of the line is invalidated, the image data of the line already output to the recording unit is read out again from the storage unit and output to the recording unit. The image recording apparatus according to claim 1. 3. The apparatus according to claim 2, wherein said recognizing means recognizes whether or not the image data of each line is input by the input means within a time required for recording of one line by the recording means. The image recording apparatus according to claim 1. 4. The apparatus according to claim 3, wherein said recognizing means has a comparing means for comparing the number of pixels of the image data inputted by said input means with the number of recording pixels of one line.
The image recording apparatus according to claim 1. 5. The image recording apparatus according to claim 1, further comprising storage means for storing image data used for image recording, wherein said input means inputs image data read from said storage means. apparatus. 6. The image data read from the storage unit is transferred to the input unit via a bus to which another device that inputs and outputs image data is connected. The image recording apparatus according to claim 1. 7. An input step of inputting image data line by line, a storage step of storing the image data input in the input step in a buffer memory, and an image data read line by line based on the image data read from the buffer memory. If the image data of a certain line is not input within a predetermined time in the inputting step, the image data of the line is invalidated, and the image data of the line already read from the buffer memory is stored in the buffer. Reading from the memory again. 8. A recognition step for recognizing whether or not image data of each line is input within a predetermined time in the input step, wherein image data of a certain line is not input within a predetermined time in the recognition step. 8. When it is recognized that the image data of the line is invalidated in the reading step, the image data of the line already read from the buffer memory is read again from the buffer memory. Image recording method. 9. The image according to claim 8, wherein in the recognizing step, it is recognized whether or not the image data of each line is input within a time required for recording one line in the inputting step. Recording method. 10. The image recording apparatus according to claim 9, wherein the recognizing step includes a comparing step of comparing the number of pixels of the image data input in the input step with the number of recording pixels of one line. Method. 11. The image processing apparatus according to claim 7, further comprising a storage step of storing image data used for image recording in an image memory, wherein in the inputting step, the image data read from the image memory is input. Image recording method. 12. The image data read from the image memory is input in the input step via a bus to which another device for inputting / outputting image data is connected. The image recording method described in 1.