JP2000228447A - Semiconductor integrated circuit design device, its wiring control method and memory medium wherein wiring control program is stored - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design device of a semiconductor integrated circuit which carries out wiring not to exceed the total wiring capacity decided arbitrarily by calculating the total wiring capacity and carrying out wiring while recognizing it. SOLUTION: This device 10 has a three-dimensional region setting part 12 which sets a three-dimensional region for carrying out wiring for each wiring to a semiconductor integrated circuit which is a design object, a priority decision part 13 which decides the order of priority of wiring operation of each wiring arbitrarily, a total wiring capacity decision part 14 which decides the total wiring capacity for each wiring arbitrarily, a layout execution part 15 which carries out wiring operation for each set three-dimensional region according to the set priority, and a layout evaluation part 16 which evaluates wiring result whenever the layout execution part 15 completes wiring operation to one three-dimensional region and controls the total wiring capacity of each wiring not to exceed the predetermined total wiring capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit designing apparatus, and more particularly to a semiconductor integrated circuit designing apparatus capable of setting a wiring capacitance included in a semiconductor integrated circuit to an arbitrary value, a wiring control method thereof, and a wiring control. The present invention relates to a storage medium storing a program.

[0002]

2. Description of the Related Art Transistor arrangement and wiring work in the design of a semiconductor integrated circuit include transistor dimensions determined based on the design criteria of the semiconductor integrated circuit to be designed.
First, a transistor circuit is arranged using data representing a layout such as a wiring width and a contact size (hereinafter, referred to as layout data), and then each wiring operation (connection) corresponding to the transistor is performed. Then, after the completion of the wiring work, a wiring load connected to the output side of each transistor is calculated. As a method of calculating the wiring load, as disclosed in, for example, Japanese Patent No. 2800881, a region where a transistor is arranged and wired in a semiconductor integrated circuit (hereinafter referred to as a layout region) is a three-dimensional region (three-dimensional). By handling, it is possible to calculate accurately.

Next, based on the calculated wiring load, it is confirmed whether or not the wiring capacity satisfies a desired operation delay time corresponding to each transistor. In this confirmation operation, if it is confirmed that the wiring capacity satisfies the desired operation delay time, the placement and wiring work are terminated.

On the other hand, if it is confirmed that the wiring capacitance does not satisfy the desired operation delay time, the operation is performed again from the arrangement of the transistors or the wiring after the transistors are arranged. Then, it is necessary to repeatedly perform the placement and wiring work until the wiring capacity satisfies the desired operation delay time.

As described above, the reason why the wiring capacitance satisfying the desired operation delay time cannot be obtained is that the wiring capacitance is too small or too large. In the process of the deep submicron or smaller, which is currently remarkably miniaturized, the parasitic wiring capacitance between wirings is significantly increased. For this reason, most cases where a wiring capacitance satisfying a desired operation delay time cannot be obtained are caused by an excessively large wiring capacitance.

[0006] The repetition of such arrangement and wiring work is as follows.
This is not preferable for a semiconductor integrated circuit, which is required to be shortened in development time, particularly in an ASIC including a cell-based IC, because the development time is increased.

In a general semiconductor integrated circuit,
If a signal wiring skew of each transistor, particularly a signal wiring skew of a clock driver or the like occurs, it becomes a serious defect in the operation delay time. However, in the conventional method of arranging and wiring transistors in a semiconductor integrated circuit, it is very difficult to eliminate the signal wiring skew during the work of arranging and wiring.

[0008]

As described above, in the conventional method of arranging and wiring transistors in a semiconductor integrated circuit, the operation timing of transistors arranged and wired by the method does not satisfy a desired operation delay time. In this case, it is necessary to return to the operation of arranging or wiring the transistors and repeat the operation until a state satisfying the desired operation delay time is obtained. Therefore, there is a disadvantage that the time required for the arrangement and wiring work increases, and the development period or design period of the semiconductor integrated circuit becomes longer.

In addition, when a wiring capacity that satisfies the operation delay time cannot be obtained by the conventional arrangement and wiring method, the skew of the signal delay of each transistor in the semiconductor integrated circuit, particularly the skew of the signal delay of the clock driver, etc. If it occurs, there is a drawback that it becomes a serious defect in the operation delay time.

Further, in the conventional arrangement and wiring method,
When performing the re-arrangement and the wiring work again, in order to reduce the wiring capacity only for wiring having a wiring capacity that does not satisfy the desired operation delay time, even if an attempt is made to work by separating other nearby signal wirings, it is difficult in recent years. Due to the increase in the degree of integration of the semiconductor integrated circuit, depending on the state of the arrangement relationship of the transistors other than the signal wiring, the signal wiring, the power supply line, the ground line, and the like,
There is a disadvantage that a place where the target wiring can be routed cannot be secured.

An object of the present invention is to solve the above-mentioned conventional drawbacks, perform wiring while calculating and confirming the total wiring capacity, and perform wiring so as not to exceed an arbitrarily determined total wiring capacity. It is an object of the present invention to provide a semiconductor integrated circuit design device, a wiring control method thereof, and a storage medium storing a wiring control program.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor integrated circuit designing apparatus for arranging and wiring transistors in a process of designing a semiconductor integrated circuit. for,
Three-dimensional area setting means for setting, for each wiring, a three-dimensional area for performing the wiring such that the wiring is located at least at the center of the three-dimensional area in a predetermined two-dimensional direction; The priority determining means for arbitrarily determining the priority of the wiring work, the total wiring capacity determining means for arbitrarily determining the total wiring capacity for each of the wirings, and the third order according to the priority determined by the priority determining means. A wiring executing means for performing a wiring operation for each three-dimensional area set by the three-dimensional area setting means; and a wiring evaluation for evaluating the wiring result each time the wiring executing means completes a wiring operation for one of the three-dimensional areas. Means for determining whether or not wiring having a higher priority than wiring related to the wiring work has already been made in the three-dimensional area where the wiring work has been performed. When there is a wiring with a higher priority, the total wiring capacity of all the wirings existing in the three-dimensional area where the wiring work has been performed is calculated, and the wiring work is further continued based on the calculation result. In this way, it is checked whether or not there is a wiring that exceeds the total wiring capacity determined by the total wiring capacity determination means. If there is such a wiring, an unwired portion in all three-dimensional regions including the wiring is determined. Are prohibited from wiring.

According to a second aspect of the present invention, in the semiconductor integrated circuit designing apparatus, the priority order determining means and the total wiring capacity determining means are provided for all wirings in the semiconductor integrated circuit to be designed, or in particular for total wirings. The priority order and the total wiring capacity are determined for a specific wiring whose capacity is limited.

Another object of the present invention to achieve the above object is to provide a wiring control method by a semiconductor integrated circuit designing apparatus for arranging and wiring transistors in a process of designing a semiconductor integrated circuit. On the other hand, for each wiring, setting a three-dimensional area for performing the wiring so that the wiring is located at least at the center of the three-dimensional area in a predetermined two-dimensional direction; The step of arbitrarily determining the priority of the work, the step of arbitrarily determining the total wiring capacitance for each wiring, and the step of setting by the three-dimensional area setting step according to the priority determined by the step of determining priority. Performing a wiring operation for each of the three-dimensional regions, and completing the wiring operation for one of the three-dimensional regions. And a step of evaluating the wiring result, wherein the wiring evaluation step is such that wiring having a higher priority than wiring related to the wiring work has already been made in the three-dimensional area where the wiring work has been performed. Judging whether or not there is a high-priority wiring, calculating a total wiring capacity of all the wirings present in the three-dimensional area where the wiring work has been performed, and Checking whether there is any wiring that exceeds the total wiring capacity determined by the total wiring capacitance determining means by continuing the wiring work. Prohibiting wiring of unwired portions in all three-dimensional regions.

In the wiring control method according to a fourth aspect of the present invention, in the priority order determining step and the total wiring capacitance determining step, the total wiring capacitance of all the wirings in the semiconductor integrated circuit to be designed, or particularly, the total wiring capacitance is determined. The priority order and the total wiring capacity are determined for a specific wiring to be restricted.

Still another object of the present invention to achieve the above object is to store a wiring control program for controlling a semiconductor integrated circuit designing apparatus which performs a transistor arranging and wiring operation in a semiconductor integrated circuit designing process and performs wiring control. In the storage medium, with respect to the semiconductor integrated circuit to be designed, for each wiring, a three-dimensional area for performing the wiring is positioned at least at a center of the three-dimensional area in a predetermined two-dimensional direction. Setting, the step of arbitrarily determining the priority of the wiring work of each wiring, the step of arbitrarily determining the total wiring capacity of each wiring, and the priority determined by the priority determining step Performing a wiring operation for each of the three-dimensional regions set in the three-dimensional region setting step in accordance with the order; Evaluating the wiring result each time the wiring operation for one of the three-dimensional regions is completed, wherein the wiring evaluation step includes the step of: A step of determining whether or not a wiring with a higher priority than the wiring has already been made; and, if there is a wiring with a higher priority, all the wirings existing in the three-dimensional area where the wiring work has been performed. Calculating the total wiring capacity; and, based on the calculation result, checking whether there is any wiring that exceeds the total wiring capacity determined by the total wiring capacity determining means by continuing the wiring work, When there is such a wiring, a step of prohibiting the wiring of an unwired portion in all three-dimensional areas including the wiring is included.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to one embodiment of the present invention. FIG.
Referring to FIG. 1, a semiconductor integrated circuit design device 1 of the present embodiment
0 is the first stored layout data of the semiconductor integrated circuit to be designed whose transistor arrangement has already been completed.
A layout data storage unit 11, a three-dimensional area setting unit 12, a priority order determination unit 13, and a total wiring capacity determination unit 14 that determine conditions related to wiring for a semiconductor integrated circuit to be designed, based on the determined wiring conditions. And a layout executing unit 15 for executing wiring work
5, a layout evaluation unit 16 for evaluating a wiring result according to
A second layout data storage unit for storing layout data for which wiring has been completed. FIG. 1 shows only the characteristic configuration of the present embodiment, and the description of other general configurations is omitted.

The semiconductor integrated circuit designing apparatus 10 of the present embodiment
Is realized by, for example, a personal computer, a workstation, or another computer system. The three-dimensional area setting unit 12, the priority order determination unit 13, the total wiring capacity determination unit 14, the layout execution unit 15, and the layout evaluation unit 16 CPU controlled by program
And a RAM or other internal memory. The first and second layout data storage units 11 and 17 store RA
M and other internal memories, a magnetic disk drive and other external storage layers t9. A computer program for controlling the CPU is provided by being stored in a magnetic disk, an optical disk, a semiconductor memory, and other general storage media.
CP loaded into the internal memory of the computer system
By controlling U, the function of each component is executed.

The first layout data storage unit 11 stores
The layout data in which the arrangement of the transistors in the semiconductor integrated circuit to be designed is already completed is stored. The layout data can be created by using various methods conventionally used.

The three-dimensional area setting unit 12 sets a three-dimensional area for wiring in a semiconductor integrated circuit to be designed. The three-dimensional area is set for each wiring in the semiconductor integrated circuit so that the wiring is located at least at the center of the three-dimensional area in a predetermined two-dimensional direction.

The priority determining unit 13 determines the priority of each wiring in the wiring work. That is, the wiring work is performed in order according to the priority determined by the priority determining unit 13. The priority can be arbitrarily determined by the user.

The total wiring capacity determination unit 14 determines the total wiring capacity for each wiring. The user can arbitrarily determine the total wiring capacitance of each wiring. Also, the value of the total wiring capacitance of each wiring may be set to one value for each wiring,
A plurality of values may be set with a certain width (suitable range).

The wiring priority and the total wiring capacity are as follows:
The determination may be made for all the wirings in the semiconductor integrated circuit to be designed, or may be made particularly for a specific wiring whose total wiring capacitance is limited.

The layout execution unit 15 performs wiring work for the semiconductor integrated circuit to be designed according to the priority determined by the priority determination unit 13. The wiring work is performed for each three-dimensional area set on the semiconductor integrated circuit by the three-dimensional area setting unit 12. The layout execution unit 15 first performs a wiring operation on the wiring having the highest priority. Next, among the remaining wirings, wiring work is performed in order from the wiring having the highest priority. At this time, every time the wiring work for one three-dimensional area is completed, the process shifts to the evaluation by the layout evaluation unit 16.

The layout evaluation unit 16 evaluates whether the layout execution unit 15 performs wiring work on the three-dimensional area. Specifically, first, it is determined whether or not a wiring having a higher priority than the wiring has already been made in the three-dimensional area where the wiring work has been performed. When there is a wiring having a higher priority than the wiring in the three-dimensional area, all the wirings existing in the three-dimensional area, that is, the wiring and the wiring already existing in the three-dimensional area are used. The total wiring capacity is calculated for each of the wirings having the highest priority. Then, based on the calculation result of the total wiring capacity of each wiring, it is checked whether or not there is a wiring that exceeds the total wiring capacity determined by the total wiring capacity determination unit 14 by continuing the wiring work. When there is such a wiring, the non-wiring portion in all the three-dimensional areas including the wiring is prohibited from wiring, and the process returns to the layout execution unit 15.

Therefore, when the layout execution unit 15 completes the wiring work for all the wirings in the semiconductor integrated circuit through the evaluation by the layout evaluation unit 16, all the wirings are determined by the total wiring capacitance determination unit 14. The wiring is performed within a range not exceeding the total wiring capacity.

The second layout data storage unit 17 stores
The layout data for which all wiring has been completed as described above is stored.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. As an initial state, the first layout data storage unit 11 stores the layout data of the semiconductor integrated circuit in which the transistor arrangement has already been completed.

Referring to FIG. 2, first, the three-dimensional area setting unit 12 sets a three-dimensional area for wiring (step 20).
1), the priority determining unit 13 determines the priority of each wiring (Step 202), and the total wiring capacity determining unit 14 determines the total wiring capacity for each wiring (Step 203). The operations of steps 201 to 203 described above can be performed independently of each other, and are not necessarily limited to the above order.

Next, the layout executing section 15 reads the layout data from the first layout data storage section 11 and determines the three-dimensional area setting section 12 for the wiring having the highest priority determined by the priority determining section 13. Perform wiring work for each three-dimensional area determined in (20)
4). However, at this time, since only the wiring having the highest priority has been performed, no other wiring has already been performed in the predetermined three-dimensional area. Therefore, all the wiring operations for the wiring are completed without the evaluation by the layout evaluation unit 16.

Next, the layout execution unit 15 performs a wiring operation for one three-dimensional area with respect to the wiring having the highest priority among all the wirings for which the wiring operation has not been completed (step 205). Then, the layout evaluation unit 1
The process proceeds to the evaluation of the wiring result according to 6.

First, the layout evaluation unit 16 determines whether or not a wiring having a higher priority than the wiring has already been made in the three-dimensional area where the wiring work has been performed (step 206). If it is determined that there is no wiring having a higher priority than the wiring, the flow returns to step 205, and the layout executing unit 15 performs wiring work on the next three-dimensional area.

On the other hand, if it is determined that there is a wiring having a higher priority than the wiring in the three-dimensional area, then all wirings existing in the three-dimensional area, that is, the wiring and the three-dimensional wiring are determined. The total wiring capacity is calculated for all the wirings having higher priority than the wiring already existing in the area (step 207). Then, based on the calculation result of the total wiring capacity of each wiring, it is checked whether or not there is any wiring that exceeds the total wiring capacity determined by the total wiring capacity determination unit 14 by continuing the wiring work (step 208). ). If there is no such wiring, the process returns to the layout execution unit 15 without performing any processing.

On the other hand, if there is a wiring that exceeds the total wiring capacity determined by continuing the wiring work, the non-wiring portion in all the three-dimensional areas including the wiring is prohibited from wiring. , Layout execution unit 15
(Step 209).

Next, the layout execution unit 15 checks whether or not the wiring work for all the wirings has been completed. If there is any wiring for which the wiring work has not been completed, the flow returns to step 205 to return to step 205 The wiring work is performed for each of the three-dimensional regions in the order of higher priority for the wiring (step 210).

When the wiring work for all the wirings is completed, the layout data for which the wiring has been completed is stored in the second layout data storage unit 17 and the processing is terminated (step 211).

Next, with reference to FIGS. 3, 4, and 5, a method of generating the wiring prohibition information according to the present embodiment (see step 211 in FIG. 2) will be specifically described.

The three-dimensional area 101 shown in FIGS.
It is a three-dimensional area set by the three-dimensional area setting unit 12. As illustrated, the three-dimensional area 101 includes grid lines (hereinafter referred to as wiring grids) drawn in a grid with a minimum wiring interval in the front-rear and left-right directions illustrated in FIG. Also, the wiring that can exist in the three-dimensional area 101 is assumed to be positioned on the wiring grid. In the example shown in FIG. 3, the three-dimensional area 101 includes two layers of wiring grids.

FIG. 4 shows, in the wiring grids included in the three-dimensional area 101, the wiring grids in the front-rear direction of FIG. W
FIG. 3 is a diagram showing a state where 1 is wired. Here, the wiring W1
Is the wiring with the highest priority among the wirings in the semiconductor integrated circuit to be designed.

FIG. 5 is a diagram showing a state in which the second and subsequent wirings W2 are wired in the seventh wiring grid in FIG. In FIG. 5, the total wiring capacitance of the wiring W1 is equal to the wiring W
Since the wiring W2 having a lower priority than the wiring W1 is laid in the three-dimensional area 101 where 1 exists, the number of wirings increases compared to the wiring W1 which is the same wiring in FIG.

Here, when the wiring W2 or another wiring is wired in a non-wiring area in the three-dimensional area 101, the wiring W1 determined by the total wiring capacitance determining unit 14
Is exceeded. In this case, number 1,
The second, fourth, fifth, sixth, eighth, ninth, and tenth wiring grids and all the wiring grids in the left-right direction in the drawing are all prohibited. This makes it possible to prohibit the wiring of the non-wired area of the three-dimensional area 101.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0044]

As described above, according to the semiconductor integrated circuit designing apparatus, the wiring control method, and the storage medium storing the wiring control program of the present invention, the total wiring capacity and the wiring work of the desired wiring are determined in advance. The priorities are arbitrarily determined, an arbitrary three-dimensional area is set on the semiconductor integrated circuit to be designed, wiring work is performed for each of the three-dimensional areas in descending order of priority, and Each time wiring is completed, the total wiring capacity of each wiring is evaluated based on the wiring result, and if necessary, unwiring of a predetermined three-dimensional area is prohibited. Since it is possible to obtain a wiring capacitance satisfying a desired operation delay time, the time required for the placement and wiring work is reduced,
This has the effect of shortening the development or design period of the semiconductor integrated circuit.

Further, according to the present invention, since a wiring capacitance satisfying a desired operation delay time can be obtained, there is an effect that occurrence of skew in signal delay of a transistor can be prevented.

Further, according to the present invention, the wiring operation is performed in descending order of priority while the wiring which may exceed the predetermined total wiring capacity is prohibited, so that the desired operation delay time It is not necessary to separate the wiring of the wiring capacitance that does not satisfy the above and perform the wiring work again. Therefore, a situation in which a place where the target wiring can be routed cannot be secured does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the embodiment.

FIG. 3 is a conceptual diagram illustrating a method of generating wiring prohibition information according to the embodiment, and is a diagram illustrating a three-dimensional area including a wiring grid.

FIG. 4 is a diagram showing a state in which wiring with the highest priority is performed in the three-dimensional area of FIG. 3;

FIG. 5 is a diagram showing a state in which another wiring is performed in the three-dimensional area of FIG. 4;

[Explanation of symbols]

 Reference Signs List 10 semiconductor integrated circuit design device 11 first layout data storage unit 12 three-dimensional area setting unit 13 priority determination unit 14 total wiring capacity determination unit 15 layout execution unit 16 layout evaluation unit 17 second layout data storage unit

Claims (6)

[Claims] 1. A semiconductor integrated circuit designing apparatus for arranging and wiring transistors in a process of designing a semiconductor integrated circuit, wherein the wiring is performed for each wiring with respect to the semiconductor integrated circuit to be designed. The three-dimensional area is
Three-dimensional area setting means for setting the two-dimensional area so as to be located at the center of at least a predetermined two-dimensional direction; priority determining means for arbitrarily determining the priority of wiring work of each wiring; Total wiring capacitance determining means for arbitrarily determining wiring capacitance; wiring executing means for performing wiring work for each three-dimensional area set by the three-dimensional area setting means according to the priority determined by the priority determining means; A wiring evaluation unit that evaluates a wiring result each time the wiring execution unit completes a wiring operation for one of the three-dimensional regions, wherein the wiring evaluation unit performs the wiring operation on the three-dimensional region. It is determined whether or not a wiring having a higher priority than the wiring related to the wiring work has already been made in the area, and if there is a wiring with a higher priority, the wiring work is performed. Calculating the total wiring capacity of all the wirings present in the obtained three-dimensional area, and further continuing the wiring work based on the calculation result, thereby reducing the total wiring capacity determined by the total wiring capacity determining means. A semiconductor integrated circuit design device which checks whether there is a wiring that exceeds, and if there is such a wiring, the non-wiring part in all three-dimensional regions including the wiring is prohibited from wiring. 2. The semiconductor device according to claim 1, wherein the priority order determining means and the total wiring capacitance determining means are provided for all wirings in the semiconductor integrated circuit to be designed, or for particular wirings whose total wiring capacitance is limited. 2. The semiconductor integrated circuit designing apparatus according to claim 1, wherein the priority order and the total wiring capacity are determined. 3. A wiring control method by a semiconductor integrated circuit designing apparatus for arranging and wiring transistors in a process of designing a semiconductor integrated circuit, wherein the wiring is provided for each wiring with respect to the semiconductor integrated circuit to be designed. The three-dimensional area for performing
Setting at least the center of the two-dimensional direction in the two-dimensional area; arbitrarily determining the priority of the wiring work of each of the wirings; and arbitrarily determining the total wiring capacitance for each of the wirings Performing a wiring operation for each of the three-dimensional regions set in the three-dimensional region setting step in accordance with the priority determined in the priority determining step; Evaluating the wiring result each time a wiring operation is completed for the three-dimensional area, wherein the wiring evaluation step further places priority on the three-dimensional area where the wiring operation has been performed, over the wiring related to the wiring operation. Determining whether a high-level wiring has already been made; and, if there is the high-priority wiring, performing the wiring operation. Calculating the total wiring capacity of all the wirings present in the three-dimensional area; and further continuing the wiring work based on the calculation result to exceed the total wiring capacity determined by the total wiring capacity determining means. A step of checking whether or not there is a wiring to be connected, and, if there is such a wiring, a step of prohibiting wiring of an unwired portion in all three-dimensional regions including the wiring. Method. 4. The method according to claim 1, wherein, in the priority order determining step and the total wiring capacity determining step, all the wirings in the semiconductor integrated circuit to be designed, or in particular, specific wirings whose total wiring capacitance is restricted are specified. 4. The wiring control method according to claim 3, wherein the priority and the total wiring capacity are determined. 5. A storage medium storing a wiring control program for controlling a wiring by controlling a semiconductor integrated circuit designing apparatus for arranging and wiring transistors in a process of designing a semiconductor integrated circuit, wherein: In the circuit, for each wiring, a three-dimensional area for performing the wiring is defined by the three-dimensional area.
Setting at least the center of the two-dimensional direction in the two-dimensional area; arbitrarily determining the priority of the wiring work of each of the wirings; and arbitrarily determining the total wiring capacitance for each of the wirings Performing a wiring operation for each of the three-dimensional regions set in the three-dimensional region setting step in accordance with the priority determined in the priority determining step; Evaluating the wiring result each time a wiring operation is completed for the three-dimensional area, wherein the wiring evaluation step further places priority on the three-dimensional area where the wiring operation has been performed, over the wiring related to the wiring operation. Determining whether a high-level wiring has already been made; and, if there is the high-priority wiring, performing the wiring operation. Calculating the total wiring capacity of all the wirings present in the three-dimensional area; and further continuing the wiring work based on the calculation result to exceed the total wiring capacity determined by the total wiring capacity determining means. A step of checking whether or not there is a wiring to be connected, and, if there is such a wiring, a step of prohibiting wiring of an unwired portion in all three-dimensional regions including the wiring. A storage medium that stores programs. 6. The method according to claim 1, wherein in said priority order determining step and said total wiring capacitance determining step, said wiring is performed for all wirings in a semiconductor integrated circuit to be designed or particularly for a specific wiring whose total wiring capacitance is limited. The storage medium according to claim 5, wherein the priority order and the total wiring capacity are determined.