JP2985833B2 - Clock distribution system and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay analysis and layout technique for an LSI, and more particularly to a technique for reducing power supply noise and electromigration in an arrangement and wiring method for a clock signal distribution portion of an LSI.

[0002]

2. Description of the Related Art Conventionally, in a CMOS LSI, a change in a circuit is concentrated temporally and locally, thereby causing a power supply noise in which a power supply or a ground potential changes, and an electromigration problem accompanying an increase in current density. This problem has been solved by increasing the number of power supply sources and ground wiring, or by increasing the width of these power supply and ground wirings.

Recently, a clock tree synthesizing method, which is a technique for reducing clock skew, has been widely adopted. However, these techniques are techniques for reducing the difference between the clock changes of the flip-flops in the circuit, so that the changes are basically concentrated, and the power supply noise problem and the electromigration problem are further exacerbated.

As a method of applying these clock tree synthesizing methods for delay optimization, for example, Japanese Patent Laid-Open No. 5-19 / 1993
Japanese Patent Application Laid-Open No. 7780 proposes a clock wiring method which makes it possible to shorten the clock cycle from the delay time of the worst case path and to increase the operation speed of the circuit. For example, Japanese Patent Application Laid-Open No. 4-2
No. 74567 proposes a delay calculation method for studying an accurate delay margin in consideration of clock skew based on a maximum propagation delay time or a minimum propagation delay time in a one-phase synchronous logic circuit. However, these are not techniques for reducing power supply noise or electromigration.

[0005] Recently, a technique has been introduced in which a clock of an operation unnecessary part is temporarily stopped by a gated clock method.

[0006]

Conventional methods for reducing power supply noise and electromigration have been to increase the number of power supply and ground wirings or to increase the width of these power supply and ground wirings. In the method, it is necessary to secure an area to be expanded for these wirings or to increase the number of terminals serving as external supply sources, and there is a problem that the chip area of the LSI and the number of terminals increase.

In order to increase the wiring width depending on the location,
There is a problem that the load of the wiring process in the layout becomes heavy.

In the method described in Japanese Patent Laid-Open No. 5-197780, in which delay optimization is performed by adjusting clock skew, power supply noise and electromigration may be reduced as a result. In particular, a technique for positively reducing these is not disclosed.

Further, the gated clock method is effective as a technique for reducing the overall power consumption.
However, the problems of power supply noise and electromigration are local current problems.To deal with these problems with gated clocks, it is necessary to control the clock in a very small unit, and a gate for stopping the clock is required. There is a problem that the area and the overall skew increase, and further, there is a problem that the control is complicated, and there is a problem that it is not practical.

Therefore, the present invention has been made in view of the above problems, and has as its object to make the clocks of a large number of flip-flops in a circuit change intensively during a small skew time. It is an object of the present invention to provide a clock distribution system and a method for reducing power supply noise and electromigration caused by the clock distribution method.

[0011]

In order to achieve the above object, a clock distribution system according to the present invention is a clock distribution system for an LSI, in which delay analysis of an input path and an output path of a flip-flop is performed , and the clock is distributed to a path of the flip-flop. Most
Delay analysis means for obtaining a short arrival time and a maximum arrival time; and a minimum delay constraint obtained by adding a clock skew in clock distribution to an input path to a flip-flop, and all directly reachable output paths from the flip-flop. On the path to the flip-flop and external output terminal
A delay constraint analyzing means for obtaining a maximum delay constraint against the
A margin analysis means for calculating a margin, which is a difference between the arrival time and the arrival time, from the obtained restriction time and the arrival time, and an element or wiring having a delay smaller than a minimum value of the absolute value of the margin. Means for determining a flip-flop to be inserted into a clock path; means for inserting an element or a wiring having a delay smaller than the minimum value of the absolute value of the margin into the clock path of the determined flip-flop; It is characterized by having. The present invention
Clock distribution method is the same as LSI clock distribution method.
And the delay solution of the input path and output path of the flip-flop
And the minimum arrival time of the path to the flip-flop
Delay analysis means for determining the maximum arrival time
Clock path in the clock distribution to the input path to the
Find the maximum delay constraint with reduced skew, and
All the directly reachable flips on the output path from the
Minimum for the path to flip-flops and external output terminals
A delay constraint analysis means for finding a delay constraint,
From the constraint time and the arrival time, the
A margin analysis means for determining a margin, which is a difference in arrival time,
A element having a delay smaller than the minimum value of the absolute value of the margin
Determine flip-flops to remove children or wires
Means and a clock cycle of the determined flip-flop.
From the road, a delay smaller than the minimum value of the absolute value of the margin
Means for deleting elements or wirings having
It is characterized by.

[0012] The clock distribution method of the present invention comprises :
The maximum arrival time and minimum time of each flip-flop
Determining the arrival time; and (b) the flip flow
The maximum and minimum required times
And (c) the difference between the maximum required time and the maximum arrival time.
From the maximum margin and the minimum arrival time
Step for finding the minimum margin after subtracting the required time
And (d) a clock input terminal of the flip-flop.
Even if a delay element is inserted, the maximum margin and the minimum margin
Determining which flip-flop is secured
And (e) the clock of the determined flip-flop.
Insert the delay element into the input terminal, and
Dispersing the operation timings of the
It is characterized by including. The clock distribution method of the present invention
The method is as follows: (a) The maximum of each flip-flop constituting the circuit
Determining the arrival time and the minimum arrival time; (b)
Maximum required time and minimum required time of the flip-flop
(C) determining the maximum required time from the maximum required time
The maximum margin that is obtained by subtracting the maximum arrival time and the minimum arrival
And the minimum margin obtained by subtracting the minimum required time from the time
(D) closing the flip-flop.
Even if the delay element connected to the
Flip flow ensuring a large margin and the minimum margin
(E) determining the determined flip-flop.
The delay connected to the clock input terminal of the flip-flop
The element is deleted, and the operation timing of each of the flip-flops is
Distributing the tags to each other.
I do .

[Outline of the Invention] The outline of the present invention will be described below. According to the present invention, delay analysis is performed based on clock skew when normal clock wiring is performed, and in a flip-flop, the maximum constraint and the minimum constraint on the input and output sides imposed on the flip-flop are simultaneously determined. It has a function of finding a range that satisfies and adding a delay to a clock of a flip-flop having a margin or removing a delay of the clock within a range that satisfies the limit, thereby shifting a change time from another clock.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a processing flow according to the embodiment of the present invention. Referring to FIG.
In the embodiment of the present invention, first, delay analysis processing 1
02 is performed. Here, the delay between the external terminal and the flip-flop is analyzed, and for each flip-flop and the external output terminal, the minimum arrival time and the maximum arrival time of the path to the flip-flop are obtained. Regarding the clock skew, taking into account its variation range, (a) consider the delay value of the clock distribution path itself in the worst delay, or (b) analyze the variation value in the delay analysis between flip-flops. Is considered as either a margin or a margin.

Next, a delay constraint analysis process 103 is performed. Here, based on the maximum delay constraint and the minimum delay constraint on the arrival time set in advance to the external terminal and the flip-flop, based on the input-side flip-flop, for each block serving as each delay calculation unit, The maximum delay constraint and the minimum delay constraint at points up to the block are obtained.

If the block is on a plurality of signal propagation paths, the worst value is taken. This is repeated until the signal reaches the flip-flop or the external input, and the required time for the output terminal of the flip-flop is obtained.

Next, a margin analysis 104 is performed. Here, the difference between the arrival time and the required time is obtained. Regarding the maximum delay constraint, when the arrival time is shorter than the required time, it indicates that the delay may be increased by the value difference.

The minimum delay constraint indicates that when the arrival time is longer than the required time, the delay may be reduced by the difference.

Next, a process 105 for determining a flip-flop for increasing the clock delay is performed on another flip-flop. When the delay of the clock of a certain flip-flop is increased, first, the delay from the flip-flop to the output path increases. That is, the maximum delay constraint on the output of the flip-flop becomes strict. At the same time, delay restrictions on the path leading to the flip-flop increase. That is, the minimum delay constraint on the input of the flip-flop becomes strict.

Therefore, in the process 105, the flip-flop has a margin for the maximum delay constraint on the output more than the delay value to be increased by the clock and the input more than the delay to be increased by the clock. , And a flip-flop that actually inserts a delay into a clock is determined.

Next, a process 106 for actually inserting a delay into the clock is performed on the flip-flop for which the clock delay insertion has been determined. Each of the above processes can be realized by a program executed by a computer.

FIG. 2 is a diagram showing a processing flow according to the second embodiment of the present invention. Here, it is assumed that a normal clock tree formation has a base delay other than the variation delay due to a buffer or the like, and a clock tree formation in which the clock delay can be reduced by deleting the base delay. I have.

First, a delay analysis process 202 and a delay constraint analysis process 203 are performed in the same manner as the process of the embodiment described with reference to FIG.
Perform 4.

Next, a process 205 is performed for other flip-flops to determine a flip-flop that reduces the delay. When the delay of the clock of a certain flip-flop is reduced, first, the delay to the output path from the flip-flop is reduced. That is, the maximum delay constraint on the output of the flip-flop becomes strict.

At the same time, the delay constraint on the path leading to the flip-flop is reduced. That is, the minimum delay constraint on the input of the flip-flop becomes strict. Therefore, in this process 205, in the flip-flop,
Obtain the minimum delay constraint for the output more than the delay value reduced from the clock, and the margin for the maximum delay constraint for the input more than the delay reduced from the clock. The flip-flop that actually removes the delay is determined.

Next, a process 206 for actually removing the clock delay is performed on the flip-flop for which the clock delay reduction is determined.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention will be described in detail in order to explain the above-described embodiments of the present invention in further detail with reference to specific circuits.

FIG. 3 is a diagram for explaining an embodiment of a circuit configuration to which the present invention is applied. In FIG. 3, 30
Reference numeral 1-304 denotes an external input terminal. In particular, reference numeral 304 denotes an external clock terminal. 305-307 and 327-32
9 is a buffer. 308 and 309 are buffers forming a clock tree. In particular, there is no limit on the number of buffers that form the clock tree.
A clock tree is formed in two stages. 310-
312, 317-319, 324-326 are flip-flops, 313, 314, 320, 321 are inverters, 315, 316, 322 are AND gates, and 323 is a NAND gate.

Here, for the sake of simplicity, the wiring delay is treated as being included in the delay of each gate.
The difference in delay time between the change (rise) from “0” to “1” and the fall (fall) from “1” to “0” is ignored.

The delay of each block is as follows: a buffer has a minimum delay of 4 ns, a maximum delay of 8 ns, an inverter has a minimum delay of 3 ns, a maximum delay of 5 ns, a NAND gate has a minimum delay of 5 ns, a maximum delay of 10 ns, and an AND gate has a minimum delay of 8 ns and a maximum delay of 1 ns.
5 ns.

It is assumed that the clock tree for the normal part is suppressed to a variation in the range of -2 ns to +2 ns with respect to 4 ns at the time of layout. In terms of a delay value, the clock delay of a normal clock tree forming unit is
The range is from 2 ns to 6 ns. Further, regarding the internal delay of the flip-flop, the minimum delay is 5 ns, the maximum delay is 10 ns, the setup time is 2 ns, and the hold time is 2 ns with respect to the path from the clock input to the output.

Table 1 shows initial values when delay analysis and required time analysis are performed. The leftmost column shows the block name (see FIG. 3), and the values other than flip-flops show the values of the output part of the block name. With respect to flip-flops, their inputs and outputs are distinguished from each other. The blank part indicates a part obtained by performing the delay analysis, the required time analysis, and the margin analysis.
Further, "-" indicates a portion having no meaning to be obtained. Here, the unit is ns.

As the initial values of the analysis, first, the arrival time, that is, the change time, for the external input terminal, the required time, that is, the constraint time, and the clock cycle for the external output terminal are given. Here, as for these values, both the maximum value and the minimum value have an arrival time of 0 ns at the external clock input terminal and an arrival time of 25 ns at the other external input terminals. For the external output terminal, the maximum required time is 25 ns and the minimum required time is 0 ns. That is, for the external terminal, 0
This indicates that the circuit must be configured so that the arrival time is not less than ns and not more than 25 ns. The clock cycle is assumed to be 50 ns.

Next, for the flip-flop, the arrival time is set for the output of the flip-flop which is the starting point of the delay analysis, and the required time is set for the input of the flip-flop which is the starting point of the constraint analysis. Here, the clock skew is considered as a delay value.
That is, the time to reach the output of block 309 is 2 ns
To 6 ns (see Table 1).

The arrival time of the output of the flip-flop is obtained from the delay time of the clock and the delay from the clock to the output of the flip-flop. Here, the maximum arrival time is 16 ns and the minimum arrival time is 7 ns. Also, the required time at the input of each flip-flop is obtained from the clock delay and the setup and hold times. Here, the maximum required time is 50 ns and the minimum required time is 8 ns.

Table 2 shows the result of obtaining the arrival time, the required time, and the margin based on the initial values in Table 1.

There are various methods for the delay analysis and the method of obtaining the required time. Here, in the delay analysis, the analysis is started from the starting point, that is, from the external input terminal and the output of the flip-flop. For each output, a method of propagating only the worst of delays from all inputs of the block is taken. The largest one is selected in the maximum delay analysis, and the smallest one is selected in the minimum delay analysis.

As an example, a description will be given by cutting out the maximum delay analysis processing of the path leading to the D input of the flip-flop 318 in FIG. 3 from the entire processing.

The inverter 314 and the AND gate 315 are analyzed first. However, since the output of the inverter 314 is only the path from the flip-flop 311, the maximum arrival time of the flip-flop 311 is added to the maximum delay 5 ns of the inverter 314. , 21 ns, and there are both paths from the flip-flops 310 and 312 to the AND gate 315. However, since both have the same delay, there is no problem in selection, and the maximum arrival time of the output of the AND gate 315 is: The sum of the maximum delay time of the flip-flop 310 or 312 and the maximum delay of 315 is 31 ns.

Next, selection occurs in the analysis at the AND gate 316. In the path arriving from the inverter 314, the output from the AND gate 316 is 36 ns, and in the path from the AND gate 315, 46 ns.
In the maximum delay analysis, the larger value is taken as the worst value, and the maximum arrival time for the output of the AND gate 316 is 46 ns.

Here, since it is considered that the delay due to the wiring is included in the delay of the block, there is no delay between the AND gate 316 and the D input of the flip-flop 318, and the maximum arrival time 46n to the flip-flop 318 is assumed.
s is required. Hereinafter, the same analysis is performed to obtain the arrival time.

Next, as an example of the required time analysis processing, the required time for the maximum delay constraint on the Q output of the flip-flop 312, that is, the maximum required time will be cut out from the entire processing.

First, the required time of the AND gate 316 is
Here, since the wiring delay is not defined separately from the block delay, it is 50 ns, which is the same as the required time of the D input of the flip-flop 318.

Next, the signal reaches the inverter 314 and the AND gate 315 which are the inputs of the AND gate 316. Since the inverter 314 has one output,
By subtracting the maximum delay 15 ns of the AND gate 316 from the maximum required time of the output of the AND gate 316, 35 ns
Is the required time for the output of the inverter 314.

On the other hand, the output of the AND gate 315 is supplied to the AND gate 316 and the flip-flop 319.
Since the two points are connected, the worst value of both is taken.

At this time, since the required time from the AND gate 316 is 35 ns and the required time from the flip-flop 319 is 50 ns, the stricter 35 ns is taken as the maximum delay constraint.

Next, by subtracting the maximum delay amount of the AND gate 315, the required time 2 of the Q output of the flip-flop 312 is obtained.
0 ns is required. The required time is similarly required for the others.

Next, a margin is obtained. Here, the margin for the maximum required time is defined as a value obtained by subtracting the maximum arrival time from the maximum required time, and the margin for the minimum required time is defined as the minimum arrival time. Minus the minimum required time.

That is, here, the maximum margin of each block satisfies the constraint even if the maximum arrival time of the block is increased by the margin, and the minimum margin of each block is the minimum margin of the block. This indicates that the constraint is satisfied even if the time is reduced by the margin. The margin is immediately obtained from the difference between the arrival time and the required time for each block.

Next, in order to disperse the clock change time by inserting a delay into the clock, a flip-flop that inserts a delay into the clock is determined. Here, it is assumed that only 5 ns delay blocks are prepared to be inserted into the clock. In this case, when this delay is inserted in the clock of the flip-flop, the output delay time of the flip-flop increases by 5 ns, and the input request time increases by 5 ns. For this reason, it is necessary to consider that the maximum margin of output decreases by 5 ns and the minimum margin of input decreases by 5 ns. Regarding the other margins, if all the constraints are satisfied before the delay is inserted into the clock, the margins tend to increase, so there is no need to consider them.

That is, the flip-flop capable of increasing the clock delay must have at least a maximum margin of 5 ns or more for the output and a minimum margin of 5 ns or more for the input. In this case, in FIG. 3, 312, 324, 325, and 326 lack the maximum allowance for output, and 317 lacks the minimum allowance for input. Therefore, among all the flip-flops, the flip-flops satisfying this condition are 310, 311 and 31
8, 319.

Therefore, assuming that the maximum is these four, this four
One of them is to select a flip-flop that inserts a delay into the clock. Examples of selection methods include inserting delays into all possible clocks, randomly selecting some, and so on. Finally, a delay is inserted in the determined flip-flop clock, and the process ends.

Conversely, when the delay is removed from the clock and the change time of the clock is dispersed,
The processing is performed as follows. Here, it is assumed that a part of the distribution system used for normal clock distribution can be deleted, and the delay that can be deleted is only 3 ns.

In this case, if this delay is removed from the clock of the flip-flop, the output delay time of the flip-flop is reduced by 3 ns and the required time of the input is reduced by 3 ns. For this reason, as the margin, the minimum margin of the output is reduced by 3 ns, and the maximum margin of the input is 3 ns.
It is necessary to consider the decrease. As for the other margins, if all the constraints are satisfied before the clock delay is removed, the margins tend to increase, and thus need not be considered. In other words, flip-flops that can eliminate clock delays are at least
The minimum margin for the output must be 3 ns or more, and the maximum margin for the input must be 3 ns or more. In this case, 3
10 and 317 have insufficient output margins.

Therefore, out of all the flip-flops, the flip-flops satisfying this condition are 311, 312, 3
18, 319, 324, 325, and 326.
Therefore, the maximum is set to seven, and a flip-flop that removes the delay from the clock is selected from the seven.

Examples of the selection method include a method of inserting a delay into all possible clocks and a method of selecting some at random. Finally, the delay is removed from the determined flip-flop clock, and the process ends.

FIG. 4 shows an embodiment in which delays are inserted into all flip-flops into which a clock delay of 5 ns can be inserted, based on the results of delay analysis shown in Table 2 for the circuit shown in FIG. FIG.

In FIG. 4, reference numerals 401 to 432 denote
They respectively correspond to 301 to 332 in order. Flip-flops into which delays can be inserted are 310, 311, 31
8 and 319, respectively, and in FIG.
411, 418, and 419. Here, 43
Reference numerals 3, 434, 435, and 436 denote buffers inserted to increase the delay. In this example, buffers are inserted for each flip-flop.

FIG. 5 also shows an embodiment in which delays are inserted into all flip-flops into which a clock delay of 5 ns can be inserted, based on the results of delay analysis as shown in Table 2 for the circuit shown in FIG. FIG. here,
501 to 532 are 501 to 53, respectively.
2 is supported. Blocks into which delays can be inserted are 31
0, 311, 318, and 319, respectively, correspond to 510, 511, 518, and 519 in FIG. Here, 533 is a buffer inserted to increase the delay, 534 and 535 are buffers forming a clock tree, and form a clock tree with the same delay and variation as 508 and 509.

FIG. 6 shows a flip-flop capable of eliminating a clock delay of 3 ns from the result of delay analysis as shown in Table 2 for the circuit shown in FIG. FIG. 10 is a diagram for explaining an embodiment in which an appropriate flip-flop is selected every other one of the numbers assigned to the blocks from among the flip-flops.

The flip-flops from which the delay of 3 ns can be eliminated are 311, 312, 318, 319, 324, and 32.
5 and 326, of which 312 and 31
9 and 325 are selected and applied.

In FIG. 6, the applied flip-flop is 6
12, 619, and 625. In this example, 633
Can form a clock tree in the same manner as the clock tree formed from 608 and 609, but it is assumed that the base delay is reduced by 3 ns at the maximum.

FIG. 7 also shows a flip-flop capable of eliminating the clock delay of 3 ns from the result of the delay analysis shown in Table 2 for the circuit shown in FIG. In this example, every other flip-flop is selected from the flip-flops corresponding to the numbers assigned to the blocks. Here, 312, 319, 3
In this example, 25 is selected and applied. In FIG. 7, the applied flip-flops correspond to 712, 719, and 725.

In this example, the clock tree formed from 708 and 709 is formed immediately after 708, so that the base delay of the clock tree formed from 708 and 709 is reduced by 3 ns at the maximum. It is assumed that it becomes smaller.

[0065]

[Table 1]

[0066]

[Table 2]

[0067]

As described above, according to the present invention,
Due to the fact that the clocks of many flip-flops in the circuit change intensively during a small skew time,
Reducing power supply noise and electromigration, can.

The reason is that, in the present invention, delay analysis is performed based on the clock skew in the case where normal clock wiring is performed, and the maximum input and output side imposed on the flip-flop is imposed on the flip-flop. Find the range that satisfies the constraint and minimum constraint at the same time, and add a delay to the clock of the flip-flop that has a margin or remove the clock delay within the range that satisfies the limit so that the change time is shifted from other clocks. It depends.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow of an embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of another embodiment of the present invention.

FIG. 3 is a diagram illustrating an example (part 1) of a circuit configuration to which an embodiment of the present invention is applied;

FIG. 4 is a diagram illustrating an example (part 2) of a circuit configuration to which an embodiment of the present invention is applied;

FIG. 5 is a diagram illustrating an example (part 3) of a circuit configuration to which an embodiment of the present invention is applied;

FIG. 6 is a diagram illustrating an example (part 4) of a circuit configuration to which an embodiment of the present invention is applied;

FIG. 7 is a diagram showing an example of a circuit configuration to which an embodiment of the present invention is applied and explained. 101 start of processing 102 delay analysis processing 103 delay constraint analysis processing 104 margin analysis processing 105 clock delay insertion flip-flop determination processing 106 clock delay insertion processing 107 end of processing 201 start of processing 202 delay analysis processing 203 delay restriction analysis processing 204 margin Degree analysis processing 205 clock delay deletion flip-flop determination processing 206 clock delay deletion processing 207 end of processing 301-304 input terminal 305-307, 327-329 buffer 308, 309 clock tree formation buffer 310-312, 317-319, 324- 326 Flip-flop 313, 314, 320, 321 Inverter 315, 316, 322 AND gate 323 NAND gate 330-332 Output terminal 401-404 Input terminal 405 −407, 427-429 Buffer 408, 409 Clock tree formation buffer 410-412, 417-419, 424-426 Flip-flop 413, 414, 420, 424 Inverter 415, 416, 422 AND gate 423 NAND gate 430-432 Output terminal 433-436 Delay adjustment buffer 501-504 Input terminal 505-507, 527-529 Buffer 508, 509 Clock tree formation buffer 510-512, 517-519, 524-526 Flip-flop 513, 514, 520, 521 Inverter 515, 516, 522 AND gate 523 NAND gate 530-532 Output terminal 533 Delay adjustment buffer 534, 535 Clock tree formation buffer 601-604 Input terminals 605-607, 627-629 Buffers 608, 609 Clock tree formation buffers 610-612, 617-619, 624-626 Flip-flops 613, 614, 620, 621 Inverters 615, 616, 622 AND gate 623 NAND gate 630- 632 Output terminal 633 Clock tree formation buffer 701-704 Input terminal 705-707, 727-729 Buffer 708, 709 Clock tree formation buffer 710-712, 717-719, 724-727 Flip-flop 713, 714, 720, 721 Inverter 715 , 716, 722 AND gate 723 NAND gate 730-732 Output terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 21/82 W (58) Investigated field (Int.Cl. ⁶ , DB name) G06F 17/50 G06F 1/10 H01L 21 / 82

Claims (6)

(57) [Claims] (A) Each flip-flop constituting a circuit
Determining the maximum and minimum arrival times of the flip-flop ; and (b) the maximum and minimum required times of the flip-flop.
Determining a request time; and (c) subtracting the maximum arrival time from the maximum request time.
From the maximum margin and the minimum arrival time
And determining the minimum margin minus the time delay to the clock input terminal of; (d) flip-flop
Even if an element is inserted, the maximum margin and the minimum margin are
Determining the flip-flop to be secured ; and (e) clock input of the determined flip-flop.
Insert the delay element into the terminal, and
Clock distribution how which comprises the steps of: dispersing one another the operation timing of the. 2. (a) Each flip-flop constituting a circuit
Determining the maximum and minimum arrival times of the flip-flop ; and (b) the maximum and minimum required times of the flip-flop.
Determining a request time; and (c) subtracting the maximum arrival time from the maximum request time.
From the maximum margin and the minimum arrival time
And determining the minimum margin by subtracting the time, (d) connected to the clock input terminal of the flip-flop
The maximum margin and the minimum
Steps to determine flip-flops with sufficient margin
And (e) the clock input of the determined flip-flop.
Delete the delay element connected to the terminal, and
Steps to disperse the flop operation timings
Clock distribution how which comprises a flop, a. 3. In an LSI clock distribution system, delay analysis of an input path and an output path of a flip-flop is performed.
Minimum time to reach the path of the flip-flop and maximum
A delay analysis means for determining the arrival time, the input path to the flip-flop obtains the minimum delay constraints plus clock skew in clock distribution,
Regarding the output path from the flip-flop, all the directly reachable flip-flops and the path to the external output terminal
Maximum delay constraint analysis means for determining the delay constraint, from the determined constraint time and arrival time, and the margin analyzing means for determining the margin is a difference between the arrival time for the constraint time, the absolute of the margin for Means for determining a flip-flop to be inserted into the clock path by means of an element or wiring having a delay smaller than the minimum value of the value; Means for inserting an element or a wiring having a small delay; and a clock distribution method. 4. In an LSI clock distribution method, delay analysis of an input path and an output path of a flip-flop is performed.
The minimum arrival time and the maximum of the path to the flip-flop
A delay analysis means for determining the arrival time, the input path to the flip-flop obtains the maximum delay constraint minus the clock skew in the clock distribution,
Regarding the output path from the flip-flop, all the directly reachable flip-flops and the path to the external output terminal
Delay constraint analysis means for finding a minimum delay constraint on , a margin analysis means for obtaining a margin, which is a difference between the arrival time with respect to the constraint time , from the determined constraint time and arrival time, and an absolute value of the margin. Means for determining an element having a delay smaller than the minimum value or a flip-flop for eliminating a wiring; and an element having a delay smaller than the minimum value of the absolute value of the margin from the clock path of the determined flip-flop. Alternatively, there is provided a clock distribution system, comprising: means for removing wiring. 5. An LSI clock distribution system comprising: (a) a delay solution of an input path and an output path of a flip-flop;
And the minimum arrival time of the path to the flip-flop
And the delay analysis processing for determining the maximum arrival time, the input path to the (b) flip-flop, the minimum delay constraints plus clock skew in clock distribution
Determined relates to an output path from the flip-flop, arrives directly all the flip-flop reachable and an external output terminal
A delay constraint analysis processing for determining the maximum delay constraints for path that, the process of obtaining the margin is a difference between the arrival time for the (c) from the determined constraint time and arrival time, the <br/> constraint time (D) a process in which an element or a wiring having a delay smaller than the minimum value of the absolute value of the margin determines a flip-flop to be inserted into a clock path; and (e) a clock path of the determined flip-flop. A process for inserting an element or a wiring having a delay smaller than the minimum value of the absolute value of the margin and a program for executing each of the processes (a) to (e) in an information processing device such as a computer are recorded. recoding media. 6. A clock distribution system for an LSI, comprising: (a) a delay solution of an input path and an output path of a flip-flop;
And the minimum arrival time of the path to the flip-flop
And (b) a maximum delay constraint that reduces clock skew in clock distribution with respect to an input path to a flip-flop.
Determined relates to an output path from the flip-flop, arrives directly all the flip-flop reachable and an external output terminal
A delay constraint analysis processing for obtaining the minimum delay constraints for path that, the process of obtaining the margin is a difference between the arrival time for the (c) from the determined constraint time and arrival time, the <br/> constraint time (D) a process of determining the flip-flop for removing an element or a wiring having a delay smaller than the minimum value of the absolute value of the margin; and (e) a clock path of the determined flip-flop.
Recording a program to be executed by the minimum absolute value each processing computer such as an information processing apparatus of the process of deleting the element or wire, of the (a) ~ (e) with a smaller delay than in the margin from recoding media.