JP3530459B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit layout method, and more particularly to a semiconductor integrated circuit layout method capable of automatically designing a semiconductor chip that satisfies timing constraints and is highly integrated.

[0002]

2. Description of the Related Art Recently, the circuit scale of semiconductor integrated circuits has rapidly increased with the systemization, and it is common to design semiconductor integrated circuits hierarchically. That is, basic cells having a small circuit scale and basic circuit functions such as an inverter, a buffer, a NAND gate, a flip-flop circuit, and an adder, and an analog circuit such as a CPU, a RAM, a ROM and an A / D converter, a PLL circuit, and the like. Mega macros having a large circuit scale are laid out on the same semiconductor chip.

A layout method of a semiconductor integrated circuit for laying out a basic cell and a mega macro on the same semiconductor chip is described in Japanese Patent Application Laid-Open No. 10-4141. The layout method of the semiconductor integrated circuit described in the above publication will be described with reference to FIG.
4-2 is a bonding pad, and 4-3 to 4-6 are a CPU, a ROM, a RAM, and an analog circuit, respectively.
Reference numeral -7 is a base portion constituting the gate array portion or an arrangement area of basic cells in the case of designing by a cell base method.

Reference numeral 4-8 is a basic cell placement prohibition area for prohibiting the placement of basic cells. Basic cells are not placed in this basic cell placement prohibition area 4-8 and are dedicated areas for wiring. It is possible to prevent unwiring, which is a problem when a basic cell is placed between mega macros in the cell placement prohibited area 4-8.

That is, when the basic cells are arranged between the mega macros 4-3 to 4-6, the freedom of the wiring path is reduced by the basic cells, and unwired or short-circuited wires or long bypass wires are generated. Basic cell placement prohibited area 4-8
It is said that this can be prevented by providing the.

As a second conventional example of a semiconductor integrated circuit layout method, after arranging and wiring mega macros and basic cells, timing verification is performed in consideration of wiring delay, and among basic cells in which a timing error has occurred, A method of specially arranging a basic cell in which the timing error can be eliminated by changing the arrangement in the basic cell arrangement prohibited area in the basic cell arrangement prohibited area has been proposed.

[0007]

The semiconductor integrated circuit layout method according to the first prior art described above satisfies the timing constraint condition when the basic cells are arranged between the mega macros, and has a basic wiring property such as the interconnectability between the mega macros. Even if the layout constraint conditions for the cells and mega macros are satisfied, the basic cells cannot be placed in the basic cell placement prohibited area, the integration degree of the entire semiconductor chip is deteriorated, and the timing constraint conditions are satisfied. There is a problem that the layout correction process becomes long.

In the semiconductor integrated circuit layout method according to the second prior art, after the timing verification is performed, the setting of the basic cell placement prohibited area is canceled for a specific basic cell, and the basic cell is automatically set again for the basic cell. Since layout and wiring must be performed, the layout design process becomes long, and it is difficult to design in a short design period, which is particularly demanding for ASIC and the like.

Therefore, an object of the present invention is to add information for permitting the placement in the basic cell placement prohibited area to a specific basic cell, and to automatically perform the automatic operation of the basic cell in the chip internal area including the area between mega macros. It is an object of the present invention to provide a layout method of a semiconductor integrated circuit, which includes a processing step of arranging and wiring, improves the integration degree of a semiconductor chip, and can shorten the design period.

[0010]

Therefore, the semiconductor integrated circuit layout method according to the present invention has a basic circuit function.
And a circuit scale larger than the basic cell having the
Layout method of semiconductor integrated circuit including a mega macro
And inside the semiconductor chip creates a chip internal area
And a chip internal area generating step
A mega macro placing step of placing the mega macro, and
Including the mega macro arranged in the mega macro arrangement step
To generate a basic cell placement prohibited area
The placement prohibited area generation step, and the basic cell placement prohibited area
Allowable basic cell placement that is an area that does not include the mega macro
An allowable basic cell placement area creating step of creating an area, and
Do not include the basic cell placement prohibited area in the chip internal area.
A basic cell placement area generator that generates a basic cell placement area
And the basic that can be placed in the allowable basic cell placement area
Select a placement-allowed basic cell that is a cell from the basic cells
Placement allowable basic cell selection step, and the placement allowed basic cell
The above-mentioned allowance basic cell selected in the selecting step is allowed
Priority is placed in the basic cell placement area, and
Place the basic cells other than cells in the basic cell placement area
A layout step including a process for performing, in the placement permissible basic cell selection step, among the basic cells serially connected to the mega macro, directly connected to the mega macro, that is, the first connection order. It is characterized in that the basic cells from the basic cell to the connection order of 2 or more are selected as the arrangement-permitted basic cells.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a layout method of a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a flow chart showing a layout method of a semiconductor integrated circuit of the present invention, and FIG. 2 is a schematic diagram of a semiconductor chip 20 designed by using the layout method of a semiconductor integrated circuit of the present invention.

In FIG. 1, the circuit connection information 1 includes connection information between external terminals and circuit blocks including basic cells and mega macros arranged in the chip internal area, and connection information between circuit blocks.

The layout information 2 is a layout grid, a wiring grid, the number of wiring layers and a preferential wiring direction of each wiring layer, names of basic cells and mega macros, outlines, and reference points for layout when performing automatic layout. It contains various information about layout such as terminal names and attributes and terminal positions.

First, in step S11, it is determined which design method to use, such as a wafer manufacturing process to be used, a package to be used, a gate array method, a cell base method, and an embedded array method.

Next, in step S12, a chip internal area in which circuit blocks such as mega macros and basic cells are arranged is generated. Referring to FIG. 2, a bonding pad 21 and an input / output buffer 22 are arranged around the semiconductor chip 20, and a chip internal area 23 is formed inside the input / output buffer 22.

Next, in step S13, mega macros are automatically or manually arranged in the chip internal area 23, and in step S14, an automatic layout area excluding the area occupied by the mega macros is generated in the chip internal area 23.

Subsequently, in step S15, a basic cell placement prohibited area is generated so as to include all the mega macros, and in step S16, a basic cell placement area excluding the basic cell placement prohibited area which is the chip internal area 23 is created. To do.

Referring to FIG. 2, mega macros M1 to M5
Are arranged in the chip internal area 23, and the basic cell placement prohibited area 24 is generated so as to include these mega macros M1 to M5. Further, a basic cell placement area 25 shown by a broken line is generated by removing the basic cell placement prohibited area 24 from the chip internal area 23.

Here, an area obtained by combining the shaded area and the basic cell arrangement area 25 is an automatic layout area.

In FIG. 2, the basic cell placement prohibited area 24
Is the lower side of the mega macros M3 to M5 and the mega macro M2.
Although it is generated along the right side of M5, it does not necessarily have to be generated along one side of the mega macro, and may be generated in a shape including the mega macros M1 to M5.

Further, in FIG. 2, the basic cell placement prohibited area 24
Is shown as one in the chip internal area 23, but there may be a plurality of basic cell placement prohibited areas. At this time, the basic cell placement area is generated as an area that does not include the basic cell placement prohibited area in the chip internal area 23.

Next, in step S17, a placement allowable basic cell that can be placed in the automatic layout area in the basic cell placement prohibited area 24 shown by the shaded area in FIG. 2 is selected from all the basic cells. Specifically, a placement enable flag that allows placement is added to the placement allowance basic cell. Therefore, the basic cells to which the allocable flag is not added are prohibited from being arranged in the basic cell layout prohibited area.

Further, the placement allowable basic cell is selected in accordance with a plurality of conditions as follows.

1) Select all basic cells directly connected to the mega macro. 2) Select only a basic cell having two terminals such as an inverter or a buffer directly connected to the mega macro. Other basic cells that are directly connected to the mega macro terminals are prohibited from being placed in the placement prohibited area. 3) Select a buffer for timing adjustment.

4) From the basic cells satisfying the above conditions 1) to 3), the basic cells having the longer sides smaller than the distance between the mega macros, such as 1) to 3) and the sizes of the basic cells are selected. Select in consideration.

The condition 1) above is to shorten the wiring length between the mega macro and the basic cell directly connected to it by arranging the basic cell directly connected to the mega macro in the automatic layout area in the basic cell placement prohibited area. It is possible to reduce the wiring delay.

In addition, 2), the basic cells other than the inverter or the buffer have at least three wiring lines connected to the basic cells, and when the basic cells are arranged in the automatic layout area in the basic cell layout prohibited area. This is a condition considering that the wiring density of the automatic layout area in the basic cell placement prohibited area increases.

The condition 3) is that after the circuit blocks are arranged in the automatic layout area and the wiring between the circuit blocks is executed, the timing verification in consideration of the wiring delay is performed, and the timing error is generated as a result of the verification. When it is determined that a cell exists, it means that a buffer to be additionally inserted in the wiring connected to the basic cell in which the timing error has occurred is selected in order to reduce the wiring delay.

The condition 4) is that when the distance between the mega macros is 100 μm at the maximum, a basic cell having a larger size, for example, a 110 μm × 300 μm basic cell is arranged in the automatic layout area within the basic cell layout prohibited area. However, it is a condition that considers the size of the basic cell and the distance between the mega macros.

Next, returning to FIG. 1, in step S18, the basic cells and the arrangement-permitted basic cells are roughly arranged in the automatic layout area by referring to the circuit connection information 1 and the layout information 2, and the circuit blocks and the circuits are arranged. The wiring between the block and external terminals is roughly. That is, a rough layout is performed in the automatic layout area for the basic cells and the placement-allowed basic cells. At this time, the placement permitted basic cells are preferentially placed in the automatic layout area in the basic cell placement prohibited area, and the other basic cells are placed in the basic cell placement area. Therefore, the placement permitted basic cells are preferentially placed in the automatic layout area in the basic cell placement prohibited area, but if they cannot be placed in this area, they are placed in the basic cell placement area.

Subsequently, in step S19, the number of wirings actually wired between the mega macros is compared with the allowable number of wirings that can pass between the mega macros by referring to the general layout information generated in step S18. Is not exceeded, and whether or not the layout evaluation criteria such as the degree of integration or the wiring density of the basic cell is within the setting range set in step S11 is determined. If it is determined, for example, the allowable number of wiring lines that can pass between mega macros is 10
For a book, if the number of wires actually wired between these mega macros exceeds 15 and exceeds the allowable number of wires,
The placement allowable basic cell is moved to the basic cell placement area 25 in the automatic layout area in the basic cell placement prohibited area, or to the basic cell placement area 25 outside the basic cell placement prohibited area.
Returning to step 18, the rough layout and wiring are repeatedly executed until the layout evaluation standard is satisfied.

Next, in step S20, step S
With respect to the layout generated in 18, the timing verification considering the wiring delay is executed and the timing information is output. Then, in step S21, it is determined with reference to the timing information generated in step S20 whether or not the specific timing included in the timing information generated in step S20 satisfies the timing constraint condition.

If it is determined in step S21 that the timing constraint condition is not satisfied, the process returns to step S18, and the rough placement / routing is executed again. If the rough placement / wiring correction does not satisfy the timing constraint condition, The wiring delay is reduced and the timing error is eliminated by adding a buffer in step S22 or by replacing the basic cell with a high-driving basic cell having the same basic cell logic and a large driving capability.

The timing constraint conditions include the following conditions. 1) Set the timing threshold. For example, when the maximum setup time / hold time is 10 ns, it is increased by 20%, that is, 1
12n in the critical path with 2nsec as the threshold
If there is a path that exceeds the second, it is determined in step S21 that the timing constraint condition is not satisfied.

2) The judgment rate is the ratio of violation to the number of critical paths. For example, if the number of critical paths is 100 and the number of wiring lines that have a timing error exceeds 100, it is determined in step S21 that the timing constraint condition is not satisfied.

In addition to the determinations in steps S19 and S21, an upper limit value of the total execution time of rough placement and wiring including re-execution may be set as a determination reference.

Next, when it is determined in step S21 that the timing constraint condition is satisfied, in order to reduce the power consumption of the semiconductor integrated circuit, the buffer is deleted or the logic of the basic cell is the same and the power consumption is reduced in step S23. Replace the basic cell with a small, low-consumption basic cell.

Next, in step S24, the circuit connection information 1,
With reference to the layout information 2 and the general layout information generated in step S18, the basic cells are finely arranged in the automatic layout area in the minimum layout grid unit, and between the circuit blocks and between the circuit block and the external terminal in the minimum wiring grid unit. Detailed wiring. That is, the detailed layout is performed in the automatic layout area for the basic cells and the placement-allowed basic cells,
Outputs detailed layout information.

Finally, in step S25, step S24
DRC by referring to the detailed layout information generated in
(Design Rule Check) is performed, and if the check result is satisfactory, mask data 3 for mask fabrication is output.

In the above description, step S24
After that, the mask data is created in step S25. However, after the detailed layout in step S24, the second layout evaluation standard is set similarly to step S19, and the detailed layout is performed until the second layout evaluation standard is satisfied. May be repeated.

Further, step S24 or step S
In 18, there is a case where the detailed layout or the general layout is modified and the arrangement-permitted basic cells arranged in the automatic layout area shown by the hatched portion in FIG. 2 are moved. In this case, the following criteria are used as criteria for moving.

1) With respect to the set timing threshold value, the placement allowance basic cell having the largest timing margin is moved in this order. For example, when the timing margin of the placement-allowed basic cell A is 2 ns, the timing margin of the placement-allowed basic cell B is 4 ns, and the timing margin of the placement-allowed basic cell C is 6 ns, the placement-allowed basic cell C → the placement-allowed basic cell Move from B to placement-approved basic cell A in this order.

2) The placement-permitted basic cell is moved toward the direction in which the wiring density is low in the automatic layout area in the basic cell placement prohibited area. It is considered that this increases the possibility of eliminating unwiring.

3) The placement allowance basic cells are moved according to the placement order.

Next, referring to FIG. 2, reference numeral 26 is an arrangement-permitted basic cell arranged in the automatic layout area within the basic cell arrangement prohibited area, and 27 is an arrangement-permitted basic cell arranged in the basic cell arrangement area 25. Represents a basic cell other than.

Reference numeral 26 is a buffer inserted in the wiring path connected to the mega macro M1 in step S22,
Reference numeral 27 may be an arrangement-permitted basic cell directly connected to the mega macro M1 before the buffer 26 is inserted.

Next, with reference to FIG. 3, a second embodiment of the semiconductor integrated circuit layout method of the present invention will be described. It should be noted that common reference characters / numerals are attached to components common to FIG.

In FIG. 3, reference numeral 31 is an arrangement allowance basic cell directly connected to the mega macro M1, 32 is an arrangement allowance basic cell connected to the arrangement allowance basic cell 31, and 33 is a base connected to the arrangement allowance basic cell 32. It is a cell.

As described above, in the layout method of the semiconductor integrated circuit according to the present embodiment, the placement permissible basic cells in step S17 of FIG. 1 are not selected only in the basic cells directly connected to the mega macro, but are connected in series to the mega macro. Among the standard cells thus selected, the layout method of the semiconductor integrated circuit according to the first embodiment is different in that the basic cells directly connected to the mega-macro to the basic cells up to the connection order of 2 or more are selected as the placement-permitted basic cells. ing.

In the example of FIG. 3, since the placement allowable basic cells are those having the connection order up to 2, the placement allowed basic cells 31 and 32 are placed in the automatic layout area within the basic cell placement prohibited area. In FIG. 3, the arrangement allowable basic cells are those having a connection order of up to 2, but any value may be used as long as both the determination with respect to the layout evaluation criterion in step S19 and the determination with the timing constraint condition in step S21 in FIG. 1 are satisfied. Good, generally, when the connection order limit value is increased, the number of placement-permitted basic cells arranged in the automatic layout area within the basic cell placement prohibited area is increased, so that the number of basic cells in the basic cell placement area 25 is relatively large. The number of semiconductor chips 20 is reduced, and the area of the semiconductor chip 20 is reduced. Furthermore, since the wiring length between the mega macro and the placement-allowed basic cell becomes shorter,
Wiring delay is reduced and timing errors are less likely to occur.

Reference numerals 31 and 32 are buffers inserted in the wiring path connected to the mega macro M1 in step S22, and 33 is an arrangement permitting basic cell directly connected to the mega macro M1 before the buffers 31 and 32 are inserted. May be In this case, the buffer 31 and the placement allowance basic cell 3
3 has a long wiring length, and 32 is provided as a second buffer in order to drive a wiring load connected to the placement allowance basic cell 33.

Reference numeral 31 is a buffer inserted in the wiring path connected to the mega macro M1 in step S22,
Reference numeral 32 may be a placement allowance basic cell directly connected to the mega macro M1 before the buffer 31 is inserted, and 33 may be a placement allowance basic cell connected to the placement allowance basic cell 32.

Further, 32 may be the high drive basic cell described in step S22. As described above, in the semiconductor integrated circuit layout method according to the second embodiment, it is possible to arrange a plurality of buffers and a plurality of arrangement-permitted basic cells in any combination in the automatic layout area in the basic cell arrangement prohibited area. .

[0055]

As described above, in the layout method of the semiconductor integrated circuit according to the present invention, the placement allowable basic cells that can be placed in the automatic layout area within the basic cell placement prohibited area are selected from all the basic cells at the initial design stage. By selecting and performing the same placement / wiring process on the placement-permitted basic cells and the basic cells excluding the placement-allowed basic cells, the degree of integration is improved as compared with the first and second conventional examples, and the semiconductor chip area is increased. Can be obtained.

That is, as compared with the first and second conventional examples, the number of placement-permitted basic cells placed in the automatic layout area in the basic cell placement prohibited area increases, so that the basic cells placed in the basic cell placement area are increased. The number of cells can be reduced, and the area of the basic cell arrangement region can be reduced.

Since the whole design process can be shortened as compared with the second conventional example, the design period can be shortened.

Further, in the rough layout / wiring process, the layout-allowed basic cells connected to the mega macro are arranged in the automatic layout area in the basic cell layout prohibited area which is close to the mega macro in distance. The circuit block is characterized in that a timing error is unlikely to occur.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a layout method of a semiconductor integrated circuit of the present invention.

FIG. 2 is a schematic diagram of a semiconductor chip designed by using the semiconductor integrated circuit layout method of the present invention.

FIG. 3 is a schematic view of a semiconductor chip designed by using the semiconductor integrated circuit layout method of the present invention.

FIG. 4 is a schematic view of a semiconductor chip designed using the first conventional technique.

[Explanation of symbols]

1 circuit connection information 2 layout information 3 Mask data 20,4-1 Semiconductor chip 21,4-2 Bonding pad 22 I / O buffer 23 Chip internal area 24 Basic cell placement prohibited area 25 Basic cell placement area 26, 31, 32 Placement-allowed basic cells or buffers 27,33 Basic cell or placement-allowed basic cell

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04 G06F 17/50

Claims (4)

(57) [Claims] 1. A basic cell having basic circuit functions, and
Including a mega macro with a larger circuit scale than the basic cell
A method of laying out a semiconductor integrated circuit, the chip including a chip internal region inside a semiconductor chip
The internal area generation step and the mega memory in the chip internal area are performed.
And Megamakuro arrangement step of arranging the black, the Megamakuro arranged in the Megamakuro disposing step
A basic cell that creates a basic cell placement prohibited area to include
Do contained and Le placement prohibited region generation process, the Megamakuro of the basic cell placement prohibited region
Allowable basics that generate a cell placement area
The cell placement area generation step and the basic cell placement prohibited area in the chip internal area are included.
Generate basic cell placement area
And the basic cells that can be placed in the allowable basic cell placement area
An arrangement in which an arrangement-allowed basic cell is selected from the basic cells
Allowable basic cell selection step and the placement allowance selected in the placement allowance basic cell selection step
Priority cell is preferentially placed in the allowable basic cell placement area
However, the basic cells other than the arrangement-allowed basic cells are set to the basic cells.
A layout process including the process of arranging in the cell arrangement area
In the arrangement permissible basic cell selection step, among the basic cells serially connected to the mega macro, two or more connections from the basic cell that is directly connected to the mega macro, that is, the first connection order is the first. the basic cell to rank, the layout method of the semi-conductor integrated circuit you and selects as the arrangement permissible basic cells. 2. A basic cell having a basic circuit function and the front.
Including a mega macro with a larger circuit scale than the basic cell
A method of laying out a semiconductor integrated circuit, the chip including a chip internal region inside a semiconductor chip
The internal area generation step and the mega memory in the chip internal area are performed.
And Megamakuro arrangement step of arranging the black, the Megamakuro arranged in the Megamakuro disposing step
A basic cell that creates a basic cell placement prohibited area to include
Do contained and Le placement prohibited region generation process, the Megamakuro of the basic cell placement prohibited region
Allowable basics that generate a cell placement area
The cell placement area generation step and the basic cell placement prohibited area in the chip internal area are included.
Generate basic cell placement area
And the basic cells that can be placed in the allowable basic cell placement area
An arrangement in which an arrangement-allowed basic cell is selected from the basic cells
Allowable basic cell selection step and the placement allowance selected in the placement allowance basic cell selection step
Priority cell is preferentially placed in the allowable basic cell placement area
However, the basic cells other than the arrangement-allowed basic cells are set to the basic cells.
A layout process including the process of arranging in the cell arrangement area
The provided, in the arrangement permissible basic cell selection process, a semi-conductor integrated circuit layout method for you and selects the distance between the arrangement permissible basic cells by comparing the size of the basic cell between the Megamakuro. 3. A basic cell having a basic circuit function and the front.
Including a mega macro with a larger circuit scale than the basic cell
A method of laying out a semiconductor integrated circuit, the chip including a chip internal region inside a semiconductor chip
The internal area generation step and the mega memory in the chip internal area are performed.
And Megamakuro arrangement step of arranging the black, the Megamakuro arranged in the Megamakuro disposing step
A basic cell that creates a basic cell placement prohibited area to include
Do contained and Le placement prohibited region generation process, the Megamakuro of the basic cell placement prohibited region
Allowable basics that generate a cell placement area
The cell placement area generation step and the basic cell placement prohibited area in the chip internal area are included.
Generate basic cell placement area
And the basic cells that can be placed in the allowable basic cell placement area
An arrangement in which an arrangement-allowed basic cell is selected from the basic cells
Allowable basic cell selection step and the placement allowance selected in the placement allowance basic cell selection step
Priority cell is preferentially placed in the allowable basic cell placement area
However, the basic cells other than the arrangement-allowed basic cells are set to the basic cells.
A layout process including the process of arranging in the cell arrangement area
And, in the layout step,
The basic cell including the basic cell is arranged roughly,
Schematically between the cell and the circuit block containing the mega macro
Wiring and general layout information including placement information and wiring information
Generated as a report , referring to the outline layout information,
A timing verification step of executing timing verification in consideration of wiring delay on the semiconductor integrated circuit and outputting timing information, and referring to the timing information, a specific timing included in this timing information satisfies a timing constraint condition. Timing determination step to determine whether or not, in the timing determination step, if it is determined that the specific timing does not satisfy the timing constraint condition, the basic cell existing in the wiring path related to the specific timing And a step of replacing the basic cell with a high-driving basic cell having the same logic as that of the basic cell and having a large driving capability , and a layout method for a semiconductor integrated circuit. 4. A basic cell having a basic circuit function and a front cell.
Including a mega macro with a larger circuit scale than the basic cell
A method of laying out a semiconductor integrated circuit, the chip including a chip internal region inside a semiconductor chip
The internal area generation step and the mega memory in the chip internal area are performed.
And Megamakuro arrangement step of arranging the black, the Megamakuro arranged in the Megamakuro disposing step
A basic cell that creates a basic cell placement prohibited area to include
Do contained and Le placement prohibited region generation process, the Megamakuro of the basic cell placement prohibited region
Allowable basics that generate a cell placement area
The cell placement area generation step and the basic cell placement prohibited area in the chip internal area are included.
Generate basic cell placement area
And the basic cells that can be placed in the allowable basic cell placement area
An arrangement in which an arrangement-allowed basic cell is selected from the basic cells
Allowable basic cell selection step and the placement allowance selected in the placement allowance basic cell selection step
Priority cell is preferentially placed in the allowable basic cell placement area
However, the basic cells other than the arrangement-allowed basic cells are set to the basic cells.
A layout process including the process of arranging in the cell arrangement area
And the timing threshold set in the layout process.
The layout allowance basic with a large timing margin
Of a semiconductor integrated circuit characterized by arranging cells in order
Layout method .