JP2008310527A - Layout design device and layout design method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout design device and layout design method of a semiconductor integrated circuit to erase any unnecessary stack via causing a layout wiring error. <P>SOLUTION: This layout design method includes: an error discrimination step S6 for discriminating an error of the layout wiring after a power source is wired in a grid pattern; and a stack via erasure step S20 for, when there is a layout wiring error, designating an erasure range based on error coordinates, to remove a stack via in the erasure range. In the step S20, a region obtained by multiplying x directional and y directional prescribed ranges around coordinates having the arranged wiring error by range coefficients is defined as an erasure range, and when no stack via to be erased exists in the first erasure range, the range coefficients are increased so that the erasure range can be updated, and a stack via to be erased in the updated erasure range is discriminated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a layout design apparatus and layout design method for a semiconductor integrated circuit having a grid-like power supply wiring.

  In hard macro design of LSI (Large Scale Integration) and logic circuits, layout design with high integration density has great advantages in terms of cost and operation speed. However, the bypass wiring is partially generated due to the stack via (Via) due to the mesh structure of the power supply wiring. This becomes a wiring bottleneck and increases the signal wiring delay time, which hinders speeding up. As a solution to this problem, it is possible to reduce the bypass wiring rate by eliminating the stack via and achieve high integration.

  A conventional LSI layout design apparatus will be described (for example, see Patent Document 1). FIG. 13 is a block diagram showing a configuration of a conventional LSI layout design apparatus. In FIG. 13, an LSI layout design apparatus 111 includes an FB (function block) block library (hereinafter referred to as a function block library) 101, a function block library reading unit 102, a power / clock (CLK) wiring unit 103, and a function block. Arrangement unit 104, redundant power supply wiring deletion unit 105, wiring unit 106, wiring confirmation unit 107, floor plan change unit 108, layout information output unit 109, function reduction or chip size change unit 110, control memory 112.

  Information necessary for layout design is stored in the functional block library 101 in advance, and the functional block library reading unit 102 reads necessary layout data from the functional block library 101 and passes it to the power / clock wiring unit 103. The power supply / clock wiring unit 103 performs power supply wiring and clock wiring based on the layout data read by the functional block library reading unit 102, and the layout data to which information on the power supply wiring and clock wiring is added is provided to the functional block arrangement unit 104. To pass. The functional block arrangement unit 104 arranges the functional block after the power supply wiring and the clock wiring are performed by the power supply / clock wiring unit 103, and passes the layout data to which the functional block arrangement information is added to the redundant power supply wiring deletion unit 105. .

  The redundant power supply wiring deletion unit 105 deletes the redundant power supply wiring after the functional block is arranged by the functional block arrangement unit 104 and passes the layout data to which the redundant power supply wiring deletion information is added to the wiring unit 106. The wiring unit 106 performs wiring to the functional block after the redundant power supply wiring deleting unit 105 deletes the redundant power supply wiring, and passes the layout data to which the wiring information to the functional block is added to the wiring checking unit 107.

  When the wiring by the wiring unit 106 is completed, the wiring confirmation unit 107 determines whether or not there is any wiring, and the layout data created by the above processing according to the determination result is used as the floor plan changing unit 108, the layout information output unit 109, and the like. It is passed to one of the function reduction or chip size changing unit 110. That is, the wiring confirmation unit 107 passes layout data to the floor plan changing unit 108 when it is determined that there is unwired and can be integrated, and passes layout data to the layout information output unit 109 when it is determined that there is no unwired. If it is determined that it is present and cannot be integrated, the layout data is transferred to the function reduction or chip size changing unit 110.

  The floor plan changing unit 108 changes the floor plan for the layout data delivered from the wiring confirmation unit 107 and returns the changed layout data to the functional block library reading unit 2. The layout information output unit 109 outputs the layout data passed from the wiring confirmation unit 107. The function reduction or chip size changing unit 110 reduces the function of the layout data delivered from the wiring confirmation unit 107 or changes the chip size, and returns the changed layout data to the function block library reading unit 102.

  FIG. 14 is a flowchart showing the power supply deletion processing operation of the prior art. As shown in FIG. 14, when a functional block is not arranged in a region sandwiching a pair of two-layer vertical power supply / ground wiring (step S11), the two-layer vertical power supply / ground wiring inside the region is deleted. (Step S12). The redundant power supply wiring deletion unit 105 deletes the one-layer horizontal power supply or ground wiring inside the area when the functional block is not disposed in the upper and lower one row area of the one-layer horizontal power supply or ground wiring (step S13). (Step S14). When the functional block is not arranged in the area between the pair of two-layer vertical power supply / ground wiring and the one-layer horizontal power supply or ground wiring (step S15), the redundant power supply wiring deletion unit 105 A pair of two-layer vertical power supply / ground wiring, a single-layer horizontal power supply or ground wiring, and a pair of two-layer vertical power supply / ground wiring and one-layer horizontal power supply / ground wiring cross each other. The power supply or ground via (1TH) is deleted (step S16).

Further, as a known technique for solving the same problem, there is a semiconductor device having a multilayer wiring structure described in Patent Document 2. In the technique described in Patent Document 2, the bypass wiring rate is reduced and the integration density is increased by securing a channel wiring region for a signal corresponding to a region in which a stack via in the vicinity of the bypass wiring is deleted in one vertical row or one horizontal row. I am trying.
Japanese Patent No. 3225929 Japanese Patent No. 2002-184950

  In the above-described conventional method, the mesh structure of the power supply wiring is configured such that the intersection of the X-axis wiring and the Y-axis wiring is connected by a stack via. Therefore, there are many stack vias in the entire chip. Therefore, by removing the stack vias and securing the wiring area so that the arrangement positions of some of the stack vias become wiring arrangement areas, it is possible to improve the degree of integration and reduce the bypass wiring ratio. However, if the stack via is simply deleted, the stack via is excessively deleted and the wiring resistance increases.

  A layout design apparatus for a semiconductor integrated circuit according to the present invention is a layout design apparatus for a semiconductor integrated circuit having a grid-shaped power supply wiring composed of a power supply wiring and a ground wiring, and includes an automatic placement and wiring unit for power supply wiring and placement and wiring, A design rule check unit that detects an error of the placement and routing executed by the automatic placement and routing unit, and when a placement and routing error is detected by the design rule check unit, a deletion range is specified based on the error coordinates, and the deletion range And a stack via deletion unit that performs processing for removing the stack via.

  In the present invention, unnecessary stack vias that cause placement and routing errors can be deleted by deleting the surrounding stack vias based on the coordinates at which the placement and routing errors are detected by the design rule check unit.

  According to the present invention, it is possible to provide a layout design apparatus and a layout design method for a semiconductor integrated circuit capable of eliminating an unnecessary stack via that causes a placement and routing error.

Embodiment 1 FIG.
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a layout design apparatus for a semiconductor integrated circuit having a grid power supply wiring according to the first embodiment of the present invention. As shown in FIG. 1, the layout design apparatus 10 according to the present embodiment includes an estimation & selection unit 11, a power supply database 12, a floor plan 13, an automatic placement and routing tool 14, a design rule check unit 15, and a stack via deletion unit 16. , And a stack via addition unit 17.

  The estimation & selection unit 11 estimates the power consumption of the chip, and selects a power source type by referring to the power source database 12 based on the result. In addition to determining the chip size, the floor plan 13 performs processing such as placement of macros and grouping as necessary when mounting pin assignments and macros. Processing other than the determination of the chip size is processing performed in a normal floor plan. The automatic placement and routing tool 14 performs power supply wiring, placement processing and wiring processing for the chip shape (floor plan information). In general, power supply wiring can be performed by a power supply wiring script. In the placement and wiring process, a function block (FB) is placed according to its shape or the like, and wiring to the FB is performed.

  Here, as will be described later, in this embodiment, the grid-like power supply wiring is arranged. For example, the first layer (M1) power supply wiring arranged in the vertical direction and the fourth layer arranged in the horizontal direction, for example. The power wiring of (M4) is connected at an appropriate interval by stack vias. Here, in this specification, the stacked via is a via stacked on the via, and connects the X-direction wiring of the nth layer and the Y-direction wiring of the (n + m) (m ≧ 2) layer. To do. In this case, these stacked vias may deteriorate the placement and routing. In other words, the bypass wiring is partially generated due to the stack via due to the mesh structure of the power supply wiring, which becomes a wiring neck and increases the signal wiring delay time, which may hinder speeding up. Therefore, in this embodiment, the stack via deletion unit 16 is provided to eliminate the placement and routing error by deleting the stack via that causes the placement and routing error.

  The design rule check unit 15 checks the overlap between the unplaced cells and the cells regarding the placement. Further, regarding wiring, wiring intervals, signal wiring shorts, unwiring, etc. are checked. When the design rule check unit 15 detects a placement and routing error, the stack via deletion unit 16 designates a stack via deletion range based on the error coordinates, and performs processing for removing the stack via in the stack via deletion range. Do. Specifically, an error coordinate (wiring NG location) where an error is detected by the check of the design rule check unit 15 is extracted, and a stack via deletion range is set. Then, a via deletion script to be input to the automatic placement and routing tool 14 is created based on the coordinates of the stack via deletion range. When the automatic placement and routing tool 14 executes the via deletion script, the stacked via is deleted. By removing the stack via that connects at least the metal of the three-layer structure, for example, the metal of the intermediate layer such as the second layer can be used for the placement and wiring.

  The stack via adding unit 17 determines whether or not a stack via can be added when there is no placement and routing error, and performs processing for adding a stack via if the stack via can be added. As described above, the stack via deletion unit 16 deletes the stack via originally existing in the power mesh structure in order to improve the wiring property. However, if the check by the design rule check unit 15 is OK, the stack via is deleted. If there is an unused part in the wiring within the via deletion range, a stack via is added again. By this process, the stack via can be disposed again at the place where the stack via is excessively deleted, and the power supply wiring resistance can be reduced.

  Next, a layout design method for the semiconductor integrated circuit according to the present embodiment will be described. FIG. 2 is a flowchart showing a layout design method of the semiconductor integrated circuit. As shown in FIG. 2, first, chip power consumption is estimated (step S1). A power consumption estimation result is obtained as an execution result of estimating the chip power consumption. Based on the power consumption estimation result, a power supply type is selected from the power supply database 12 (step S2). Next, in addition to determining the chip size based on the floor plan 13, in the case of mounting a pin assignment or macro, processing such as macro placement and grouping as necessary is performed (step S3). Processing other than the determination of the chip size is processing performed in a normal floor plan.

  Next, power supply wiring processing is performed (step S5). In the power wiring process, the power wiring process is performed using the chip-shaped data among the floor plan information data generated in the floor plan step S4. This power supply wiring process can be performed, for example, by generating a power supply wiring script and causing the automatic placement and routing tool 14 to execute the script. 3 and 4 are diagrams showing the power supply wiring. As shown in FIGS. 3 and 4, in the power supply wiring according to the present embodiment, VDD wiring and GND wiring are alternately arranged and arranged in a grid pattern. Here, stack vias 57, 57a, and 57b are provided in order to connect the power supply wires to each other.

  When the power supply wiring is arranged, the automatic placement / wiring tool 14 performs placement processing and wiring processing on the functional block (step S5). Thereafter, a design rule check regarding placement and routing is performed to determine whether or not there is an error (step S6). Specifically, regarding the placement, the unplaced wiring cells and the overlap of the cells are checked. As for wiring, wiring intervals, signal wiring shorts, unwiring, and the like are checked. If there is an error in the placement and routing, the process proceeds to the stack via deletion process (step S10).

  In the stack via deletion step S20, first, the wiring NG location is extracted (step S21). In this step S21, the coordinates where the wiring error is detected in the placement and routing error detection step S6 are extracted. In addition to extracting not only wiring errors but also wiring congested portions, these coordinates are hereinafter referred to as error coordinates 51 (see FIGS. 3 and 4). The error coordinates 51 can be extracted by the design rule check unit 15 performing the design rule check. Based on the extracted error coordinates 51, a stack via deletion range is calculated (step S22).

  In the calculation of the stack via deletion range, first, the stack via deletion range of a predetermined range × range coefficient “n” (52) is set in the x direction 53 and the y direction 54 with the error coordinate 51 as the center. The range coefficient n can be an integer such as 1, 2, 3,..., And is a value that is sequentially updated as will be described later. First, the stack via deletion range 55 is set by setting the range coefficient to “1”. When the stack via 57 exists in the stack via deletion range 55, the process proceeds to the next step S23.

  In the example shown in FIGS. 3 and 4, one and four stack vias 57 a exist in the stack via deletion range 55, respectively. As described above, when the stack via deletion range 55 includes the stack via, the process proceeds to the next step. In step S23, it is determined whether or not the stack via deletion range 55 is smaller than the chip size. If the stack via deletion range 55 is larger than the chip size, the process returns to step S3 and is executed again from the floor plan process.

  On the other hand, when the stack via deletion range 55 is smaller than the chip size, the stack via 57a in the stack via deletion range 55 can be deleted. In this case, a via deletion script to be input to the automatic placement and routing tool 14 is generated based on the coordinates of the stacked via deletion range 55 (step S24). Then, by executing this via deletion script by the automatic placement and routing tool 14, all the stack vias 57a in the stack via deletion range 55 are deleted (step S25). When the stacked via is deleted, the process returns to step S5 and is executed again from the placement and routing process (step S5). That is, for example, in the example shown in FIG. 3, the coordinate position from which the stack via 57a is deleted can be used for placement and routing. By using this area, placement and routing errors can be resolved.

  When the placement and routing error is extracted again in step S6, the stack via deletion step S20 is performed again. Here, when the same coordinates as above are extracted as the error coordinates 51, as shown in FIG. 3, no stack via exists in the stack via deletion range 55 because the stack via 57a has already been deleted. In this case, the range coefficient 52 for calculating the stack via deletion range is updated to a large value to obtain a stack via deletion range 56. Since there is a stack via 57b that can be deleted in the stack via deletion range 56, the processing from step S23 is executed as before. In the present embodiment, the range coefficient n is an integer such as 1, 2, 3,..., But may be other than an integer such as 1, 1.5, 2,.

  If the placement and routing error is eliminated by deleting the stack via 57 within the stack via deletion range set in this way, the process proceeds to step S7. In step S7, it is determined whether a stack via can be added (step S7). In the above-described stack via deletion step S20, the stack via is deleted for improving the wiring property. Thereafter, the deleted stack via (for example, the stack vias 57a and 57b) exists in the stack via deletion range. Among them, there may be a portion that is unused in the placement and routing (step S5). In other words, in the example shown in FIG. 3, there is only one stack via 57a, 57b in each of the stack via deletion ranges 55, 56. However, depending on how the range coefficient is set, a plurality of stack vias are included in the stack via deletion range. May exist. In that case, the positions of all the stacked vias 57a and 57b are not necessarily used for the placement and wiring. That is, among the deleted stack vias 57a and 57b, it is determined that a stack via can be added again to a portion that is unused in the placement and routing, and the stack via is deleted in order to restore the portion where the stack via is excessively deleted. A stack via is added to the deleted location (step S8). If it is not possible to add a stack via in step S7, the process ends.

  The stacked via deletion range calculation method will be described in more detail. As shown in FIG. 3 and FIG. 4, a coefficient for determining the range of stack vias to be deleted with respect to the wiring error coordinate 51 is given by a range coefficient 52. As shown in FIG. 3, the value of the range coefficient 52 is determined by the design standard of the layout design, thereby determining the range coefficient. Alternatively, if not determined by the design criteria, the stack via deletion range can be updated in units of power supply pitch or via pitch as shown in FIG.

  The stack via deletion unit 16 uses the wiring error coordinate 51 as an error coordinate value, and a stack obtained by multiplying the range coefficient 52 by the value in the X direction 53 and Y direction 54 of a predetermined range around the error coordinate value. A via deletion range 55 is set. Here, when the stack via 57 is not included in the stack via deletion range 55, the range coefficient 52 is updated, and the stack via deletion range is expanded in both the X direction 53 and the Y direction 54 in both ± directions. The range is 56. The process of updating the range coefficient 52 and updating the stack via deletion range is repeatedly executed until there is a stack via 57 within the stack via deletion range. That is, when there is no stack via in the stack via deletion range 56, the range coefficient is updated or the stack via deletion range 57 expanded by the power supply pitch or the via pitch is set, and whether or not the stack via is included in the range. Determine whether.

  When the stack via 57 is included in the stack via deletion range in this way, the stack via 57 within the stack via deletion range is deleted, and it is determined whether or not the placement and routing error is resolved. If it is not solved, the stack via deletion range is updated until another stack via is included.

  In the present embodiment, when the placement and wiring becomes the wiring NG, the stack via deletion range is calculated based on the wiring NG location, and the stack via within the stack via deletion range is deleted. In this way, the stack via deletion range is set, and the stack via deletion is repeatedly updated until the placement and routing error is resolved, thereby deleting the stack via. Then, by performing placement and routing again after this, the detour wiring rate around the stack via is reduced, and the speed is increased by shortening the signal wiring delay time. That is, by setting the stack via deletion range in this way and sequentially deleting the stack vias, it is possible to delete only the stack vias causing the placement and routing error. Furthermore, by determining whether a stack via can be added to the place where the stack via has been deleted and adding the stack via, the deleted stack via is re-added to the stack via placement position that has not been used for placement and routing, and wiring is performed. The resistance can be reduced.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. FIG. 5 is a diagram showing a layout design apparatus for a semiconductor integrated circuit according to the present embodiment. As shown in FIG. 5, the layout design apparatus 10b according to the present embodiment further includes a power analysis tool 18 and a power reinforcing wiring adding unit 19 in addition to the configuration of the layout design apparatus 10 according to the first embodiment shown in FIG. . The power analysis tool 18 detects a power analysis error that is an error corresponding to the amount of noise generated in the power wiring. Specifically, the power supply analysis root 18 determines whether or not electromigration (EM: phenomenon in which the atomic arrangement of metal used for wiring is disturbed and disconnected due to excessive current flow) occurs as a power supply analysis error. And / or it is detected whether the voltage drop (IR-drop) of a power supply wiring is within a reference value. That is, the power supply is verified based on the design data after placement and routing and the power supply information (designation of the power supply point). If the values of EM and IR drop are not within the standard, the error coordinates are extracted.

  When the power analysis tool 18 detects that the value of the EM or IR drop exceeds the reference value, the power reinforcing wiring adding unit 19 specifies the power reinforcing wiring additional range based on the error coordinates, and the power reinforcing wiring Add power reinforcement wiring within the additional range. Specifically, first, a range (coordinates) in which power supply wiring can be added is calculated. Then, a power supply wiring script is created based on these coordinates. When the automatic placement and routing tool 14 executes this power supply wiring script, the power supply wiring is added.

  Next, a layout method of the semiconductor integrated circuit according to the present embodiment will be described. 6 and 7 are flowcharts showing a layout method of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 6, the layout method of the semiconductor integrated circuit according to the present embodiment includes an EM and IR drop verification step S9 as a subsequent step of the stack via addition step S8, and a determination step whether or not the verification result is OK. If S20 and the verification result is not OK, it further includes a power reinforcing wiring addition step S20. Steps S1 to S8 and step S10 are the same as those in the first embodiment, and a description thereof is omitted.

  In step S9, the EM / IR drop is verified. In the verification of the EM / IR drop, the power supply analysis tool 18 performs verification based on the design data after placement and routing and the power supply information (designation of the power supply point). Next, in step S10, it is determined whether or not the value of the EM / IR drop is within the reference. If it is not within the set standard, it is determined as an error. In the case of error determination, the process proceeds to the power reinforcing wiring adding step S30.

  In the power reinforcing wiring adding step S30, first, EM and IR-DropNG locations are extracted (step S31). In the extraction of the NG location, the error coordinates are extracted by the power source analysis tool 18 in the same manner as the wiring error in the placement and routing tool. Next, based on the error coordinates, a power reinforcing wiring additional range is calculated (step S32). The calculation of the power reinforcing wiring additional range is performed in the same manner as the calculation of the stack via deletion range described above. That is, by setting a range in the X direction and the Y direction having a predetermined range around the error coordinates, the power reinforcing wiring additional range is set. Then, it is determined whether or not the power supply wiring can be added. Then, the range coefficient is increased until the power supply wiring can be added, and the power reinforcing wiring addition range is updated. When the power reinforcing wiring addition range becomes a range where the power wiring can be added, it is determined whether or not the power reinforcing wiring adding range is smaller than the chip size (step S33).

  If the power reinforcing wiring addition range is larger than the chip range, the process returns to the floor plan process in step S3. When the power reinforcement wiring addition range is smaller than the chip size, a power reinforcement wiring addition script is created by the power reinforcement wiring addition unit 19 (step S34), and the power reinforcement wiring addition script is executed by the automatic placement and routing tool 14. Then, a power reinforcing wiring is added (step S35). When the power reinforcing wiring is added in this way, the EM / IR drop verification in step S9 is performed again. The EM and IR-Drop verification is performed again, the determination of the EM and IR-Drop verification in step S10 is OK, and the layout design is finished.

  Next, a method for calculating the power reinforcing wiring additional range will be described with reference to FIG. As shown in FIG. 8, a coefficient for determining a range in which the power reinforcing wiring can be arranged is given by a range coefficient (62). The range coefficient 62 can be determined by the design standard of layout design. The EM and IR drop error coordinates 61 are multiplied by a range coefficient m to a predetermined range in the X direction 63 and the Y direction 64 to obtain a power enhancement wiring additional range. Note that any method of multiplying the range coefficient m may be used.

  Then, the power reinforcing wiring range 65 is expanded to the power reinforcing wiring range 66 in the ± direction according to the range coefficient 52 in the X direction 63 and the Y 64 direction with the EM and IR drop error coordinates 61 as a base point. The expansion of the power reinforcing wiring range is repeatedly performed until the power reinforcing wiring 67 can be wired.

  In this embodiment, when EM or IR-Drop verification results in NG, a floor plan change or a logic change is performed by adding a power reinforcement wiring (and a stack via) to an empty area within the power reinforcement wiring addition range. By reducing the number of repetitions by logical function reduction and layout conversion, and by preventing problems caused by EM and IR-Drop of power supply wiring, it is possible to significantly reduce design man-hours and prevent functional degradation.

  That is, if the stack via is simply deleted to secure a wiring area to improve the degree of integration and reduce the detour wiring rate, problems due to EM and IR-Drop of the power supply wiring become conspicuous as the process becomes finer. Usually, in order to determine which area (location) on the LSI chip the logic function is to be placed, the size of the block that realizes each logic function is obtained so that no dead area (dead space) remains on the chip. Although the arrangement of the blocks (floor plan) is performed, there is a problem in that a return to the floor plan occurs due to the above-mentioned trouble. On the other hand, in this Embodiment, the malfunction by EM and IR-Drop can be prevented by verifying EM and IR-Drop.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. In the present embodiment, the power supply additional wiring strengthening unit 19 determines that the coordinates where the location (error) where the value of the EM or IR drop exceeds the reference value has occurred based on the analysis result of the power analysis tool 18 is a stack via. It is determined whether it is within the deletion range. If the coordinates where the error has occurred are within the stack via deletion range, the floor plan unit 13 redoes the floor plan. The configuration of the layout design apparatus is the same as that of the second embodiment.

  FIG. 9 and FIG. 10 are flowcharts showing a stack via deletion process and a power reinforcing wiring addition process, respectively, in the layout design method intended for semiconductor integration according to the present embodiment. As shown in FIGS. 9 and 10, in the present embodiment, the stack via deletion process S40 is different from the semiconductor integrated circuit layout method according to the second embodiment shown in FIGS. 6 and 7 in the stack via deletion process S40. A range coordinate calculation step S41 is added. Further, the power reinforcing wiring adding step S50 includes a step S51 for determining whether or not the EM / IR drop NG location is within the stack via deletion range. Other steps are the same as those in the second embodiment.

  That is, in the stack via deletion step S40, the stack via deletion range coordinates are calculated after the stack via deletion step in step S25 (step S41). The stack via deletion range coordinate is a coordinate indicating the stack via deletion range determined to be smaller than the chip size in step S23 among the stack via deletion range calculated in step S22.

  Next, in the power enhancement wiring addition step S50, when the power enhancement wiring addition range in step S33 is smaller than the chip size, the EM / IR drop NG coordinates extracted in step S31 are within the stack via deletion range coordinates calculated in step S41. It is determined whether or not there is (step S51). Within the stack via deletion range, the stack via is basically deleted in order to improve the wiring property, that is, the place and wiring property including the error coordinate in the placement and wiring is not good. Therefore, it is difficult to add the power reinforcing wiring within the stack via deletion range. For this reason, if the power supply enhancement wiring addition range is included in the stack via deletion range, an error is determined and the process is repeated from the floor plan in step S3.

  In the present embodiment, it is verified whether or not the EM / IR drop NG coordinates are included in the stack via deletion range calculated in the stack via deletion step S40. Reduction of the design man-hours and prevention of functional degradation can be achieved by reducing the power supply wiring and preventing problems caused by EM and IR-Drop.

Embodiment 4 FIG.
Next, a fourth embodiment of the present invention will be described. In the present embodiment, the power supply additional wiring strengthening unit 19 analyzes whether or not the number of flip-flops included in the predetermined range including the coordinates where the EM or IR drop error occurs is within the reference value as a result of analysis by the power analysis tool 18. Determine whether. Then, when the number of flip-flops included in the predetermined range including the coordinates where the EM or IR drop error occurs is equal to or more than the reference value, the estimation & selection unit 11 re-estimates the power consumption of the semiconductor integrated circuit. . The configuration of the layout design apparatus is the same as that of the second embodiment.

  FIG. 11 and FIG. 12 are flowcharts showing a stack via deletion step and a power reinforcing wiring addition step in the layout design method intended for semiconductor integration according to the present embodiment, respectively. As shown in FIGS. 11 and 12, in the present embodiment, the stack via deletion step S60 is within the deletion range as compared with the semiconductor integrated circuit layout method according to the second embodiment shown in FIGS. Flip-flop (F / F) number calculation step S61 is added. Further, in the power reinforcing wiring adding step S70, a step S71 for determining whether or not the F / F number at the EM / IR-DropNG location is within the reference range is provided. Other steps are the same as those in the second embodiment.

  The calculation of the F / F number within the stack via deletion range in step S61 can be obtained by comparing the stack via deletion range with the F / F arrangement coordinates. The number of F / Fs included in the stack via deletion range is counted. In the present embodiment, the number of F / Fs in the unit area of the chip is estimated by counting the number of F / Fs included in the stack via deletion range.

In the power reinforcing wiring adding step S70, it is determined whether or not the F / F number in the predetermined area is within the reference range for the error coordinates extracted in step S31. In this determination, when there are a plurality of error coordinates, it is determined whether or not the F / F number in each predetermined area including all the error coordinates is within the reference range. In this case, considering the process and the like, the allowable F / F number of the unit area value is examined. For example, when the allowable F / F number within 100 μm ² is based on, for example, 100, the F counted in the above step S61. It is determined whether the / F number is within this standard.

  In this embodiment, the determination is made based on the number of F / Fs counted in step S61. However, the coordinates of a predetermined area including the error coordinates extracted in step S31 are extracted, and these coordinates and F / Of course, it is possible to calculate the number of F / Fs in the predetermined area from the comparison of the arrangement coordinates of F and determine whether or not this is within the reference value.

  Here, when none of the F / F numbers in the predetermined area including all the error coordinates satisfy the reference value, the process returns to the power estimation process in step S1. In this process, the chip power consumption is estimated. If the answer is No in step S71, the number of F / Fs included in the chip is reviewed in this process.

  In the present embodiment, the power enhancement included in the power enhancement wiring addition step S70 is performed by comparing the F / F number in the predetermined area including the EM and IR-DropNG locations in the power enhancement wiring addition step S70 with the reference value. The range calculation step S32, the determination step S33 whether or not the power supply addition range is smaller than the chip size, the power strengthening wiring addition script creation step S34, and the power strengthening wiring addition step S35 can be omitted, and the design man-hour can be reduced. it can.

The embodiment described above has the following effects. That is,
1. Since the detour wiring rate around the stack via is reduced, it is possible to increase the speed by shortening the signal wiring delay time. Furthermore, by reducing or preventing the number of iterations due to floor plan changes, logic changes, and logic function reductions accompanying accommodation of unwired areas, it is possible to significantly reduce design man-hours and prevent functional degradation.
2. EM and IR-Drop can be predicted from the layout design data after placement and routing by the coordinates of the location where the stack via is removed and the number of additional stack vias at that location.
3. Layout design man-hours by reducing the number of iterations to return to the floor plan by adding power reinforcing wiring (stack via) in the empty area within the power reinforcing wiring additional range in order to improve defects due to EM and IR-Drop of power wiring Can be reduced.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

1 is a block diagram showing a layout design apparatus for a semiconductor integrated circuit having a grid power supply wiring according to a first embodiment of the present invention; 4 is a flowchart showing a layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention; It is a figure explaining the stacked via deletion process in Embodiment 1 of the present invention. Similarly, it is a figure explaining the stack via deletion process in Embodiment 1 of the present invention. It is a figure which shows the layout design apparatus of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is a flowchart which shows a stack via deletion process among the layout design methods of the semiconductor integration intention concerning Embodiment 2 of this invention. It is a flowchart which shows a power reinforcement wiring addition process among the layout design methods of the semiconductor integration intention concerning Embodiment 2 of this invention. It is a figure explaining the calculation method of the power supply reinforcement | strengthening wiring additional range in Embodiment 2 of this invention. It is a flowchart which shows a stack via deletion process among the layout design methods of the semiconductor integration intention concerning Embodiment 3 of this invention. It is a flowchart which shows a power supply reinforcement | strengthening wiring addition process among the layout design methods of the semiconductor integration intention concerning Embodiment 3 of this invention. It is a flowchart which shows a stack via deletion process among the layout design methods of the semiconductor integration intention concerning Embodiment 4 of this invention. It is a flowchart which shows a power reinforcement wiring addition process among the layout design methods of the semiconductor integration intention concerning Embodiment 4 of this invention. It is a block diagram which shows the structure of the conventional LSI layout design apparatus. It is a flowchart which shows the conventional power supply deletion process operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Estimate & selection part 12 Power supply database 13 Floor plan 14 Automatic placement and routing tool 15 Design rule check part 15 Automatic wiring tool 16 Stack via deletion part 17 Stack via addition part 18 Power analysis tool 19 Power reinforcement wiring addition part 51 and 61 Error coordinates 52, 62 Range coefficient 53, 63 X direction 54, 64 Y direction 55, 56 Stack via deletion range 57 Stack via 65, 66 Power supply enhancement wiring range 67 Power supply enhancement wiring

Claims (15)

A layout design apparatus for a semiconductor integrated circuit having a grid-like power wiring,
An automatic placement and routing unit for performing power supply wiring and placement and routing;
A design rule check unit for detecting an error of the placement and routing executed by the automatic placement and routing unit;
A semiconductor integrated circuit having a stack via deletion unit that designates a deletion range based on the error coordinates and performs a process for removing a stack via in the deletion range when an error in the placement and routing is detected by the design rule check unit Layout design equipment. 2. The apparatus further comprises a stack via adding unit that determines whether or not a stack via can be added when the placement and routing error is eliminated, and performs processing for adding a stack via if it can be added. The layout design apparatus of the semiconductor integrated circuit as described. A power analysis unit that detects a power analysis error, which is an error according to the amount of noise generated in the power wiring,
The power supply analysis unit further includes a power supply additional wiring reinforcement unit that specifies a wiring addition range based on the error coordinates and adds a power reinforcement wiring within the wiring addition range when the power analysis error is detected. 3. The layout design apparatus for a semiconductor integrated circuit according to claim 1, wherein: The layout design apparatus for a semi-semiconductor integrated circuit according to claim 3, wherein the power supply analysis unit detects whether electromigration occurs and / or whether the voltage drop of the power supply wiring is within a reference value. It has a floor plan section that determines the floor plan,
The power supply additional wiring reinforcement unit determines whether or not the coordinates where the power analysis error occurs are within the deletion range,
5. The layout design apparatus for a semiconductor integrated circuit according to claim 3, wherein the floor plan unit redoes the floor plan if the coordinates where the power analysis error occurs are within the deletion range. A power estimation unit for estimating the power consumption of the semiconductor integrated circuit;
The power supply additional wiring reinforcement unit determines whether or not the number of flip-flops included in a predetermined range including coordinates where the power supply analysis error occurs is within a reference value,
The power estimation unit re-estimates the power consumption of the semiconductor integrated circuit when the number of flip-flops included in a predetermined range including the coordinates where the power analysis error has occurred is equal to or greater than a reference value. The layout design apparatus for a semiconductor integrated circuit according to claim 3. The stack via deletion unit sets, as a first deletion range, an area obtained by multiplying a predetermined range in the x direction and the y direction by a first range coefficient around a coordinate where a placement and routing error has occurred. If there is no stack via to be deleted, the area obtained by updating the first range coefficient to a large value and multiplying the predetermined range is set as the second deletion range, and the stack via to be deleted in the second deletion range. 7. The layout design apparatus for a semiconductor integrated circuit according to claim 1, wherein whether or not there exists is determined. The stack via deletion unit sets a predetermined range in the x direction and the y direction around the coordinates where the placement and routing error occurs as a first deletion range, and when there is no stack via to be deleted in the first deletion range Setting a second deletion range in which the x direction and the y direction of the first deletion range are increased by the power supply pitch or via pitch, and determining whether or not there is a stacked via to be deleted in the second deletion range. 7. The layout design apparatus for a semiconductor integrated circuit according to claim 1, wherein the layout design apparatus is a semiconductor integrated circuit layout design apparatus. The power supply additional wiring strengthening unit sets a region obtained by multiplying a predetermined range in the x direction and the y direction by a second range coefficient around the coordinates where the power analysis error has occurred as a first wiring additional range. When the power supply wiring cannot be added to the wiring addition range, the area obtained by updating the second range coefficient to a large value and multiplying the predetermined range is set as the second wiring addition range, and the power supply wiring is added to the second wiring addition range. The layout design apparatus for a semiconductor integrated circuit according to claim 3, wherein it is determined whether or not it can be added. The power supply additional wiring reinforcement unit sets a predetermined range in the x direction and the y direction around the coordinates where a power analysis error has occurred as a first wiring additional range, and when the power wiring cannot be added to the first wiring additional range, A second wiring addition range is set by increasing the x direction and y direction of the first wiring addition range by the power supply pitch or via pitch, and it is determined whether or not a power supply wiring can be added to the second wiring addition range. The layout design apparatus for a semiconductor integrated circuit according to claim 3. A layout design method for a semiconductor integrated circuit having a grid-like power supply wiring,
An error determination step for determining an error in the arrangement and wiring after executing the power supply wiring and the arrangement and wiring; and
A layout design method for a semiconductor device, comprising: a stack via deletion step of designating a deletion range based on an error coordinate and removing a stack via in the deletion range when there is an error in the placement and routing. The semiconductor device according to claim 11, further comprising a stack via addition step of determining whether a stack via can be added when the placement and routing error is eliminated, and adding a stack via if it can be added. Layout design method. A power error detection process for detecting a power analysis error, which is an error corresponding to the amount of noise generated in the power wiring,
The power supply additional wiring strengthening step of designating a wiring additional range based on the error coordinates when the power analysis error is detected and adding a power reinforcing wiring within the wiring additional range. 13. A layout design method for a semiconductor integrated circuit according to 11 or 12. It has a floor plan process that determines the floor plan,
In the power supply additional wiring strengthening step, it is determined whether or not the coordinates where the power analysis error occurs are within the deletion range. If the coordinates where the power analysis error occurs are within the deletion range, the floor plan is determined. The layout design method for a semiconductor integrated circuit according to claim 13, wherein the process is repeated. A power estimation process for estimating the power consumption of the semiconductor integrated circuit;
In the power supply additional wiring strengthening step, it is determined whether or not the number of flip-flops included in a predetermined range including the coordinates where the power analysis error occurs is within a reference value, and the predetermined including the coordinates where the power analysis error occurs 15. The layout design method for a semiconductor integrated circuit according to claim 13, wherein when the number of flip-flops included in the range is equal to or greater than a reference value, the power estimation step is performed again.

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