JP2006294707A - Semiconductor integrated circuit and method of wiring the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems associated with microfabrication of semiconductor processes such as wiring congestion, crosstalk, and timing errors, without any increase in area. <P>SOLUTION: When it is determined that there is wiring congestion (step S202) after arrangement/wiring (step S201), the suspected area is specified (step S203), and only that area is locally expanded until the value of a necessary wiring amount/maximum wiring amount ratio in this area becomes less than 1 to locally secure wiring resources (step S204). When the value of the necessary wiring amount/maximum wiring amount ratio becomes less than 1, the wiring grid width is determined (step S205) and rearrangement and rewiring are conducted (step S206). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring method for a semiconductor integrated circuit and a semiconductor integrated circuit that can solve the problems of wiring congestion, timing, and crosstalk.

  In recent years, with the miniaturization of semiconductor processes, System On Chip (hereinafter referred to as SOC) equipped with various functions has become mainstream. In SOC, a system that previously required several chips can be replaced with one chip. By using a single chip, wiring between chips can be omitted, and by reducing the number of mounted chips, space can be saved, and cost reduction can be realized. In addition, it has become possible to handle a large amount of data by increasing the speed of the computer, and there are many opportunities for the SOC to be designed flat rather than hierarchically. The advantages of the flat design are that there is no area loss at the boundary of the hierarchy, that all the wiring resources can be used, and that it is possible to save time and effort for creating constraints for each hierarchy.

However, miniaturization of semiconductor processes also includes problems. One of the reasons is that since the wiring thickness and wiring width have become smaller due to the recent miniaturization of semiconductor processes, the resistance of the wiring pattern that operates at a high frequency is reduced. That is, since the current density increases as the operating frequency increases, increasing the speed increases the burden on fine wiring patterns and is one of the causes of reducing circuit reliability. In order to solve such a problem, it is necessary to design the wiring pattern to be thick, but in order to make the wiring pattern thick, it is necessary to widen the wiring interval. However, in order to widen the wiring interval, the area must be increased, resulting in a loss in area. Here, in Patent Document 1, in order to solve the problem that the circuit reliability is reduced and the area is lost due to such high speed, as a means of thickening the wiring pattern without increasing the entire area. In the high-frequency operation region in the circuit, a method is proposed in which a wide wiring grid different from other regions is set to increase the wiring width.
Japanese Patent Laid-Open No. 61-10253

  Another problem associated with the miniaturization of the semiconductor process is that, depending on the floor plan, the wiring of distant blocks can wrap around and local wiring congestion occurs. Here, the minimum wiring interval is a value determined by the ability of the process, and the layout tool performs wiring based on the minimum wiring interval. This reference is called a wiring grid. The wiring grid set in the wiring layer is not changed after it is set at the beginning of the layout. And wiring is wired on the wiring grid like a mesh. Therefore, when wiring congestion occurs, in order to eliminate this, it is necessary to widen the area and to redo the wiring for the whole. However, such a method results in an area loss.

  Here, focusing on the technique of Patent Document 1 that proposes a method of providing a plurality of types of wiring grids without increasing the area, a method of eliminating wiring congestion is also conceivable, but the method described in Patent Document 1 This is a method in which the grid width is determined in advance by paying attention to the circuit operation at the stage before layout. Therefore, in this case as well, there is a conventional problem that the wiring grid set at the beginning of the layout cannot be changed later, so that the problem of wiring congestion occurring in the layout stage can be solved. Not available.

  Further, as an example in which a problem caused by a fine process of a semiconductor is remarkable, a malfunction due to the influence of crosstalk is further given. This malfunction occurs because the wiring interval in the same wiring layer is shortened as the miniaturization progresses, and as a result, the side coupling capacitance becomes large and is easily affected by crosstalk. In order to avoid this, if the wiring grid is set with a large wiring interval, crosstalk problems and timing problems are less likely to occur. However, if the wiring interval increases and the wiring grid decreases, the wiring resources Less. When the wiring resources are reduced, there is a possibility of locally causing wiring congestion in a large-scale layout such as an SOC including a number of blocks. Therefore, if a crosstalk problem occurs, increase the wiring interval to reduce the side coupling capacity while securing the wiring resources, that is, increase the area to increase the wiring interval and reduce the wiring grid interval. It is avoided by opening it. However, in the same way as in the case of the above-described elimination of wiring congestion, the area is lost by the increased amount.

  In order to solve the above-described problems, an object of the present invention is to solve the problems of wiring congestion, crosstalk, or timing error caused by the narrowing of the wiring interval without increasing the area.

  In order to achieve the above object, in the present invention, a ratio of a function of the number of wirings to a function of the number of wiring resources is calculated for each predetermined area, and a value based on the calculation result is used to calculate each predetermined area. By determining a new wiring grid for the above, an error that requires rewiring such as wiring congestion is eliminated without increasing the area of the semiconductor integrated circuit.

  In other words, the wiring method for a semiconductor integrated circuit according to the first aspect of the present invention is the wiring method for a semiconductor integrated circuit composed of a plurality of circuit blocks, which is designed using a wiring grid having a plurality of types of pitches. In addition, a rewiring verification step for verifying the necessity of rewiring due to an error in the semiconductor integrated circuit, and a predetermined region including a region requiring rewiring based on a verification result obtained in the rewiring verification step Based on the ratio calculated in the rewiring area designating step, the rewiring area designating process for calculating the ratio between the value based on the number of wirings and the value based on the number of wiring resources for the predetermined area And a wiring grid width determining step for determining a new wiring grid different from the reference wiring grid set for the entire wiring layer.

  According to a second aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the first aspect, the rewiring area designating step is an area where the rewiring is required based on the verification result obtained in the rewiring verification process. Calculating an evaluation value based on a ratio of a function of the number of wirings to a function of the number of wiring resources for the predetermined area specified by the area specifying step; An evaluation step of determining whether or not the calculated evaluation value is within a predetermined range and returning to the processing of the region specifying step when the calculated value is not within the predetermined range, wherein the region specifying step includes the evaluation When the process is returned from the process, the new predetermined area including the predetermined area after the determination by the evaluation process is specified, and the wiring grid width determination process is determined in the evaluation process. More, when the evaluation value is determined to be within the predetermined range, and determines the new wiring grid to be set to the new predetermined area based on the evaluation value.

  According to a third aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the second aspect, the rewiring verification step verifies the necessity of rewiring due to wiring congestion, and the region designation step includes the rewiring. According to the verification result obtained in the verification process, a region including a region where wiring congestion occurs is designated as the predetermined region.

  According to a fourth aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the second aspect, the rewiring verification step verifies the necessity of rewiring due to crosstalk, and the region designation step includes the rewiring. A region including a region where crosstalk occurs is designated as the predetermined region based on the verification result obtained in the verification step.

  According to a fifth aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the second aspect, the rewiring verification step verifies the necessity of rewiring due to a timing error, and the region designation step includes the rewiring. A region including a region where a timing error has occurred is designated as the predetermined region based on the verification result obtained in the verification step.

  A wiring method for a semiconductor integrated circuit according to a sixth aspect of the present invention is the wiring method for a semiconductor integrated circuit composed of a plurality of circuit blocks, which is designed by using a wiring grid having a plurality of types of pitches. A rewiring verification step for verifying the necessity of rewiring due to an error in the semiconductor integrated circuit, and a wiring grid width determination step for determining a new wiring grid for eliminating the error obtained by the rewiring verification step; An area designating step for designating a predetermined area including an area that requires rewiring based on the verification result obtained in the rewiring verification process; and for the predetermined area designated by the area designating process, An evaluation value based on a ratio of the function to the function of the number of wiring resources is calculated, it is determined whether the calculated evaluation value is within a predetermined range, and within the predetermined range If there is not, the process returns to the process of the area designating step, and if it is within the predetermined range, the process of determining the predetermined area is included, and the process of designating the area is returned from the evaluation process. In this case, a new predetermined area including the predetermined area after the determination in the evaluation step is specified.

  According to a seventh aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the sixth aspect, the rewiring verification step verifies the necessity of rewiring due to crosstalk, and the region designation step includes the rewiring. A region including a region where crosstalk occurs is designated as the predetermined region based on the verification result obtained in the verification step.

  According to an eighth aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the sixth aspect, the rewiring verification step verifies the necessity of rewiring due to a timing error, and the region designation step includes the rewiring. A region including a region where a timing error has occurred is designated as the predetermined region based on the verification result obtained in the verification step.

  According to a ninth aspect of the present invention, there is provided a wiring method for a semiconductor integrated circuit according to a ninth aspect of the present invention, wherein the wiring method is set for the entire wiring layer in a wiring method for a semiconductor integrated circuit composed of a plurality of circuit blocks. A uniform wiring grid changing step for uniformly changing a reference wiring grid to a wiring grid of a predetermined pitch, and the placement and wiring after the placement and wiring are performed based on the wiring grid of the predetermined pitch changed by the uniform wiring grid changing step For a semiconductor integrated circuit, a rewiring verification process for verifying the necessity of rewiring due to wiring congestion, and a predetermined area including an area that requires rewiring are specified by the verification result obtained in the rewiring verification process. And a rewiring area designating step for calculating a ratio between a value based on the number of wirings for the predetermined area and a value based on the number of wiring resources, Serial based on the ratio calculated by rewiring region specifying step, characterized in that it comprises a wire grid width determining step of determining a different new wiring grid and the wiring grid of the predetermined pitch.

  According to a tenth aspect of the present invention, in the wiring method for a semiconductor integrated circuit according to the ninth aspect, in the rewiring area designating step, an area requiring rewiring is determined based on the verification result obtained in the rewiring verification process. Calculating an evaluation value based on a ratio of a function of the number of wirings to a function of the number of wiring resources for the predetermined area specified by the area specifying step; An evaluation step of determining whether or not the calculated evaluation value is within a predetermined range and returning to the processing of the region specifying step when the calculated value is not within the predetermined range, wherein the region specifying step includes the evaluation When the process is returned from the process, a new predetermined area that is expanded and includes the predetermined area after the determination in the evaluation process is designated, and the wiring grid width determination process is performed in the evaluation process. Accordingly, when the evaluation value is determined to be within the predetermined range, and determining a new routing grid to be set to the predetermined region based on the evaluation value.

  The semiconductor integrated circuit according to claim 11 is a semiconductor integrated circuit comprising a plurality of circuit blocks, wherein the plurality of circuit blocks include at least a circuit block having a plurality of regions respectively wired with different pitches. It is characterized by including one.

  According to a twelfth aspect of the present invention, in the semiconductor integrated circuit according to the eleventh aspect, the circuit block including the plurality of regions includes a boundary line between adjacent regions among the plurality of regions, and the A connection region having connection wirings for connecting wirings having different pitches is provided.

  According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit according to the twelfth aspect, the connection wiring includes oblique wiring.

  According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit according to the eleventh aspect, a boundary line between adjacent regions of the plurality of regions is the wiring of the different pitches included in each of the adjacent regions. A contact is provided only on one of the two.

  As described above, according to the first to fifth aspects of the present invention, only an area in which an error based on the wiring is generated is detected, and an error in the predetermined area is corrected by expanding only the predetermined area including the detected error area. The number of wiring resources that can be eliminated is secured, and a new wiring grid is created based on an evaluation value expressed by a ratio using a value based on the number of wirings and a value based on the number of wiring resources for a predetermined area where the number of wiring resources can be secured. Determine and eliminate errors based on wiring locally without increasing the area of the semiconductor integrated circuit.

  According to the sixth to eighth aspects of the present invention, only a region in which an error based on wiring is detected is detected, a new wiring grid that can eliminate the error based on wiring is determined in advance, Specify an area. Then, the predetermined area when the new wiring grid is used is adjusted based on an evaluation value represented by a ratio using a value based on the number of wirings and a value based on the number of wiring resources for the predetermined area, Ensure the number of wiring resources that can solve the problem. Thereby, the error based on the wiring is locally eliminated without increasing the area of the semiconductor integrated circuit.

According to the ninth and tenth aspects of the present invention, after the wiring grid is uniformly changed, the presence / absence of wiring congestion is determined, and the wiring grid is locally changed only for the area where the wiring congestion occurs. Therefore, for example, in consideration of problems such as crosstalk, it is possible to change the wiring grid only in an area where wiring congestion occurs after the wiring grid interval is set to be wider in advance.
In the inventions according to claims 11 to 14, since regions having different wiring grid intervals can be set locally, it is possible to deal with a case where local wiring congestion is eliminated without increasing the entire area.

  As described above, according to the first to eighth aspects of the invention, by expanding only the region in which an error has occurred based on the wiring, it is possible to secure a sufficient number of wiring resources to eliminate the error. An error based on the wiring caused by the miniaturization of the process can be locally solved only for a predetermined region without increasing the area of the semiconductor integrated circuit.

  According to the ninth and tenth aspects of the present invention, the reference wiring grid of the entire semiconductor integrated circuit is changed in advance to a wiring grid that does not cause an error based on wiring such as crosstalk. Since the wiring grid is changed so that only the area where the wiring congestion occurs is specified locally and the number of wiring resources can be secured, the side coupling capacitance is set in consideration of crosstalk and timing errors. In addition, the wiring grid can be laid out in a smaller area only in an area where wiring resources are required due to wiring congestion.

  According to the invention described in claims 11 to 14, since different wiring grids can be set locally, the wiring grid is changed only in a region where the wiring congestion occurs without increasing the area, thereby reducing the wiring congestion. It can cope with the case to resolve.

(First embodiment)
FIG. 1 shows one circuit block such as a high-frequency circuit block among semiconductor integrated circuits composed of a plurality of circuit blocks. FIG. 1 shows a state in which the wiring is changed with respect to a predetermined area in a wiring grid (hereinafter referred to as a reference wiring grid) that is uniformly defined in the entire wiring layer of the semiconductor integrated circuit. Show. The reference wiring grid is set from the minimum wiring interval (wiring pitch) determined by the ability of the process.

  Reference numeral 13 denotes a reference wiring grid interval uniformly defined in the entire wiring layer, and 10, 11 and 12 are locally set wirings so as to be different from the reference wiring grid interval 13. This is the grid area. In the enlarged partial view of the region 10, W indicates a wiring, and 14 indicates the interval of the wiring grid in the region 10.

  In the present embodiment, a method of performing wiring by locally changing the wiring grid in a layout causing wiring congestion will be described.

  Wiring congestion in the layout usually occurs due to local concentration of wiring. This is largely due to the cell arrangement. As a workaround, set a wiring grid that is larger than the original reference wiring grid for areas that are likely to be congested, and let the layout tool recognize that the area is difficult to route, and then re-execute placement and routing Thus, local wiring congestion can be avoided.

  FIG. 2 shows a flowchart of a wiring method for eliminating local wiring congestion by locally changing the wiring grid interval.

  First, in step S201, predetermined elements are arranged and wired, and then in step S202 (rewiring verification process), an error occurs due to wiring congestion caused by wiring in the entire wiring layer. Search for. Here, if the wiring congestion has occurred in the verification result of step S202 and an area requiring rewiring is indicated, the process proceeds to step S203 (area specifying step), and the area where the wiring congestion has occurred is determined. Specify a predetermined area to include. In the designated predetermined area, the maximum wiring amount and the necessary wiring amount are counted.

  Here, the maximum wiring amount and the necessary wiring amount will be described with reference to FIG.

  Generally, since the wiring direction is determined for each wiring layer, the direction is taken into consideration. For example, as shown in FIG. 3A, when an area for 6 grids in the vertical direction and 7 grids in the horizontal direction are designated, the maximum number of vertical wirings in this area is seven. Since each grid includes 6 grids, the area of FIG. 3A includes 42 grids in total. Here, the maximum wiring amount in the region of FIG. 3A is defined as 42 grids as a value based on the number of wiring resources (a function of the number of wiring resources). The necessary wiring amount is defined as a wiring amount with respect to wiring actually existing in the area. Taking the region of FIG. 3B that is in the same range as FIG. 3A and being actually wired as an example, FIG. 3B has four wires in the vertical direction. The wiring amount for the entire wiring is 24 grids. Therefore, the necessary wiring amount in FIG. 3B is defined as 24 grids as a value based on the actual number of wirings (a function of the number of wirings). In the same way, in the case of FIG. 3C, there are 21 grids. At this time, since the wiring direction is vertical, the grid for the horizontal wiring is ignored. In the case of wiring congestion, there are cases where the wiring overlaps twice. Similarly, the case of the horizontal direction is shown in FIGS. 3 (d), (e), and (f). Here, the necessary wiring amount / maximum wiring amount based on the ratio between the function of the actual number of wirings and the function of the number of wiring resources in a predetermined region is defined as an evaluation function (evaluation value). This evaluation function indicates the degree of wiring congestion in a predetermined area where the required wiring amount and the maximum wiring amount are defined. In step S204 (evaluation process) following the process of step S203 for designating a predetermined area including an area where wiring congestion occurs, the evaluation function value for the predetermined area is calculated, and the calculated evaluation function value is a predetermined value. The degree of wiring congestion is determined based on whether or not it is within the range. Specifically, if the value of this evaluation function exceeds 1, wiring is not possible, so it is determined whether or not it is in a range not exceeding 1 (predetermined range). If it exceeds 1, the process returns to step S203, and further The determination is performed again for a new predetermined area that has been expanded. However, in practice, since it is difficult to set the predetermined range to a value that does not exceed 1, it is preferable to set the value to be about 0.7 to 0.5 and enlarge the predetermined area. When the value of the evaluation function becomes 0.7 to 0.5 by adjusting the size of the predetermined area by the repetitive process (rewiring area specifying process) between steps S203 and S204, and a new predetermined area is determined. Next, the process proceeds to step S205 (wiring grid width determining step), and the wiring grid is changed. The interval between the new wiring grids to be changed is determined by multiplying the reciprocal of the evaluation function value (value based on the evaluation value) that is smaller than 1 by the current wiring grid interval value. Based on the new wiring grid obtained in this way, the placement / wiring is executed again in the next step S206. As a result, the number of wirings in a region where wiring congestion has occurred locally is limited, and cells are arranged in consideration of the information, thereby suppressing wiring congestion.

(Second Embodiment)
Next, in the present embodiment, the case where the wiring method for changing the wiring grid in order to eliminate the crosstalk error is applied to the layout in which the crosstalk error has occurred will be described with reference to the flowchart of FIG. I will explain.

  FIG. 4 shows the first point in that crosstalk verification including timing error verification is performed in step S402 following step S401 in which arrangement and wiring are performed, and then in step S403, the presence or absence of crosstalk is determined. It differs from FIG. 2 of the flowchart of embodiment.

  In the layout causing the crosstalk error, the long wiring is performed with the minimum space width, and the side coupling capacitance is increased, thereby being easily affected by the crosstalk.

  After placement and wiring are performed in step S401, crosstalk is verified in step S402, and the result is confirmed in step S403. In the series of steps S402 to S403 (rewiring verification step), when crosstalk based on wiring occurs and it is determined that rewiring is necessary, the area near the net where crosstalk occurs is determined. Attention is paid and a predetermined area including the area is designated in step S404 (area designation step). Next, in step S405 (evaluation step), the maximum wiring amount and the necessary wiring amount described in the first embodiment are counted, and the necessary wiring amount / maximum wiring amount is calculated as an evaluation function value. Then, the predetermined area is enlarged in steps S404 to S405 (rewiring area designating step) until the value becomes about 0.7 to 0.5. When the predetermined area is determined, the process proceeds to the subsequent step S406 (wiring grid width determining step), and the wiring grid width is changed. Also in the present embodiment, the wiring grid width to be changed is determined by multiplying the current wiring grid width by the reciprocal of the evaluation function value set to a value smaller than 1. In the next step S407, wiring and arrangement are executed again in this state. As a result, the wiring grid in the vicinity of the wiring affected by the crosstalk is increased, and as a result, the coupling capacitance is reduced, so that the crosstalk error can be locally solved without increasing the area of the semiconductor integrated circuit.

  In the above description, the method of determining the wiring grid after determining the predetermined area has been described. However, the predetermined area may be set after determining the wiring grid. This is shown in the flowchart of FIG. In the flowchart of FIG. 5, the process up to step S503 for confirming the verification result of the crosstalk error is the same as the process up to step S403 in the flowchart of FIG. 4, but it is determined in step S503 that a crosstalk error has occurred. In such a case, the area designation is not performed, and a wiring grid width that does not cause a crosstalk error is determined in step S504 (wiring grid width determination step). Then, after the wiring grid width is determined in step S504, a predetermined area where crosstalk using the determined wiring grid is generated is specified in step S505 (area specifying step). That is, in step S504, the coupling capacitance at the place where the crosstalk error occurs is checked, and the extent to which the crosstalk error is eliminated is calculated, and the wiring grid width is determined therefrom. . In step S505, a predetermined area where the crosstalk error has occurred is set. In the next step S506 (evaluation process) for the predetermined region designated in step S505, an evaluation function is calculated as in the first embodiment, and the calculated evaluation function is smaller than 1. The degree of wiring congestion is determined depending on whether or not it is within the range (predetermined range). Here, through a series of steps S505 to S506 (rewiring area designating step), the predetermined area is further expanded and a new predetermined area is set and judged until the evaluation function falls within the predetermined range. Repeated. When the value of the evaluation function falls within the predetermined range, rewiring is performed in step S507. In this way, the wiring grid width is determined in advance in order to realize a coupling capacity that eliminates the crosstalk error, and rewiring is performed under this state to locally eliminate wiring congestion, thereby providing a semiconductor integrated circuit. Without increasing the area, it is possible to secure the wiring width so that the crosstalk error does not occur without fail.

(Third embodiment)
Next, in the present embodiment, a case where a wiring method for changing a wiring grid in order to eliminate wiring congestion is applied to a layout causing a timing error will be described with reference to the flowchart of FIG. To do.

  In the flowchart of FIG. 6, the arrangement and wiring process in step S601, the process of performing timing verification including crosstalk verification in step S602, and the process of S603 for determining the presence / absence of a crosstalk error from the crosstalk verification result are shown in FIG. However, when it is determined in step S603 that there is a timing error, the process does not move to a process for changing the area for changing the wiring grid width, but the load capacity is large. 4 is different from the flowchart of FIG. 4 only in the process of moving to step S604 for selecting wiring.

  In a layout where a timing error occurs, the longest wiring is performed with the minimum space width, which increases the side coupling capacity and increases the load capacity. Is prone to occur.

  After placement and wiring in step S601, timing verification (STA) is performed in step S602, and the result is confirmed in step S603. If it is determined in this series of steps S602 to S603 (rewiring verification process) that a timing error based on wiring has occurred, a timing error is caused in the next step S604 because the load capacity is large. A wiring is selected. Subsequently, in step S605 (area specifying step), a predetermined area including the area where the timing error has occurred is specified. In the next step S606 (evaluation step), the maximum wiring amount and the necessary wiring amount described in the first embodiment are counted, and similarly, the necessary wiring amount / maximum wiring amount is used as an evaluation function. Then, the predetermined area is enlarged by repeating the series of steps S605 to S606 (rewiring area specifying step) so that the value falls within a predetermined range of about 0.7 to 0.5. When the predetermined area is determined, the process proceeds to step S607 (wiring grid width determination step), and the wiring grid is changed. Also in this embodiment, the wiring grid width to be changed is determined by multiplying the current number of wiring grids by the reciprocal of the evaluation function value set to a value smaller than 1. In the next step S608, wiring and placement are executed again in this state. Thereby, by reducing the load capacity, the delay value of each cell is lowered, and the timing error can be corrected.

  Further, as described in the second embodiment, a predetermined region may be set after the wiring grid is determined. This is shown in the flowchart of FIG.

  In the flowchart of FIG. 7, the process up to step S703 for confirming the verification result of the timing error is the same as the process up to step S603 in the flowchart of FIG. 6, but in the series of steps S702 to S703 (rewiring verification process), If it is determined that an error has occurred, the area designation is not performed, and the wiring grid width is determined in step S704 (wiring grid width determination step). In step S704, the amount of load capacity to be reduced is calculated and a new wiring grid width is determined. Then, in step S705, a wiring having a large load capacity is selected. In step S706 (area specifying step), a predetermined area including the wiring having a large load capacity selected in step S705 is set. In step S707 (evaluation step), an evaluation function (necessary wiring amount / maximum wiring amount) is calculated for the predetermined region where the timing error set in step S706 has occurred, and the value of this evaluation function is calculated. The processes in steps S706 to S707 (rewiring area specifying step) are repeated until the evaluation function falls within the predetermined range until the evaluation function falls within the predetermined range, based on the predetermined area and the new wiring grid. Perform rewiring. Thus, by determining the wiring grid in advance and performing rewiring, the load capacity can be reduced and the timing can be improved.

(Fourth embodiment)
In the above embodiment, after placement and wiring, various verifications such as crosstalk and timing are performed, and if there is a problem in the result, a method has been adopted. In this embodiment, a wiring method that is applied in advance as a precaution against crosstalk and timing will be described with reference to the flowchart of FIG.

  In FIG. 8, first, in step S801, the wiring grid of the entire wiring layer is uniformly made larger than the minimum width. By uniformly increasing the wiring grid width, the side coupling capacitance is reduced and crosstalk and timing errors are less likely to occur. However, when the uniform wiring grid is increased, the wiring resources are reduced, so there is a high possibility that wiring congestion will occur. Therefore, only in the area where the wiring congestion occurs, it is necessary to secure the wiring resources by reducing the wiring grid or returning to the minimum grid to solve the wiring congestion. Step S801 and subsequent steps are the same as those in the flowchart shown in FIG. 2 in the first embodiment, but in FIG. 2, wiring congestion is performed by specifying a region to widen the wiring grid width in step S203. On the other hand, in the present embodiment, the wiring grid width is restored to the original reference wiring grid width or narrowed to secure wiring resources, thereby eliminating wiring congestion. This is different from the first embodiment.

  That is, first, in step S801 (uniform wiring grid changing step), the entire reference wiring grid is uniformly enlarged to a wiring grid having a predetermined interval, and the widened wiring grid having a predetermined interval is arranged in step S802.・ Wiring is performed. As a result, wiring congestion has occurred in step S803 (rewiring verification process), and if a verification result indicating that rewiring is necessary is issued, the wiring congestion has occurred in step S804 (area designation process). A wider area is specified, including the current area. In the next step S805 (evaluation process), the maximum wiring amount and the necessary wiring amount described in the first embodiment are counted, and the value of the evaluation function is calculated in the same manner. It is determined whether or not the value is in a predetermined range where no wiring congestion occurs, that is, in this embodiment, whether or not the value exceeds 1 (predetermined range). In the series of steps S804 to S805, even if the value of the evaluation function exceeds 1, when the wiring grid width is reduced, an area where the value of the evaluation function is smaller than 1 is selected. When a region where wiring congestion has occurred and the value of the evaluation function becomes smaller than 1 by reducing the wiring grid width, that is, a region where wiring congestion is eliminated is selected, the following step S806 ( In the wiring grid width determination step), a new wiring grid width to be actually reduced is determined. As a result, a wiring resource can be secured locally in a region where wiring congestion occurs, and rewiring is performed in the next step S807. By doing this, it is possible to obtain the effect of widening the spacing of the wiring grids in almost all regions in the wiring layer, that is, the effect of reducing the side coupling capacitance, and to expand the area of the semiconductor integrated circuit. In addition, the wiring grid can be laid out in a small area only in an area where wiring resources are required due to wiring congestion.

(Fifth embodiment)
In the embodiments described so far, no consideration is given to the boundary between the area where the wiring grid is changed and the area of the original wiring grid. However, when performing the minimum wiring correction, for example, when the wiring is corrected only in the changed wiring grid area without moving the wiring in the original wiring grid area, the wiring between both areas is connected. Area is required. An example in which this connection region is provided is shown in FIG.

  When the original wiring W is as shown in FIG. 9A based on the reference wiring grid set for the entire wiring layer, first, as shown in FIG. Set. When the wiring direction is the vertical direction, a search is made for a place where the vertical wiring W is continuous. In the case of FIG. 9B, there are three. In the present embodiment, the number of grids obtained by subtracting 1 from this number is set as the connection area.

  In FIG. 9C, a region between the dotted line region 20 and the new wiring grid region 10 is a connection region, and a region having a width of 2 grids obtained by subtracting 1 from 3 is shown. In this example, the original wiring grid area is set as the connection area, but the area of the new wiring grid may be expanded to be the connection area. In the connection area, it is not always necessary to pass through the wiring grid, and if necessary, the wiring in the original wiring grid area and the wiring in the new wiring grid area can be extended. In the connection region thus set, the boundary wiring W is connected by the connection wiring W1 in a direction orthogonal to the respective wiring directions.

  In FIG. 9D, the three continuous wirings W are bent and connected in the connection region. One of the three wirings is connected using the connection wiring W1 on the boundary line between the region 10 and the entire reference wiring grid region, and the remaining two are connected in the horizontal direction within the connection region. Are connected by the connection wiring W1. However, in this way, when there are a plurality of clusters of continuous wiring W and the interval between them is not sufficient, it is better to set the connection area further wide.

  Although FIG. 9 shows an example of connection using the connection wiring W1 using the wiring grid in the connection region, the connection on the wiring grid is not necessarily required. For example, FIG. 10 shows an example of connection by oblique wiring.

  The original wiring W shown in FIG. 10 (a) is the same as FIG. 9 (a). Further, FIG. 10 (b) for determining a new wiring grid area 10 and FIG. 10 (c) for setting a connection area. 9 is the same as FIG. 9, but in FIG. 10, when the wiring W on the original wiring grid is connected to the wiring W on the new wiring grid, the diagonal wiring W2 is used. Although affected by the grid width and the minimum spacing width, there is a possibility that the connection can be made in a smaller area than the connection using the wiring W1 on the grid as shown in FIG. The fact that the connection can be made in a small area means that there is little change from the original wiring W, which is particularly effective when it is not desired to move the original wiring W as much as possible.

(Sixth embodiment)
Next, contactable locations at the boundary between the original wiring grid area and the new wiring grid area will be described. When a new wiring grid area 10 is set as shown in FIG. 11 (a), there is a possibility that contacts to the upper and lower wiring layers may occur at the position indicated by X in FIG. is there. In this case, depending on the location, the minimum spacing width rule of the wiring layer may not be satisfied when the contact is formed. In order to prevent such a minimum spacing width error due to contact, contact is possible at the boundary between the original wiring grid region and the new wiring grid region 10 as shown in FIGS. 11 (c) and 11 (d). As for the location, the location where contact is possible only on one of the wiring grids is unified. Since the minimum grid is set so as not to cause a minimum spacing width error when the contact is formed, by making contact possible only on either grid, at least the minimum spacing width error at the time of forming the contact Can be prevented.

  In the semiconductor integrated circuit wiring method and the semiconductor integrated circuit according to the present invention, the wiring grid width is locally changed to a different width from the others in the wiring layer, so that local wiring congestion can be achieved without increasing the area. In addition, it is possible to eliminate errors related to crosstalk and timing, which is useful for a high-density semiconductor chip such as an SOC in which reduction in area is important.

It is a block diagram of the wiring layer containing a different wiring grid area | region in the 1st Embodiment of this invention. It is a flowchart figure in the case of solving wiring congestion in the 1st Embodiment of this invention. It is explanatory drawing of the required wiring amount in the 1st Embodiment of this invention, and maximum wiring amount, (a) is explanatory drawing of the maximum wiring amount of vertical wiring, (b) is required wiring about vertical wiring. (C) is an explanatory diagram of the required wiring amount for the vertical and horizontal wirings, (d) is an explanatory diagram of the maximum wiring amount of the horizontal wiring, and (e) is an explanatory diagram of the required wiring amount for the horizontal wiring. FIG. 4F is an explanatory diagram of the required wiring amount for vertical and horizontal wiring. It is a flowchart figure in the case of solving a crosstalk error in the 2nd Embodiment of this invention. It is a flowchart figure in another case which solves a crosstalk error in the 2nd Embodiment of this invention. It is a flowchart figure in the case of solving a timing error in the 3rd Embodiment of this invention. It is a flowchart figure in another case which solves a timing error in the 3rd Embodiment of this invention. It is a flowchart figure in the case of preventing a timing error and crosstalk in the 4th Embodiment of this invention. It is a figure which shows an example of the setting of a connection area | region, and connection wiring in the 5th Embodiment of this invention. It is a figure which shows the example of the connection wiring which used the setting of a connection area | region and the diagonal wiring in the 5th Embodiment of this invention. It is explanatory drawing of the contact possible location in the boundary of the original grid area | region and a new grid area | region in the 6th Embodiment of this invention.

Explanation of symbols

10, 11, 12 New wiring grid area (predetermined area)
13 Original wiring grid width (reference wiring grid)
14 New wiring grid width 20 New wiring grid area 30 including connection area Contact areas S202, S402, S403
, S502, S503, S602
, S603, S702, S703
, S803 Rewiring verification step S203, S404, S505
, S605, S706, S804 Area designation steps S204, S405, S506
, S606, S707, S805 Evaluation steps S205, S406, S504
, S607, S704, S806 Wiring grid width determination step S206, S407, S507
, S608, S708, S807 Rearrangement / wiring process W Wiring W1 Connecting wiring W2 Diagonal connecting wiring

Claims (14)

In a wiring method of a semiconductor integrated circuit composed of a plurality of circuit blocks designed using a wiring grid having a plurality of types of pitches,
A rewiring verification step for verifying the necessity of rewiring due to an error in the semiconductor integrated circuit that has been placed and wired; and
A predetermined area including an area requiring rewiring is specified based on the verification result obtained in the rewiring verification step, and a ratio between a value based on the number of wirings and a value based on the number of wiring resources for the predetermined area A rewiring area designating process for calculating
A wiring grid width determining step for determining a new wiring grid different from the reference wiring grid set for the entire wiring layer based on the ratio calculated by the rewiring area designating step. Integrated circuit wiring method. The wiring method for a semiconductor integrated circuit according to claim 1,
The rewiring area designation step includes:
An area designating step for designating a predetermined area including an area where the rewiring is necessary according to the verification result obtained in the rewiring verification process;
For the predetermined area specified in the area specifying step, an evaluation value based on a ratio of the function of the number of wirings to the function of the number of wiring resources is calculated, and whether the calculated evaluation value is within a predetermined range An evaluation step of determining whether or not to return to the processing of the region designation step if not within the predetermined range,
The area designating step designates a new predetermined area that includes the predetermined area after the determination by the evaluation process and is expanded when the process is returned from the evaluation process,
The wiring grid width determination step sets the new predetermined region based on the evaluation value when the evaluation value is determined to be within the predetermined range by the determination in the evaluation step. A wiring method for a semiconductor integrated circuit, characterized in that an appropriate wiring grid is determined. In the wiring method of the semiconductor integrated circuit according to claim 2,
The rewiring verification process verifies the necessity of rewiring due to wiring congestion,
The wiring method for a semiconductor integrated circuit, wherein in the region designating step, a region including a region where wiring congestion is caused by the verification result obtained in the rewiring verification step is designated as the predetermined region. In the wiring method of the semiconductor integrated circuit according to claim 2,
The rewiring verification step verifies the necessity of rewiring due to crosstalk,
The wiring method for a semiconductor integrated circuit, wherein in the region designating step, a region including a region where crosstalk is generated is designated as the predetermined region based on the verification result obtained in the rewiring verification step. In the wiring method of the semiconductor integrated circuit according to claim 2,
The rewiring verification process verifies the necessity of rewiring due to a timing error,
The wiring method for a semiconductor integrated circuit, wherein the region designating step designates a region including a region where a timing error has occurred based on the verification result obtained in the rewiring verification step as the predetermined region. In a wiring method of a semiconductor integrated circuit composed of a plurality of circuit blocks designed using a wiring grid having a plurality of types of pitches,
A rewiring verification step for verifying the necessity of rewiring due to an error in the semiconductor integrated circuit that has been placed and wired; and
A wiring grid width determining step for determining a new wiring grid that eliminates the error obtained by the rewiring verification step;
An area designating step for designating a predetermined area including an area that requires rewiring according to the verification result obtained in the rewiring verification process;
An evaluation value based on a ratio of a function of the number of wirings to a function of the number of wiring resources is calculated for the predetermined region specified in the region specifying step, and whether or not the calculated evaluation value is within a predetermined range And if not within the predetermined range, return to the processing of the region designation step, and if within the predetermined range, including an evaluation step to determine the predetermined region,
The area designating step designates a new predetermined area that includes the predetermined area after the determination by the evaluation process and is expanded when the process is returned from the evaluation process. Wiring method. The wiring method of a semiconductor integrated circuit according to claim 6,
The rewiring verification step verifies the necessity of rewiring due to crosstalk,
The method of wiring a semiconductor integrated circuit, wherein, in the region designating step, a region including a region where crosstalk has occurred is designated as the predetermined region based on a verification result obtained in the rewiring verification step. The wiring method of a semiconductor integrated circuit according to claim 6,
The rewiring verification process verifies the necessity of rewiring due to a timing error,
The wiring method for a semiconductor integrated circuit, wherein the region designating step designates a region including a region where a timing error has occurred as a result of the verification result obtained in the rewiring verification step. In a wiring method of a semiconductor integrated circuit composed of a plurality of circuit blocks designed using a wiring grid having a plurality of types of pitches,
A uniform wiring grid changing step for uniformly changing the reference wiring grid set for the entire wiring layer to a wiring grid of a predetermined pitch;
Rewiring verification for verifying the necessity of rewiring due to wiring congestion with respect to the semiconductor integrated circuit after being placed and wired based on the wiring grid of the predetermined pitch changed in the uniform wiring grid changing step Process,
A predetermined area including an area requiring rewiring is specified based on the verification result obtained in the rewiring verification step, and a ratio between a value based on the number of wirings and a value based on the number of wiring resources for the predetermined area A rewiring area designating process for calculating
A wiring grid width determining step of determining a new wiring grid different from the wiring grid of the predetermined pitch based on the ratio calculated by the rewiring region specifying step. Method. In the wiring method of the semiconductor integrated circuit according to claim 9,
The rewiring area designation step includes:
A region designating step for designating the predetermined region including a region requiring rewiring according to the verification result obtained in the rewiring verification step;
For the predetermined area specified in the area specifying step, an evaluation value based on a ratio of the function of the number of wirings to the function of the number of wiring resources is calculated, and whether the calculated evaluation value is within a predetermined range An evaluation step of determining whether or not to return to the processing of the region designation step if not within the predetermined range,
The area designating step designates a new predetermined area that includes the predetermined area after the determination by the evaluation process and is expanded when the process is returned from the evaluation process,
In the wiring grid width determination step, a new wiring grid that is set in the predetermined region based on the evaluation value when the evaluation value is determined to be within the predetermined range by the determination in the evaluation step. A wiring method for a semiconductor integrated circuit, characterized in that: In a semiconductor integrated circuit composed of a plurality of circuit blocks,
The plurality of circuit blocks include at least one circuit block including a plurality of regions respectively wired with different pitches. The semiconductor integrated circuit according to claim 11, wherein
The circuit block including the plurality of regions includes a connection region including a boundary line between adjacent regions among the plurality of regions and having a connection wiring that connects the wirings having different pitches. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 12, wherein
The connection wiring includes oblique wiring. A semiconductor integrated circuit, wherein: The semiconductor integrated circuit according to claim 11, wherein
Of the plurality of regions, a boundary line between adjacent regions includes a contact only on any one of the wirings having different pitches in each of the adjacent regions. .

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