GB2179478A - Planning circuit routes - Google Patents

Abstract

In the zone by zone computer planning of track routes for multi- layer printed circuit boards and the like the computer may be unable to route a track through a zone because of the presence of a via-hole or because other tracks have been forced to detour round a via-hole, so taking up all the available space. The solution of the invention is that at such a juncture the computer should display the routes so far to the Operator, indicate the tracks that cannot be routed (31), point out the via-hole (or via-holes) that may be the cause of the trouble (V6), and allow the Operator to take such action - by moving a via-hole to a different place (V6') - as will permit the computer to progress beyond the problem point (either after a fresh start, or simply by continuing from the point affected by the Operator- induced change). <IMAGE>

Description

SPECIFICATION Planning circuit routes This invention concerns the planning of circuit routes, and relates in particular to the design and planning of the layout of the conductive tracks used on printed circuit boards and the like.

In recent years considerable attention has been given to the problem of producing the layout of the conductive tracks required for printed circuit boards (pcbs), thick film circuits, thin film circuits, M.O.S devices and so forth. The first stage is generally the preparation of an artwork master, and in the case of printed circuit boards, for example, methods for making this artwork master involve the accurate deposition by hand of black adhesive tape onto a stable translucent material at a suitably enlarged scale, the resultant taped artwork master then being photographically reduced to produce the final working artwork.The accuracy of this manual technique is becoming more difficult to maintain in the face of decreasing track widths and intertrack clearances resulting from increasing packaging density requirements; while the use of digitization/photo-plotter techniques has overcome the accuracy problem it does not provide assistance in reducing the time required for the intellectual effort involved in deciding the positions of the components and the interconnection tracking, and much use is now being made of computers to assist in determining these two factors.

The following discussion relates for convenience mainly to the production of circuit designs for multi-layer printed circuit boards; it will be understood that the concepts disclosed are equally applicable to circuit designs for any other multi-layer device.

Satisfactory computer programs have been developed for automatically determining the positions of components on a printed circuit board, and an example of such a program is that used by the Marconi Company Limited under the name APPLE and referred to briefly in The Marconi Review, Third Quarter, 1974. However, it has proved difficult, if not impossible, to develop a program which automatically decides all of the track routes interconnecting the components. For difficult boards, some tracks cannot be routed by the computer, and the human Operator is required to adjust the computer 5 partial solution to achieve a complete solution.

In the past, routing programs were of the "search" type-that is to say, they involved asking where, on the board, could there be placed the next route to be devised. More recently, however, ''planned" routing programs have become available wherein there is asked a different question, namely what route can best be allotted to this part of the board. An example of such a programme is that used by The Marconi Company Limited under the name PEAR, and also referred to briefly in The Marconi Review (loc. cit.).Nevertheless, even the use of a program like PEAR is not without its problems, one of them being that if, after there have been devised all the possible routes, there remain some connections unrouted (because there is no available space on the board for any routes for those connections), the human intervention needed to deal with the problem involves re-devising a number of connection routes in toto in order to fit in the unrouted connections, and this is a rather error-prone procedure.

In an attempt to avoid this situation there has been evolved a modified route planning technique in which: a notional grid is superimposed upon the board, and the computer defines each route it is devising (in accordance with the rules of the chosen program) in terms both of the connection points and of the crossing points-here referred to as "X-points"-where the route crosses the grid lines; an initial schematic representation of the devised routes (the schematic representation constituting the vectorial connections all along each route between adjacent points, whether connection points or X-points) is displayed to the Operator, together with the X-points; and when human intervention is needed to redefine any route so as to make space for an otherwise unroutable connection this is effected by repositioning merely the relevant X-points.In this technique the board is divided into notional parallel strips or zones (usually defined by the array of component pin positions), and all the routes are simultaneously devised through each zone in sequence-that is, starting with the zone at one edge of the board and progressing, zone by zone, across the board to the opposite edge-rather than each route being devised from beginning to end, route by route.

Such a modified route planning technique is incorporated in The Marconi Company Limited's routing program APRICOT, and is employed in the artwork master production method described and claimed in the Complete Specification of their UK Letters Patent No. 1,502,006 (l/5856/M).

It is unfortunately often the case with route planning under the control of a suitably programmed computer that the final track route result, though in accordance with the specified rules, and even though acceptable for the most part, is extremely untidy and overly complicated.

Moreover, it is also often the case that the untidiness and complexity are because a small number of routes, though properly placed according to the rules, have nevertheless caused a much greater number of connections to be made by routes clearly other than the optimum for those connections. Thus, because the computer is required to determine all the routes that can possibly be determined, the proposed solution may well be a track route plan which could have been clear and simple if only one or two routes had not been defined but has instead become unnecessarily confused and complicated. A further improved route planning system, applicable specifically to APRICOT-like methods, involves more human intervention to deal with those situations where the rigid programming of the computer causes a needlessly complicated result.

It is employed in the artwork master production method described and claimed in the Specification of The Marconi Company Limited's UK Letters Patent No. 2,096,368 (1/6444/MR), and seeks to overcome the difficulty by arranging that a route between two circuit points is not automatically devised by the computer if devising it will result in subsequently-devised routes being overly complicated.

The computer-assisted planning methods used in these earlier inventions are, as stated, applicable to various physical implementations of circuit, but they are especially suitable for use with multi-layer and/or double-sided circuit boards where the portions of track in one plane (on one side, or in one layer) of the board are routed generally in one direction while the portions of track in another plane (on the other side, or in a second layer) are routed generally in a second direction (which is conveniently orthogonal to the first Using such boards, each track is taken as far as it can be in one plane, and then is continued, via a hole through the board (or between-layer insulation) in the other plane.At some stage the computer displays to the Operator the results of its deliberations, and the Operator can accept, reject or amend the suggested routes before instructing the computer to continue. A relatively minor modification of these earlier techniques is the subject of an Application for UK Letters Patent by the Marconi Company Limited, namely Application No. 85/25,262 (publication No. 2,131,5771/6719/MR).

Here, when the computer has determined that a portion of track route in one plane should now be terminated at a via-hole, where it is to be continued by a portion of track routed in another plane, or even is to be re-routed altogether (in the event, say, that no suitable via-hole exists), the situation is displayed to the Operator for him to make a choice between the computer's suggestions, or to make his own suggestion, before the computer is allowed to proceed with its route planning.

The present invention concerns another relatively minor modification, not unlike that just mentioned, which arises when the space for lateral routing in a zone becomes so congested that the computer is literally unable to find room to extend the route so far. The matter may be further explained as follows: The area-of a pcb, say-across which routes are to be devised is notionally divided into separate zones by a series of notional grid lines (in practice, on a pcb these grid lines very conveniently follow the lines of component pin positions). The places where routes cross each grid line are called X-points (crossing points). The routing process is now viewable as a set of independent routing processes, one per zone.

In each zone the problem is to make a set of connections each of which is between an origin and a destination. Each of the origins and destination can be any of: (a) a component pad on the top edge of the zone; (b) a component pad on the bottom edge of the zone; (c) an X-point on the top edge of the zone; (d) an X-point on the bottom edge of the zone; (e) a random pad somewhere between the top and bottom edges of the zone.

The set of connections for a zone is divided into two sub-sets-one sub-set will be associated with the tracks running predominantly in one direction (say, the "horizontal" tracks on one side of a pcb), while the other sub-set will be associated with the tracks running "across" the first (say, on the "vertical" side of a pcb).

An acceptable routing procedure is: (1) Consider the set of connections associated with the one (horizontal side) sub-set of tracks. In general-but not always-there will be a need for a via-hole (via) at each end of the connection.

(2) Decide whether there is a need for an origin via (and if so, where). If there is such a need then augment the list of the other (vertical side) sub-set of tracks with the additional connection requirement (i.e., from the origin to the origin via). Apply a similar process at the destination end of the connection.

(3) Plan the routing of the one (horizontal side) sub-set; in general, but not always, it will be from the relevant origin via to the relevant destination via. In the event (say) that there is no need for an origin via then the connection will be from the origin itself to the destination via.

So far, so good. The problem comes when the computer discovers it has run out of room-that so many tracks are being routed through some part of a zone that there is literally no free space for another. The situation can best be understood by imagining first of all how it applies to a double-sided pcb with "horizontal" tracks on one side joinable by via-holes to "vertical" tracks on the other side, where any particular zone is only deep enough (from top to bottom) to allow five adjacent tracks to run along it (from side to side)-from five origins at one side of the zone to five destinations at the other side of the zone-yet the computer has a sixth origin that needs to be connected by a sixth track in the zone to a sixth destination.There is simply no room for the sixth track! Now, instead imagine that there is (still) room for five tracks, and that there are-so far-only four tracks, but that one of these tracks runs to/from a viahole that is taking up precious room in the zone (via-holes are larger than tracks are wide), forcing the four tracks to detour round it so that they and the via together take up all the available "five-track" space. It is this type of problem with which the present invention concerns itself; the inability of a track to be routed through a zone because other tracks have been forced to detour round a via-hole, so taking up all the available space.The solution proposed is that at such a juncture the computer should display the routes so far to the Operator, indicate the tracks that cannot be routed, point out the via-hole (or via-holes) that may be the cause of the trouble, and allow the Operator to take such action-by moving a via-hole to a different place-as will permit the computer to progress beyond the problem point (either after a fresh start, or simply by continuing from the point affected by the Operator-induced change). In other words, where a problem arises because the number of tracks to be routed in each zone results in locally dense areas caused by the need to kink the tracks around "badly placed" via-holes, the suggested answer is simply to allow the Operator to control the positions of via-holes so that they are instead "well placed", and cause no, or less, dense area and track kinking.

In one aspect, therefore, this invention provides a method of planning the routes of circuit connections on a multi-layer printed circuit board or the like, in which: (a) a computer is used to plan the routes according to certain rules which require (i) that initially the area of the board or the like be divided into zones by a plurality of imaginary grid lines, (ii) that the routes in each zone be planned zone by zone, and (iii) that for each zone, where a planned route has route lengths that are in a plurality of layers, sequential lengths in different layers are joined by a via-hole;; (b) zone by zone the computer plans the route lengths running along each zone, and, where a length-joining via-hole has been (badly) placed so as to cause a blockage or a subsequent route length detour, and consequently there is no free across-zone space available for a planned alongzone route length, with the result that the computer is unable further to extend the route length along the zone, the routes so far planned for the zone are displayed to a human Operator; (c) the Operator then decides, and so instructs the computer, where to re-site the badly placed via-hole, and whether the relevant routes should be re-planned from the re-sited via-hole or from an earlier stage; (d) and thereafter the planning process is continued, in accordance with (a), (b) and (c) above, until a satisfactory situation is achieved.

The route planning method of the invention is intended primarily for use with the artwork master production methods of our aforementioned Patents Nos. 1,502,006 and 2,096,368.

Though, for convenience, the discussion hereinafter refers mostly to planning the track routes for printed circuit boards (pcbs) and the like, what is actually prepared are the artwork masters subsequently used to make the boards.

The method of the invention is in principle applicable to any sort of printed circuit board, thick film circuit, thin film circuit, M.O.S device and the like. For the most part, however, it is likely to be used with so-called multi-layer printed circuit boards, and it is primarily concerned with double sided boards (which may be regarded as having two layers of tracks). It is conventional with such double-sided boards that the tracks on one side are in general aligned in one direction (say, up and down the board, or "vertical"), while the tracks on the other side are in general in a second direction orthogonal to the first (from side to side of the board, or "horizontal").

The imaginary grid lines may be arranged and orientated in any way, and need not be rectangular, or even regular, so long as the computer is aware of their positions. Most conveniently, however, the grid is a rectangular grid, comprising one set of parallel lines orthogonal to a second set, and where the planned routes are for a printed circuit board in which conductive tracking is required to extend between and around the positions of a regular array of component pins then the imaginary grid lines are preferably defined by the rows and/or the columns of those pin positions. In any event, however, it is intended that in one layer the tracks will be aligned across the zones (from the bottom of a zone to its top, and thence to the next zone, and so from zone to zone), while in another the tracks will be aligned along the zones (in a direction from one side of a zone to the other).The method of the invention concerns dealing with the problem of a via-hole taking up valuable space in a zone, and, either immediately or subsequently, causing there to be left no across-zone room for the computer to extend an along-zone track.

Any particular route may have a number of lengths in different layers, the sequence of lengths forming the whole route by being joined one to the next by via-holes between the relevant layers. On a conventional double-sided printed circuit board, for instance, a route might start with a length on the vertical side, be connected by a via-hole to a length on the horizontal side, and be further connected, by another via-hole, to a final length on the vertical side.

It may well be that the placing of a via-hole (for the connection of one route length in one layer to a sequential route length in another layer), taking up (as it does; as stated earlier, a via hole is larger across than a track is) valuable space in the zone, results in there being no space for some subsequent along-zone route length in one or other layer. There are several reasons why this may occur. For example, there may be no space because there has been reached the zone boundary towards which successive along-zone route lengths are being placed (conveniently, the lengths are thought of as being planned and placed either from the top to the bottom of each zone or in the reverse-bottom to top-direction). Again, space may be short because there has been reached some zone-narrowing fixed component position.Another possibility is that there has been reached a zone space-taking route length having a higher priority, and planned sometime earlier (it will very commonly be the case that in a preliminary stage the computer decides to plan one set of route-lengths from "one" edge and a second from the "other" edge, so that, by the time it comes to planning the second set, most of the originally available space has been taken up with the first set). Moreover, this lack of space may occur immediately, because the via-hole itself has taken up all the available space, or ultimately, because some earlier, but still subsequent, along-zone route lengths have had to detour around the via-hole, so eventually causing there to be no room following the last of these detouring lengths.It is this situation that the inventive method seeks to deal with, and it does it by displaying the zone as so far planned, and allowing the Operator to move the offending-the badly-placed-via-hole.

It might be thought that if the computer placed the via-hole where it did then that is the end of the matter, for there is nowhere else to put it. This is not so, however. It will often be that the computer had a number of possible sites for the via-hole, and-being unable to look far enough ahead-chose the wrong one-the one that would give rise to the lack-of-room problem, instead of one that would not have done so. The human Operator, with the benefit of a better overall view, can re-site the offending via-hole in any one of the possible positions that will not cause the problem.

The display the computer provides for the Operator can be a printed display, such as is available from a plotter, but for various reasons the use of a Visual Display Unit of the television screen type is much preferred.

Exactly where the Operator re-sites the badly-placed via-hole is a decision he takes based upon his experience of and feel for these matters, and no further comment need here be made.

However, it is worth pointing out (as is discussed further hereinafter with reference to the accompanying Drawings) that the situation in the zone will often be that, for one reason or another, a series of along-zone routes length detours has already occured, forming a "promon tory", that the offending via-hole has been placed in line with the promontory when it could instead have been placed alongside it (in what one might think of as a recess), and all the Operator has to do is move-or rather, instruct the computer to move-the via-hole sideways and up alongside the promontory, further away from the bottom zone boundary, so naturally making more room available.

Once the Operator has re-sited the badly-placed via-hole the computer must be instructed to continued with the route planning process, and clearly this "continuation" must start not from where the computer called a halt but at least from where the Operator has re-sited the via-hole.

However, it may be desirable to have the computer re-plan from an even earlier point-the Operator may, for example, suspect that his chosen via-hole position could seriously upset some previously planned routes-and thus the inventive method allows the Operator to instruct the computer at what point to begin the re-planning.

After the Operator has suitably instructed the computer, the method loops back to the computer planning section, and the cycle of planning, displaying and instruction is continued until a circuit has been devised that is satisfactory to both machine and man. At that stage the production of, say, an artwork master utilising as a basis the result of the combined computer/ Operator efforts may be carried out in any convenient manner, and attention is here drawn to the various techniques mentioned in the earlier Patent Specifications identified hereinbefore.

The invention extends to an artwork master whenever produced using the route planning method of the invention.

The invention is now described, though only by way of illustration, with reference to the accompanying drawings in which: Figure 1 is diagrammatic, and represents a double-sided printed circuit board having conductive tracks thereon interconnecting the pin positions of various components carried by the board; Figures 2A, B, C and D are diagrammatic, and represent a section of a printed circuit board bearing a matrix of pin positions with different types of position-interconnecting routes being devised by a computerised route-devising system.

Fig. 1 is a diagrammatic representation of a double-sided printed circuit board (10) on which is shown a 4 row 5 column matrix of 20 holes (as 11) into which are fitted the connector members of the components (not shown) the board is to carry. In boards of the type under consideration the components are usually intergrated circuits in the form of dual-in-line packs (dips); the holes 11 then mark the positions of the components' pins, by which the components are both mounted on the board and inter-connected with other components.

Certain of the pin positions 11 are joined to others by conductive tracks (as 12a, 12b, 12c) on one or both surfaces of the board 10. The tracks (as 12b) on the obverse side (that side showing in the Figure as viewed) are all effectively vertically disposed (as viewed) and shown by solid lines, while the tracks (as 12a, 12c) on the reverse side are all effectively horizontally disposed (as viewed) and shown by dashed lines. Where an inter-connection route uses tracks on both sides of the board, the two are themselves interconnected by plated-through holes, known as via-holes (as 13).Thus, in the board shown in Fig. 1: (a) The conductive tracks interconnecting the top left pin position (column 1, row 1-position 1,1) to the bottom right pin position (column 5 row 4~position 5,4) are horizontal track 12a on the reverse side connected by a via-hole 13 to vertical track 1 2b on the obverse side connected by another via-hole 13 to second horizontaol track 1 2c on the reverse side.

(b) The tracks interconnecting pin position 4,1 to pin position 1,4 are a vertical track (14a) connected by a via-hole to a horizontal track (14b) connected by a second via-hole to a second vertical track (14c).

(c) The track interconnecting pin position 5,1 to pin position 4,4 is a single vertical track (15).

A board layout identical to that of Fig. 1 is shown in Fig. 1 of the drawings accompanying the Specification of our aforementioned Application No. 81/10,484.

Figs. 2A, B, C and D each represent a section of a double-sided printed circuit board. Each of these Figures shows the same two rows of pin-position holes (or pads) 1 to 16 (as 20). Each row defines the edge of a zone-the upper (as viewed) row the upper edge (ZUE), and the lower (as viewed) row the lower edge (ZLE). The zone has room for 9 (horizontal) tracks between the pin position holes (or pads) defining the zone edges, and one track at each edge.

In Fig. 2A there are shown the connections-the schematic connections (as 21), rather than the actual track routes-that the computer is required to plan for this zone of the board. Most of the connections (as 21a,b) are from one pin position to another, possibly by way of a via-hole (not shown at this stage), but a few (as 21c) are from a pin position to a crossing point (X-point; as 22) where the route is required to pass across the zone boundary and into the neighbouring zone (not shown). After initially setting up the zone-defining grid (the lines ZUE and ZLE are two grid lines, together defining a zone between them), for each zone in turn the computer decides how the connections will be composed of route lengths on one side of the board and route lengths on the other side, sequential lengths being connected by via-holes.

The main stages of the planning process are as follows: (1) The computer initially determines the order in which the point-to-point connections are to be made. It also decides which connections are to be packed to the top row and which connections are to be packed to the bottom row. In the diagram of Fig. 2A the resulting list of connections is:: Pack to Top Row Pack to Top Row 1 8,-9, 7 21- [ V3-V4j-X3 2 7,- 10, 8 4t- [ V5-V6 ] -X4 3 1 Ot- 1 2t 9 11be4, 4 13t- [ Vl ] -X 10 10b-13b 5 15- [ V2bX2 11 5t- [ V7 ] -1 4b 6 1 - 16 12 6t- [ V8 ] -16b V,-V6 and Xa-X4 are in Fig. 2B- V7 is in Fig. 2c;V8 is in Fig. 2D. The via-holes, V, to V8, are not normally part of the list; they are included merely to facilitate the understanding of subsequent Figures.

(2) The computer than takes the first connection (8t-9t) and packs it to the top row. It then takes the second connection (7t-10t) and packs that to the connection just laid. This process of taking and packing connections is repeated until either all the connections have been packed or until a connection fails to be packed.

Fig. 2B shows eight connections packed to the top row. The computer has then started on the bottom row pack list, and Fig. 2C shows two connections (2b-5b, and 10b-13b) packed to the bottom row. At this stage the computer attempts to route the 5t- [ V7 ] ~14b connection, trying to pack it to the two connections already packed to the bottom row. The (horizontal) route length is shown as the dashed-dotted line (31); it is clear that the via-hole V6 at the right hand end of the earlier-planned connection No.8 (4t- [ V5-V6 ] -X4) is "badly placed", and is causing a blockage which prevents the failing connection from being made.

The computer stops when this connection fails to be routed.

(3) At this stage the Operator can move the offending via-hole V6 to the right (by just specifying a new X co-ordinate, say). The Operator can then ask the computer to re-route all the connections starting from the 8th.

The 8th connection will now be re-routed to new via-hole position (V6' as in Fig. 2D), and this results in less blockage than before. The computer can then automatically route the 9th, 10th, 11th and 12th connections (the last two successfully!).

The situation is again shown in Figs. 3C and 3D (which are slightly enlarged version of the right-hand side of Figs. 2C and 2D). In Fig. 3C the offending, badly-placed, via-hole V6 is emphasised (together with the track length leading to it), as is the route of the failed track length 31 that is blocked because of the lack of any gap between via-hole V6 and the route length (32) for the 10b-13b connection. However, by moving viahole V6 to a new position V6 (shown dotted in Fig. 3C), tucked away in the recess left between the route length to via-hole V4 and that via-hole itself, so the Operator creates room for length 31 to extend (along the dotted section 31a) to 14,has shown in the finished plan of Fig. 3D. Additionally, room is at the same created for the tracking of the 12th connection (6t- [ V8 ] -16b); the track (33) is accomodated between the tracks to V6 and to 14b.

Claims (6)

1. A method of planning the routes of circuit connections on a multi-layer printed circuit board or the like, in which: (a) a computer is used to plan the routes according to certain rules which require (i) that initially the area of the board or the like be divided into zones by a plurality of imaginary grid lines, (ii) that the routes in each zone be planned zone by zone, and (iii) that for each zone, where a planned route has route lengths that are in a plurality of layers, sequential lengths in different layers are joined by a via-hole;; (b) zone by zone the computer plans the route lengths running along each zone, and, where a length-joining via-hole has been (badly) placed so as to cause a blockage or a subsequent route length detour, and consequently there is no free across-zone space available for a planned alongzone route length, with the result that the computer is unable further to extend the route length along the zone, the routes so far planned for the zone are displayed to a human Operator; (c) the Operator then decides, and so instructs the computer, where to re-site the badly placed via-hole, and whether the relevant routes should be re-planned from the re-sited via-hole or from an earlier stage; (d) and thereafter the planning process is continued, in accordance with (a), (b) and (c) above, until a satisfactory situation is achieved.

2. A method as claimed in Claim 1, applied to a double sided printed circuit board (which may be regarded as having two layers of tracks).

3. A method as claimed in either of the preceding Claims, in which: the imaginary grid is a rectangular grid, comprising one set of parallel lines orthogonal to a second set; where the planned routes are for a printed circuit board in which conductive tracking is required to extend between and around the positions of a regular array of component pins then the imaginary grid lines are defined by the rows and/or the columns of those pin positions; and in one layer the tracks are to be aligned across the zones (from the bottom of a zone to its top, and thence to the next zone, and so from zone to zone), while in another the tracks are to be aligned along the zones (in a direction from one side of a zone to the other).

4. A method as claimed in any of the preceding Claims, in which, after a satisfactory route plan has been devised, there is then prepared an artwork master utilising as a basis the result of the combined computer/Operator efforts.

5. A method as claimed in any of the preceding Claims and substantially as hereinbefore described.

6. An artwork master whenever produced using a route planning method as claimed in any of the preceding Claims.