GB2152283A - Gate protection arrangement for a semiconductor device - Google Patents

Gate protection arrangement for a semiconductor device Download PDF

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GB2152283A
GB2152283A GB08430820A GB8430820A GB2152283A GB 2152283 A GB2152283 A GB 2152283A GB 08430820 A GB08430820 A GB 08430820A GB 8430820 A GB8430820 A GB 8430820A GB 2152283 A GB2152283 A GB 2152283A
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diffused
semiconductor device
semiconductor
semiconductorwell
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GB8430820D0 (en
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Jun-Ichi Koike
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The input resistor of a gate-protecting circuit is formed by a diffused semiconductor layer (21), and an input pad (38) is formed over the diffused semiconductor layer (21), so that the input resistor (21) and the input pad (38) are arranged in a three-dimensional manner. This reduces the total layout area, and provides a device of a highly integrated form. Silicide layers (29) can also be provided both for contact regions for the input resistor (21) and for transistor regions (31,33) of the protected circuit to enhance the operating speed. <IMAGE>

Description

SPECIFICATION Gate protection arrangement for a semiconductor device The present invention relates generallyto a semiconductor device provided with a gate-protecting circuit.
In many semiconductor integrated circuits, a gate protecting circuit is provided in the vicinity of the input portion, particularly in the vicinity of an input pad (bonding pad), in orderto protect the internal circuit elements from excessively large input signals from external units. Fig. 1 ofthe accompanying drawings shows an example of a known integrated circuit in which a gate-protecting circuit 1 consisting of an input resistor 2 and a clamping diode 3 is inserted between an input pad 4 and internal circuitry 5 having elements that must be protected.
In this gate-protecting circuit, the input resistor may be a diffused semiconductor layer (or region) that is obtained by doping the main surface of a semiconductor substrate with impurities. Alternatively, the input resistor may be a polycrystalline silicon layer that is formed on the main surface of the semiconductor susbtrate. Fig. 2 of the accompanying drawings shows a resistor in which the main surface of a semiconductor substrate 6 is doped with impurities to form a shallow diffused semiconductor layer8 between field oxide films 7. In Fig. 2 and input pad 9 intheform of an aluminium layer is connected to one end of the semiconductor layer 8, and wiring 10 ofthe internal circuitry is connected to the other end of the semiconductor layer 8.Fig. 3 ofthe accompanying drawings shows a resistor in which a polycrystalline silicon layer 13 (which has a high resistance but a low impurity concentration) is formed by e.g. chemical vapour deposition (CVD) on a field oxide film 12 of a semiconductor substrate 11. As shown in Fig. 3, an input pad 14 is connected to one end of the polycrys tallinesiliconlayerl3,andwiring iSfortheinternal circuitry (e.g. circuitry 5 from Fig. 1 ) is connected to the other end of the polycrystallinesilicon layer 13, over an insulating film 16 (e.g. see "Nikkei Electronics", January31, 1983, p. 138, etc.).
With the above two constructions, however, the inventor has discovered that the input resistor and the input pad are laid out separately on the main surface ofthe semiconductor substrates, so thatthe area occupied by the gate-protecting circuit is increased, making it difficult to accomplish a high degree of integration. In devices which operate at high speed, in particular, the resistances of the semiconductor layer 8 and polycrystalline silicon layer 13 have been reduced by a silicide technique without increasing the steps offabrication. Therefore, in orderforthe semiconductor layer and the polycrystalline silicon layerto retain a predetermined resistance, their areas must be increased, which makes it difficu It to fabricate a device in a highly integrated form.
To overcome the problem, the present invention proposes that the input pad is formed over a diffused semiconductor layerforming the input resistor. This makes possible a reduction in the total areaofthe device and hence permits the device to have a highly integrated form.
Embodiments ofthe present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. is a diagram of a gate-protecting circuit and has already been described; Figs. 2 and 3 are sections through conventional resistor constructions and have already been described; Fig. 4 is a plan view of major portions of an embodiment of the present invention; Fig. 5 is a section taken along line X-X th rough Fig. 4; and Figs. 6(A) to 6(F) are sections showing the manufacturing steps thereof.
Fig. 7 is a sectional view of an alternative embodiment of the present invention.
Figs. 4 and 5 illustrate an embodiment of the present invention, wherein Fig. 4 is a plan view, and Fig. 5 is a section along line X-X therethrough. As shown in the drawings, a diffused semiconductor layer 21 consisting of p-type impurities such as boron ions is formed in an oblong shape in a portion of the surface of an n-type silicon substrate 20 which contains impurities such as phosphorous ions. The semiconductor layer 21 is between 0.5 to 10pm deep and has a sheet resistivity of 1 to 50 k#/Ei. Semiconductor region 21 A is formed in a separate portion as a p-type well in which an NMOS transistor QN of a CMOS circuit will be formed, as described later and has a similar depth and sheet resistivity to the layer 21.
An oxide film which is between 0.5 to 2.0 pm thick, and which acts as a field oxide film 22, is formed on top ofthe semiconductor layer 21, and a pair of contact portions 23,24 are formed in the oxide film 22 at each end of the semiconductor layer 21. A p-type semiconductor layer 25 or an n-type semiconductor layer 26 that acts as a channel stopper can be formed, if desired, underthe oxide film 22, and p-type high concentration semiconductor layers (1 x 1020/cm3) 27, 28 having a depth of 0.35 pom are formed underthe contact portions 23,24.The semiconductor layer (5 x 10l6/cm3) 25 having a depth of 1 pom formed overthe semiconductor layer 21 (and having a higher impurity concentration than region 21) also serves as a part of the input resistor so that the input resistance is effectively defined by the regions 21 and 25. It should be noted that the layers 25 and 26 are optional, but can be useful in obtaining optimum performance. An SiO2 film 29 that acts as an intermediate insulating layer is then formed, and contact holes are formed therein at the contact portions 23,24.
A PMOS transistor Qp consisting of a gate electrode 30 and p-type semiconductor layers (1 x 1020/cm3) 31 having a depth of 0.35 pm is formed in another portion of the silicon substrate 20, and an NMOS transistor QN consisting of a gate 32 and n-type semiconductor layer (1 x 1 020/cm3) 33 is formed in the other semiconductor layer 21A. These transistors Qp and QN form part of the internal circuitry ofthe MOS circuit that is to be protected.
Aluminium layers 34,35 and 36 are formed over the SiO2film 29to connect the transistors QP, QN, amd aluminium layers 37,38 are connected to the semiconductor layers (the highconcentration impurity layers 27,28) through contact holes. Of these, the aluminium layer37 is connected to the internal circuitry (such as the CMOS circuit), and the aluminium layer 38 that acts as an input pad is formed in approximately square configuration on the oxide film 22 or, in other words, overthe semiconductor layer 21.
The steps of manufacturing this semiconductor device will be described below in conjunction with Figs. 6(A) to 6 (F).
First, the main surface of an n-type silicon substrate 20 is completely oxidized to form an oxide film 40, as shown in Fig. 6(A), and then windows 41 areformedin the oxide film 40 by a photolithographic technique, as shown in Fig. 6(B). Using the oxidefilm as a mask, boron ions are implanted and are diffused by a high-temperature treatment, to form the p-type diffused semiconductor layers 21,21A, as shown in Fig.
6(C). The oxide film 40 is then removed by etching.
An SiO2 film 42 is then formed over the whole surface, as shown in Fig. 6(D), and an Si2N3film 43 of a required pattern is formed thereon. The Si2N3 film 43 is then selectively oxidized to form thick oxide films that act as the field oxide films 22 as shown in Fig. 6(E).
If it is desired to include a region 25 and 26forchannel stopping and, in the case of region 25, for serving as part ofthe input resistor, the following steps (not shown) can be used. After the step of Fig. 6(D), first and second ion implantationsthrough a SiO2film 42 are carried out using an Si3N4film 43 and two photoresistfilms (not shown) as masks. One of the photoresistfilms covers the surface of n-type substrate for implanting p-type impurities which will be used to form region 25, and the other covers the surface of p-type well for implanting n-type impurities which will be used to form the region 26.In the step of Fig. 6(E), the channel stoppers 25 and 26 and a field oxide film 22 can then be formed simultaneously by a conventional heat treatment method.
The NMOS transistor QN and PMOS transistor Op are thereafter formed in a customary manner, the high-concentration impurity layers 27,28 are formed simultaneouslywith the semiconductor layers 31 of the PMOS transistor Op, and a wiring layer 37 and an input pad 38 areformed mimultaneouslywith the formation and contact of the aluminum layers 34,35 and 36, and are connected together. This completes the semiconductor device shown in Fig. 6(F) and Fig. 4.
The same reference numerals as those used in Fig. 4 are used forthe device of Fig. 6(F).
According to the thus-constructed semi conductor device, the input pad 38 is formed on the semiconductor layer 21 that acts as an input resistor. Therefore, the total area ofthe input pad 38 and the semiconductor layer21 can be reduced bythe quantity by which they are superposed, and the device can be efficiently integrated. The input pad 38 is formed flat on the field oxidefilm 22, so that a good bonding can be effected.
Some advantages ofthe embodiments described above are as follows: (1) The input resistor of a gate-protecting circuit is formed by an impurity diffused semiconductor layer, and an input pad is formed on the input resistor.
Therefore, the total layout area can be reduced to less than that when the input resistor and the input pad are arranged separately, and the semiconductor device can be realized in an extremely highiy-integrated form.
(2) An input pad is formed on a thick field oxide film on an impurity diffused semiconductor layer, so that the input pad is flat, enabling a good bonding of a wireorthe like.
(3) An impurity diffused semiconductor layer and an input pad can be formed by utilizing standard steps for fabricating MOS transistors, and can hence be formed easily without complicating the manufacturing process thereof.
The invention accomplished by the inventor has been described in detail above bywayofafirst embodiment thereof. However, the invention should in no way be limited to this embodiment alone, and can be variously modified within a scope that does not depart from the gist thereof. For instance, the device may be of a construction in which an n-type well is formed in a p-type silicon substrate, orit may be of the SOS (silicon on sapphire) construction, orthe SOI (silicon on insulating film) construction. In addition to boron and phosphorous ions, furthermore, the impurities may be any ofthose in groups IllorV, such as arsenic or antimony ions.Furthermore, an electrically conductive layer consisting of a high-melting point metal layer such as platinum, molybdenum or the like, ora silicide layer thereof, may be provided over the diffused semiconductorlayerwhich is a source or drain region of a MOS transistor, or on the surface (uppersurface) ofthe polycrystalline silicon layer that acts as a gate electrode, in order to reduce the resistance of these regions. In this case, the present invention is effective for providing an input protective resistor of a desired resistance within a small area.
Fig.7 shows an alternative embodiment of the present invention which utilizes Platinum silicide layers 50 which are formed on the resistor contact layers 27,28, Platinum silicide layers 52 which are formed on the source and drain regions 31 of the transistor Op and Platinum silicide layers 54 which are formed on the source and drain regions 33 of the transistor 0N. Numerals in Fig. 7 which corresponds to numerals used in Fig. 5 identify like elements. The silicide layers 50,52 and 54 having a sheet resistivity of 4f)1izl and 500 Athick can be formed in a self-aligned manner similarto that described on pages 164 and 165 of an article by T.Shibata etal., "An Optimally Designed Process for Submicrometer MOSFET's", IEEE Journal of Solid-State Circuits, Vol. SC-17, No.2, April 1982, pp. 161-165, which article is herein incorporated by reference. As noted in that article, the advantages of this silicidetechnique is that it permits lowering the resistance of the source and drain regions so that a shallow diffused source and drain can be used without increasing the resistance ofthe source and drain to the point that it degrades the circuit performance. Other various metals can be used for forming the silicide, including Mo, W,Ta, orTi.
By virtue of the structure of Fig. 7, the silicide can be added atthe location shown without being plated over the resistor 21. This prevents the silicidefrom undesirably reducing the resistance value ofthe resistor 21 (which would correspondingly require increasing the area of the resistor).Atthesametime, the resistance of the source, drain and resistor contacts is reduced to maximize speed.
An added feature of the Fig. 7 arrangement is the ormation ofa SiO2film 56 overthe gate of electrodes of the respective transistors Op and QN. This serves as a side wall for the silicide step, and can be accomplished in a manner similarly that shown in Fig. 2 of the article by P. J. Tsang et al., "Fabrication of High-Performance LDDFET's With Oxide Sidewall SpacerTechnology", IEEE Transactions on Electronic Devices, Vol. ED-29, No.4, April 1982, pp. 590-596, which article is also herein incorporated by reference.
It should be noted that, if desired, the silicide could be formed over the gate electrode by etching the S i02 film to expose the gate electrode prior to the silicidation.
The foregoing description has dealt with the cases in which the invention accomplished by the inventor is adapted to a semiconductor device employing a CMOS circuit as the protected internal circuit, which acts as the background ofthe invention. The invention, however, should in nowaybe limitedthereto, and can be adapted to othersemiconductordevices having different internal circuitry arrangements.
It isto be understood that the above-described arrangements are simply illustrative ofthe application ofthe principles of this invention. Numerous other arrangements may be readily devised by those skilled in the art which embody the principles of the invention.

Claims (18)

1. A semiconductor device having a gate-protecting circuit between an input pad and internal circuit elements, an input resistor of said gate-protecting circuit being a diffused semiconductorwell region of a second conductivity type within a semiconductor substrate of a first conductivity type, the input pad being located overthe diffused semiconductorwell region.
2. A semiconductor device according to claim 1, wherein a field oxide film is formed overthe diffused semiconductorwell region, and the input pad is a metal film formed on the field oxide film.
3. A semiconductor device according to claim 2, wherein the diffused semiconductor well region is between 0.5to 10pm deep, and the field oxide film is between 0.5 to 2.0 pm thick.
4. A semiconductor device according to claim 2 or claim 3, wherein the internal circuit elements include a CMOS circuit in the semiconductor substrate, the CMOS circuit having a NMOS and a PMOS transistor, the gates ofwhich being coupled to the input resistor.
5. A semiconductor device according to claim 4 further comprising a first high impurity concentration region of the second conductivity type in part of the diffused semiconductorwell region to couple the input pad to the diffused semiconductorwell region, and a second high impurity concentration region in a different part of the diffused semiconductor well region to couple the gates of the NMOS and PMOS transistors to the diffused semiconductorwell region.
6. A semiconductor device according to claim 5, wherein the first and second high impurity concentration regions are covered with a layer of silicide film.
7. A semiconductor device according to any one of claims 4to 6, wherein the source and drain regions of the NMOS and PMOS transistors are covered with a layer of silicide film.
8. A semiconductor device according to claim 7 as dependent on claim 6, wherein the silicideflims on the source and drain regions of said NMOS and PMOS transistors and on the first and second high impurity concentration regions are formed simultaneously.
9. A semiconductor device according to claim 7 or claim8,whereinthesilicidefilmsoverthesourceand drain regions are formed in a self-aligned manner with a field oxide film form surrounding each ofthe PMOS and N MOS transistors.
10. A semiconductor device having a gate-protecting circuit between an input pad and internal circuit elements comprising: a diffused semiconductorwell region of a second conductivity type within a semiconductor substrate of a first conductivity type, the diffused semiconductor well region acting as an input resistor of the gateprotecting circuit; a field oxide film overthe diffused semiconductor well region; a MOS circuit of the internal circuit elements, the MOS circuit including MOS transistors; and a silicidefilm covering source and drain regions of the MOS transistors and having first and second regions,thefirst region being to couple the input pad to the diffused semiconductorwell region, and the second region being to couple the MOS transistors to the diffused semiconductorwell region.
11. A semiconductor device according to claim 10, wherein the internal circuit elements include a CMOS circuit in the semiconductor substrate, the CMOS circuit including a NMOS and a PMOS transistor both having gates thereof coupled to the input resistor.
12. A semiconductor device according to claim 10 or claim 1 1,furthercomprising afirst high impurity concentration region of the second conductivity type formed in the first region, and a second high impurity concentration region formed in the second region.
13. A semiconductor device according to any one of claims 1 Oto 12, wherein the silicide films overthe source and drain regions and the first and second regions are formed in a self-aligned manner with a field oxide film surrounding each silicidefilm.
14. A semiconductor device according to any one of claims 10 to 13, wherein the silicidefilms on said source and drain regions ofthe NMOS and PMOS transistors and onthefirst and second high impurity concentration regions are formed simultaneously.
15. A semiconductor device according to any one of 14, wherein the input resistor further comprises a semiconductor region of a second conductivity type formed in a surface ofthe diffused semiconductor region between the well region and the field oxide film, the semiconductor region having and impurity concentration greater than that of the diffused semiconductor well region.
16. A semiconductor device according to claim 15, further comprising channel stopper regions formed in the substrate adjacent source and drain regions of each ofthe NMOS and PMOS transistors, the channel stopper regions having a conductivity type opposite that of the respective source and drain regions to which they are adjacent, the channel stopper regions being formed simultaneously with the semiconductor region ofthesecond conductivity type formed in a surface ofthe diffused semiconductorwell region.
17. A semiconductor device according to claim 15 orclaim 16,wherein oneofsaid PMOS and NMOS transistors is formed in a second diffused semicon ductorwell region of said second conductivity type which is formed simultaneously with said diffused semiconductorwell region.
18. Asemiconductordevice having a gate-protecting circuit between an input pad and external circuits substantially as herein described with reference to and as illustrated in Figs. 4 to 6, or Fig. 7 ofthe accompanying drawings.
GB08430820A 1983-12-07 1984-12-06 Gate protection arrangement for a semiconductor device Expired GB2152283B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58229915A JPS60123052A (en) 1983-12-07 1983-12-07 Semiconductor device

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Publication Number Publication Date
GB8430820D0 GB8430820D0 (en) 1985-01-16
GB2152283A true GB2152283A (en) 1985-07-31
GB2152283B GB2152283B (en) 1987-06-17

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GB08430820A Expired GB2152283B (en) 1983-12-07 1984-12-06 Gate protection arrangement for a semiconductor device

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JP (1) JPS60123052A (en)
KR (1) KR850005142A (en)
DE (1) DE3444741A1 (en)
FR (1) FR2556502B1 (en)
GB (1) GB2152283B (en)
HK (1) HK4389A (en)
IT (1) IT1178736B (en)
SG (1) SG77688G (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313722A1 (en) * 1987-10-29 1989-05-03 Deutsche ITT Industries GmbH Protection arrangement for MOS circuits
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
EP0427565A2 (en) * 1989-11-10 1991-05-15 Seiko Epson Corporation Integrated circuit having MIS transistor
US5121179A (en) * 1990-10-08 1992-06-09 Seiko Epson Corporation Higher impedance pull-up and pull-down input protection resistors for MIS transistor integrated circuits
US5227327A (en) * 1989-11-10 1993-07-13 Seiko Epson Corporation Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits
EP0535536B1 (en) * 1991-09-30 2001-12-05 Texas Instruments Incorporated Depletion controlled isolation stage

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3855252T2 (en) * 1987-12-07 1996-08-14 Texas Instruments Inc Method of manufacturing a twin-well BICMOS transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673428A (en) * 1970-09-18 1972-06-27 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3967295A (en) * 1975-04-03 1976-06-29 Rca Corporation Input transient protection for integrated circuit element
GB1592856A (en) * 1976-11-27 1981-07-08 Ferranti Ltd Semiconductor devices
JPS5811750B2 (en) * 1979-06-04 1983-03-04 株式会社日立製作所 High voltage resistance element
JPS57111065A (en) * 1980-12-27 1982-07-10 Seiko Epson Corp Mos field effect type semiconductor circuit device
JPS58119670A (en) * 1982-01-11 1983-07-16 Nissan Motor Co Ltd Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313722A1 (en) * 1987-10-29 1989-05-03 Deutsche ITT Industries GmbH Protection arrangement for MOS circuits
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
EP0427565A2 (en) * 1989-11-10 1991-05-15 Seiko Epson Corporation Integrated circuit having MIS transistor
EP0427565A3 (en) * 1989-11-10 1992-03-04 Seiko Epson Corporation Integrated circuit having mis transistor
US5227327A (en) * 1989-11-10 1993-07-13 Seiko Epson Corporation Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits
US5121179A (en) * 1990-10-08 1992-06-09 Seiko Epson Corporation Higher impedance pull-up and pull-down input protection resistors for MIS transistor integrated circuits
EP0535536B1 (en) * 1991-09-30 2001-12-05 Texas Instruments Incorporated Depletion controlled isolation stage

Also Published As

Publication number Publication date
IT1178736B (en) 1987-09-16
GB2152283B (en) 1987-06-17
KR850005142A (en) 1985-08-21
FR2556502A1 (en) 1985-06-14
JPS60123052A (en) 1985-07-01
GB8430820D0 (en) 1985-01-16
HK4389A (en) 1989-01-27
IT8423948A0 (en) 1984-12-06
FR2556502B1 (en) 1988-07-29
DE3444741A1 (en) 1985-06-20
SG77688G (en) 1989-03-23

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