FR2608872A1 - Low-rate data transmission device for an information transmission system using, in one direction of transmission, the so-called TDMA principle - Google Patents

Abstract

This low-rate data transmission device for an information transmission system using, in one direction of transmission, the so-called TDMA principle includes, on the one hand, in each secondary station SS1, SS2, SS3, ..., low-rate data transmission means MTFD1, MTFD2, MTFD3, ..., each associated with a transmission control memory MCE1, MCE2, MCE3, ..., reorganised for this transmission in a specific manner, in order to transmit the said data FD1, FD2, FD3, ..., according to shared time slices assigned to the various means MTFD, and, on the other hand, in the main station SP, means MRT for reconstructing, according to a predetermined frame TP, for example in accordance with notice X 50 of the CCITT, the low-rate data transmissions present in the shared time slices. Application: rural telephone systems.

Description

WDISPOSIT1F OF LOW-RATE DATA TRANSMISSION FOR A
INFORMATION TRANSMISSION SYSTEM USING SENSE
OF TRANSMISSION, THE PRINCIPLE SAYS AMRT ".

 The present invention relates to a low-speed data transmission device for an information transmission system using in a transmission direction the so-called TDMA principle, a transmission system consisting of a network comprising a main station and secondary stations comprising among others, a transmission control memory.

 Such an information transmission system is described in French Patent No. 2,502,426. This radio information transmission system is of the point-and-point type and consists of a network comprising a main station and secondary stations. This type of configuration is frequently used to build a distributed telephone hub.

 In the main station direction to secondary stations the transmission is broadcast, the main station transmitting to all secondary stations according to a conventional time multiplex.

In the sense of secondary stations to main station the transmission is carried out in packets according to the so-called principle of AnRT (Multiple Access to Distribution in the
Time). A secondary station transmits only if a time slot has been allocated to it and in a time slot there can only be one station to be transmitted. With such a method, all the secondary stations are synchronous with the main station and these secondary stations transmit in such a way that their information does not overlap on arrival at the main station. For this purpose, it is necessary to offset the transmission times of the secondary stations to take into account their distance from the main station and provide for guard time between each packet issued to avoid overlap on arrival.

 When such a system is used to make a telephone hub, each packet transmitted by a secondary station and which groups several bytes of a speech channel, represents a bit rate of 64 kbit / s, if the speech channel has been coded according to the MIC process. If one or more secondary stations are to transmit low speed data links to the main station, for example 1200 bit / s, they must use either service channels, if they exist in the TDMA frame structure, or take a 64 kbit / s rate per link to be transmitted, which has the disadvantage of reducing the number of circuits available to retransmit the speech paths.

 The present invention proposes a low-rate data transmission device for an information transmission system of the kind mentioned above, which makes it possible to avoid the aforementioned drawback.

For this purpose, such a low-speed data transmission device is remarkable in that it comprises, on the one hand, in each secondary station, MTFD means of low bit rate data transmission cooperating with the reordered transmission control memory for this purpose. specifically for transmitting said data, a time slot of the TDMA frame being shared and allocated to the different means
MTFD can be in different secondary stations through the organization of successive frames in a multiframe to allocate a time slot according to the rate to be transmitted and secondly in the main station of the MRT means for reconstituting according to a predetermined frame the low rate data transmissions present in the shared time slots.Thus, to avoid taking a large number of 64 kbit / s rates for retransmission of low bit rate data links, it is necessary to give the transmission TDMA a frame and multiframe structure such that in this case each packet representing a bit rate at 64 kbit / s can be shared between several low bit rate links, these links coming from the same secondary station or from different secondary stations. A low-rate data transmission will take each packet more or less often depending on the value of the flow to be discharged.

 The following description, made with reference to the accompanying drawings, all given by way of example, will make it clear that the invention can be implemented.

 FIG. 1 schematically shows an information transmission system in which the device according to the invention is used.

 FIG. 2 represents an example of organization of the frames in such an information transmission system.

 Figure 3 shows a simplified block diagram of a secondary station.

 FIG. 4 represents the diagram of one embodiment of low-speed data transmission means.

 Figure 5 shows a simplified block diagram of a main station.

 FIG. 6 shows the diagram of an embodiment of means for reconstituting data transmission at a low rate in a predetermined frame.

 FIG. 7 shows an exemplary embodiment of an addressing member included in the means for reconstituting low-speed data transmissions.

 In Figure 1 is shown schematically an information transmission system in which the device according to the invention is used. In this transmission system, the network consists of a main station SP and several secondary stations SS1, SS2, SS3,.

In the direction from the main station to the secondary stations the transmission is carried out according to a time multiplex, the information is transmitted by the transmission part PEP from the main station to all the receiving parts
PR1, PR2, PR3, ..., of the different secondary stations SS1,
SS2, SS3, ...,.

In the sense of secondary stations towards main station, the transmission is carried out according to the principle
TDMA The transmission part PE1 of the secondary station S51 transmits, in the time slots which have been assigned to them, its information to the reception part PRP of the main station, likewise the transmission part PE2 of the secondary station 882 and the transmission part PE3 of the secondary station SS3 transmit their information in the time slots that have been allocated to them. When low-rate data has to be transmitted by the different secondary stations to the main station, the TDMA transmission must be organized in order to allow perform low speed data multiplexing to limit the number of circuits used for this retransmission.

 According to the invention, the low-speed data transmission device is remarkable in that it comprises, on the one hand, in each secondary station SS1, sus2, sus3, ..., means MTFD1, MTFD2, MTFD3, .. ., of low-speed data transmission, each cooperating with a transmission control memory MCE1, MCE2, MCE3 ..., for transmitting said data FD1, FD2, FD3, ..., a time slot of the frame TDMA being shared and allocated to different MTFD means that can be in different secondary stations by arranging successive frames in a multiframe to allocate a time slot according to the rate to be transmitted and secondly in the main station SP means MRT for reconstituting according to a predetermined frame TP the low bit rate data transmissions present in the shared time slots.

 FIG. 2 represents an example of possible organization of the frames in an information transmission system such as that described in FIG.

 The idea of the invention is therefore to organize the transmission A.M.R.T. to perform low speed data multiplexing by sharing a time slot of the A.M.R.T. frame. between several low-speed data transmission equipment that may be in different stations.

 For this purpose and according to a preferred application the sharing of this time slot is carried out identically to what is indicated in the opinion X50 of C.C.I.T.T. This mode of sharing is however not limiting.

 This X50, 64 kbit / s bit rate, defines an interleaved 8-bit envelope structure. The structure of the multiplexing comprises 80 envelopes with 8 bits. The signal elements of each channel use one or more envelopes.

8-bit interleaved envelopes appear as follows on 64 kbit / s media:
- on 12.8 kbit / s channels, they are repeated in 5 envelopes,
- on 6.4 kbit / s channels, they are repeated from 10 to 10 envelopes,
- on 3.2 kbit / s channels, they are repeated from 20 to 20 envelopes,
- on the 1.6 kbit / s channels, they are repeated from 40 to 40 envelopes,
- on the 800 bit / s channels, they repeat 80 in 80 envelopes,
In each byte, the first bit is used, among other things, to synchronize the frame, the next 6 bits carry the data while the last bit can be used as a service bit.

The flows transported on the different channels are respectively
- 600 bits for a channel at 800 bit / s,
- 1.2 kbit / s for a 1.6 kbit / s channel,
- 2.4 kbitls for a 3.2 kbit / s channel,
- 4.8 kbit / s for a 6.4 kbit / s channel,
- 9.6 kbit / s for a 12.8 kbit / s channel,
The structure of the TDMA frame will be organized taking into account this opinion.

 In the direction of transmission from secondary stations to main station, the transmission of information is done in the time slots identified from GRO to GR31. Each time slot has a guard time during which there is no transmission and which therefore allows uncertainty on the arrival time of information at the main station. To reduce the influence of the guard time on the transmission rate efficiency, each time slot corresponds to 72 bytes.

The time slot GRO is reserved for a signaling link at 16 kbit / s which can be taken randomly for each of the stations. In this time slot the packet is constituted by
- a byte of guard time where there is no resignation,
- 5 bytes of rhythm to recover the clock at the reception,
- an unused byte,
- 16 bytes carrying the signaling link,
- 48 bytes not used.

 The time slot GR1 is taken successively by each of the stations. For this purpose, a multiframe is defined, multiframe which comprises as many frames as there are stations. In order to align with the X 50 message, a maximum number of stations is set at 80. Thus, a multiframe of 80 frames marked TGRO to TGR79, each comprising 32 time slots GR, is obtained.

 The CR1 time slice, which also lasts 72 bytes, carries a small packet of just 5 bytes of timing and one RDP packet start mark byte. This time slot GR1 is used at the main station to control the setting of secondary stations and possibly to determine the corrections to make.

The time slots GR2 to CR31 can be used by each of the secondary stations, provided that the main station has assigned them. They can be used to carry 64 kbit / s speech channels or low-rate data channels. Each contains a 72-byte packet, so constituted
- a byte of guard time where there is no transmission,
- 5 bytes of rhythm to recover the clock at the reception,
an RDP packet start mark byte,
a channel byte signaling byte when the packet is assigned to a speech channel,
- 64 bytes of information (which corresponds to the packetization of 8 ms of speech, when the packet is assigned to a speech channel).

 The coding of the speech being done at 8 kHz, the structure of the A.M.R.T. leads to a bit rate equal to 2.304 MHz. Each time slot GR lasts 250 iis. Each TGR frame lasts 8 ms and the multiframe formed by all 80 frames lasts 640 ms.

If a GR time slot is used by a station for a low-speed data link, this station takes this GR slice
- once on 80 frames if the link is at 600 bit / s,
- once on 40 frames if the link is at 1.2 kbittS,
- once in 20 frames if the link is at 2.4 kbit / s,
- once in 10 frames if the link is at 4.8 kbit / s,
- once in 5 frames if the link is 9.6 kbit / s.

So a time slot GR can convey
- 80 links at 600 bits,
- 40 links at 1.2 kbit / s,
- 20 links at 2.4 kbit / s,
- 10 links at 4.8 kbit / s,
- 5 links at 9.6 kbit / s,
or a mixture of these links at different speeds, whether these links are connected to a single secondary station or to different secondary stations.

 The place of these different links in the multiframe is fixed relative to the beginning of this multiframe.

The beginning of the multiframe is marked with respect to the multiplex frame transmitted in the main station to secondary stations direction. This multiplex is organized as follows
a TR frame composed of 36 time slots identified from ITO to IT35, each time slot carrying a byte.

an MT multiframe composed of 64 frames identified from TR to TR63
- a SMT supermultitram composed of 80 multiframes identified from MTO to MT79.

 The rate of this multiplex is 2.304 Mbit / s and each time slot carries a bit rate of 64 bits.

The duration of a frame is 125 ps, that of a multiframe is 8 ms and that of the supermultitram is 640 ms.

Each frame carries 30 information circuits in the IT2 to IT31, corresponding to the time slots GR2 to
CR31.

 IT32 to 35 are unused.

 The ITO carries synchronization patterns for locating the different ITs in a frame.

IT1 is used as follows
in the frames of rank 4n (0, 4, 8, 12, ..), synchronization patterns S making it possible to locate the different frames and multiframes in the supermultitram and in the multiframe of rank m, the data channel intended for the numbered station m.

 in 4n + 2 (2, 6, 10, 14, ...), 16 kbit / s signaling link for the dialogue between the main station and the terminal stations.

 in the frames of rank 2n + 1 (1, 3, 5, 7, ...), channel signaling V / V relating to the circuit of rank n.

 In the direction of the main station towards secondary stations, the operation is very simple. If a time slot is reserved for carrying low-speed data links, this 64-kbit / s circuit carries a X 50-organized multiplex. This multiplex is broadcast to all secondary stations and to each secondary station. Low bandwidth equipment will extract from the multiplex the channels that are intended for them.

In the sense of secondary stations towards main station when a time slot GR has been realized to carry low-speed data links it is necessary that
for a data link from a secondary station, the latter transmits in the time slot GR only during certain frames which are a function of the bit rate of the link
- the main station receiving in a GR time slot information from several secondary stations and relating to several data links, transforms this received packet data into a 64 kbit / s multiplex according to the X 50 advice .

 The simplified block diagram of a secondary station is shown in Figure 3.

The reception part 1 (referenced PR1 for the secondary station SS1 in FIG. 1), connected to an antenna 2, makes it possible to deliver the multiplex MX which is used by the equipment connected to the station. From this multiplex
MX, a reception time base 3 is reconstituted, time base 3 which makes it possible, by means of a control signal BR, to control a demultiplexer 4 which extracts the signaling signals via the V / V channel and the signaling link CS intended to a calculator 5.

From the reception time base 3, is deduced a time base transmission 6 which takes into account the distance between the secondary station and the main station. This time base 6 controls, by means of the control signal BE, a multiplexer 7 which groups together the timing signals RY, the signaling channel V / V, the signaling link CS transmitted by the calculator 5 as well as the information present on the bus
DGRs issued during GR time slots by equipment connected to the station. The output of the multiplexer 7 is connected to the transmission part 8 (referenced PE1 for the secondary station 881 in FIG. 1), which transmits the various information by means of the antenna 9. This transmission is validated by the contents of the memory of issue-code 10.

This memory 10 is read at the rate of the time slots GR by the transmission time base 6. The memory 10 contains information written by the computer 5, indicating whether a time slot GR is assigned or not to the secondary station.

 In accordance with the invention for enabling efficient transmission of low-rate data FD low-speed data transmission means 11 (referenced MTFD1 for the secondary station 1 in FIG. 1) are advantageously inserted in the secondary station and are thus switched on the DGR input of the multiplexer 7. For this purpose a synchronization signal SY is delivered to an output of the transmission time base 6, while the clock 12 of the station transmits the signal HST, clock 12 recovered on the signal of the reception part 1 and also used for the reconstruction of the reception time base 3.

 In FIG. 4, an exemplary embodiment of the low-speed data transmission means 11 is proposed.

 The means 11 receive FD data which are synchronous with the clock of the station HST = 2.304 MHz transmitted to a clock circuit 1100. These data are resynchronized using a FIFO circuit 1101 in which the writing is performed with a clock HE 1102 extracted from the data FD and the reading is executed with the clock HS from the clock circuit 1100. The clock HS can take the values 600 Hz, 1200 Hz, 2400 Hz, 4800 Hz and 9600 Hz depending on the data rate received. The packetization of the information is performed in the time slot GR assigned to the means 11, using two memories 1103 and 1104 of 64 bytes, in which the writing and reading are alternately performed. The reading of a memory is performed while the other is being written. For this, the means 11 have 2 time bases 1106 and 1107 in phase with the multiframe packet (TGRO to TGR79) by by means of the synchronization signal SY delivered by the transmission time base 6 (FIG. 3) of the station, synchronization signal SY also used to position the clock circuit 1100.

 Thus the writing in the memories 1103 and 1104 is controlled via a multiplexer 1105 by the time base 1106 whose clock is equal to HS / 6 (supplied by the clock circuit 1100). This time base 1106 comprises a divider by 64 1106a, followed by a divider by 2 1106b. It is this last divider 1106b which makes it possible to choose the memory in which the writing W is done while the divider 1106a indicates the addresses WA where the writing must be done. The data to be written to the output of the FIFO circuit 1101 is transformed using a serial-parallel converter 1108 which groups together 6 data bits. The writing in the memory is done in the different bytes with the bits 1 to 6, the bits of rank 0 and 7 being unused.

Similarly, the reading of the memories 1103 and 1104 is controlled via the multiplexer 1105 by the time base 1107 whose clock is equal to HST / 8 (supplied by the clock circuit 1100). This time base 1107 comprises a par divider 1107a, followed by a divider by 321107b, itself followed by a divider by 1107c. The divider 1107b gives the NGR numbers of the time slots CR of the frame and the divider 1107c gives the NTGR numbers of the TGR frames of the multiframe. The memory in which to read
R is indicated by the 2 1106b divisor of the time base 1106, as opposed to the write. The divider 1107a indicates the read-out addresses RA of the memory, but this reading can take place only under two conditions
- it must occur during the time frame
GR allocated to low bit rate data transmission. This is done using a comparator 1109 which compares the allocated number NAGR with the state of the divider 1107b.

- it must occur during the frame (s)
TGR allocated to low-speed data transmission. For this, it is arranged a memory 1110 of 80 words of 1 bit in which are indicated the frames affected. This memory is read from the divider 1107c which gives the frame numbers.

 When these two conditions are fulfilled, a valid gate AND gate 1111 (signal VAL) reads the memory via the multiplexer 1105 as well as the transmission of the data FD to the DGR bus by the transmission circuit 1112 after said FD data has been transformed using a parallel-serial converter 1113.

The contents of the memory 1110 indicate the frames for which the transmission takes place. For example for a data transmission at 9.6 kbit / s the transmission can take place during
TGR 0, 5, 10, 15, ... 70, 75.

 or TGR 1, 6, 11, 16, ... 71, 76.

 or TGR 2, 7, 12, 17, ... 72, 77.

 or TGR 3, 8, 13, 18, ... 73, 78.

 or TGR 4, 9, 14, 19, ... 74, 79.

or for transmission at 4.8 kbit / s the transmission may take place during
TGR 0, 10, 20, 30, ... 60, 70.

 or TGR 1, 11, 21, 31, ... 61, 71.

 or TGR 5, 15, 25, 35,. .65, 75.

 or TGR 9, 19, 29, 39, ... 69, 79.

and so on for 2.4 kbit / s transmissions; 1.2 kbit / s and 600 bit / s.

 As the description of this exemplary embodiment of low rate data transmission means is completed, it is now advantageous to describe more precisely the organization of the transmission control memory 10 of FIG. exploited according to the idea of the invention.

 According to one characteristic of the invention, the low-rate data transmission device exploits the transmission control memory 10 for transmission and transmission control of said data, the transmission control memory preferably containing two useful areas, a first useful area indicating whether a time slot is assigned to a maximum rate data transmission or a low bit rate data transmission, a second useful area indicating, for the latter case, whether the frame considered is assigned to this low speed transmission.

 The transmission control memory contains the information relating to all the GR time slots that have been assigned to the station. In a preferred application, a memory of 1024 bytes has been chosen which is decomposed into 3 zones of which 2 are used. The first zone that is used has the first 32 octets, 0 to 31, the second zone, which is unused, uses the next 480 octets, 32 to 511, the third zone is used from octet 512 to octet 1023, it corresponds to 32 times 16 bytes.

In the first 32 byte area, each byte corresponds to a GR time slot in the TGR frames. Each byte contains 2 bits E and S which serve to define the type of transmission. Bit E indicates whether the time slot GR is assigned to the station while bit S indicates whether the time slot GR is assigned to a speech channel (maximum bit rate), in which case the transmission takes place in all the frames TGR, or a low rate data transmission, in which case the transmission takes place only in certain TGR frames. The meaning of this set of 2 bits is therefore the following
ES
OX: no show
1 0: speech channel broadcast in all
frames
1 1: Low data pathways
broadcast in certain frames.

 In this 32-byte area, bytes 0 and 1 are unused.

 The second area of the memory that is used and which therefore contains the 32 groups of 16 bytes, is used to indicate the frames in which there must be a transmission. Only groups 2 to 31 are used and in each group only 10 bytes, representing 80 frames are used. Each of the 80 bits of these 10 bytes indicates for each frame if there is a transmission or if there is none.

 This memory is read in two parts. A first time, the first part of the memory is read from the time slot counter. This operation makes it possible to know if there must be emission of a voice or a data channel or no emission at all. The second time, the second part of the memory is read, the time slot counter indicates the group to be read, the last stages of the frame counter indicate the group byte to be read while the first stages of the counter indicate the bit of the byte to use. This second reading therefore makes it possible to identify, in the case of transmission of data at low bit rate, the frames in which there must be a transmission.

 The simplified block diagram of a main station is shown in Figure 5.

The reception part 20 of the main station (referenced PRP in FIG. 1), connected to an antenna 21, makes it possible to receive the information transmitted by the secondary stations during the different time slots GR, the output is connected to a device of FIG. alignment 22, known per se. This alignment device 22 is controlled by the signal BP1 of the time base 23 of the main station and, starting from the detection of the presence of information packets after recognition of the start of packet reference bytes.
RDP, deliver on the MXR bus the stream of information regularly positioned in the different time slots GR. The MXR bus is intended for equipment connected to the station. The time base 23 controls, by means of the signal BP2, a demultiplexer 24 which makes it possible to extract the V / V channel signaling signals and the signaling channel CS intended for a computer. 25.

 The time base 23 also controls, by means of the signal BP3, a multiplexer 26 which makes it possible to group the V / V channel signaling signals, the signaling link CS transmitted by the computer 25, the frame locking information VER and the MXE information. transmitted during the time intervals of the multiplex by the equipment connected to the station.

The output of the multiplexer 26 is connected to the transmission part 27 (referenced PEP in FIG. 1), itself connected to an antenna 28.

 In accordance with the invention to enable efficient reconstruction according to a predetermined frame TP low bit rate data transmissions present in the shared time slots of the reconstitution means 29 (referenced MRT in FIG. 1) are advantageously inserted in the main station on the MXR bus. For this purpose, a synchronization signal SY is delivered by the time base 23. The clock of the frequency station 30 HST delivers the signal HST / 8 and a signal 88 while the computer 25 delivers a positioning signal POS.

 FIG. 6 proposes an exemplary embodiment of the means for reconstitution 29 of low bit rate data transmissions according to a predetermined frame which, according to the nonlimiting initial choices, is an X 50 frame.

The reconstitution means 29 receive the bus
MXR. After a transformation by means of a serial-parallel converter 290, the information contained in a time slot GR is stored. For this purpose, two memories 291 and 292 are used, memories in which, successively, a write is performed. In each memory is written, via a multiplexer 293, the content of a time slot GR of a multiframe, that is to say 80 time slots. This writing is controlled by a time base 294 whose clock is the HST / 8 frequency signal delivered by the clock 30 of the station (FIG. 5). This time base 294 comprises a par divider 294a, followed by a divider by 32 294b, itself followed by a divider by 80 294c and a divider by 294d 2. The latter divider 294d chooses the memory in which the writing is done. The divider 294c selects the sector of the memory SM and the divider 294a chooses the OS bytes within each sector. The writing in the memory is done only for the time slot GR assigned to the reconstitution means 29. This is achieved by means of a comparator circuit 295 which compares the allocated number NAGR with the NGR state of the divider 294b and validate the writing (signal
VAL) when there is a tie. The time base 294 used for writing is in phase with the multiframe packet (TGRO to
TGR79) thanks to the synchronization signal SY delivered by the time base 23 of the station. It is the same for the time base 296 used for reading.

The reading of the two memories 291 and 292 is made via the multiplexer 293, in opposition to their writing. One is read while one reads the other. The reading address of the memories is delivered from an addressing member 297 consisting mainly of memories and described in more detail in FIG. 7. This addressing member 297 is read using the time base. 296 whose clock is the signal 58 delivered by the clock 30 of the station (FIG. 5), signal S8 whose frequency is equal, according to the preferred application, to 8
KHz. This time base 296 is composed of a divider by 296a, on the one hand by a divider by 16 296b and on the other hand by a divider by 64 296c, itself followed by a divider by 16 296d. The divider 296a gives the channel number, the divider 296b gives the channel number, the divider 296c gives the word number and the divider 296d gives the group number. The memory in which the reading R is to be read is indicated by the divider by 294d of the time base 294. The NOC and NPAC addresses delivered by the addressing device 297 are a function of the multiplexed rates on the X 50 frame. The computer 25 (FIG. 5) thus positions, using the POS signal, this addressing member 297 to take account of the configuration of the X 50 frame. At the output of the memories 291 and 292, there is only 6 bits per octet. An insertion device 298, the inputs of which are connected to the outputs of the dividers 296a and 296b, makes it possible to substitute for the bits of rank 0 and 7, framing bits according to the advice X 50.

The output of the insertion device 298 is connected to an input of a parallel-serial converter 299 which transforms the output data of the memories 291 and 292 into serial data, thereby obtaining at the output of the converter 299 a TP flow. at 64 kbit / s according to X 50.

 In Figure 7 is described in more detail, an exemplary embodiment of an addressing member 297.

 In the frame X 50, which comprises 80 bytes, there are 5 channels numbered from 0 to 4. In each channel there are data channels in variable number according to their bit rate, however in the same channel are only channels of data with the same bit rate.

Thus, depending on the flows, a channel can therefore carry the following channels
- 9.6 kbit / s rate: only one channel marked Vo.

In the X 50 frame this channel is found every 5 bytes.

- bit rate at 4.8 bit / s: two channels marked Vo and
V1. In the X 50 frame one channel is found every 10 bytes.

 - 2.4 kbit / s rate: 4 channels marked Vo to V3.

In the X 50 frame one channel is found every 20 bytes.

 - bit rate at 1.2 kbit / s: 8 channels marked Vo to V7.

In the X 50 frame one channel is found every 40 bytes.

 - flow rate at 600 bit / s: 16 channels marked Vo to V15.

In the X 50 frame a channel is found every 80 bytes, so it occupies only one byte.

 The memory 291 (or 292) is a storage RAM and contains 80 packets of 64 bits. This memory must be read in an order such that it delivers 64 frames X 50 each containing 80 bytes. In fact, the memory size is 8192 bytes: it can contain 128 packets but only 80 packets are used: packets O to 4, 8 to 12, 16 to 20, ..., 120 to 124.

 The read addresses of this memory could be provided from a memory of 8192 x 13 bits in which the computer of the station would write information taking into account the structure of the multiplex X 50.

Such a procedure would require the computer to make a large number of writes in this memory to indicate the read addresses of the storage memory 291 (or 292).

An identical result can be advantageously achieved with less substantial means and without imposing on the computer such a prohibitive number of writings. According to one characteristic of the invention, at the main station the means for reconstituting, according to a predetermined frame, for example an X 50 frame composed of V channels and C channels, the low-speed data transmissions comprise, inter alia, a addressing organ mainly consisting of:
- A frozen memory, preferably a REPROM in which are stored the read addresses for the Vo channel of the Co channel of the predetermined frame and this for all the different rates.

 - A RAM to address the sector of the frozen memory to read and the number of the channel concerned.

 an adder circuit for adding to the address values delivered by the frozen memory constants relating to the channel V and to the channel C concerned.

 Thus, in the REPROM memory 2970 are stored the read addresses for the Vo channel of the Co channel for the 5 speed rates envisaged in the application. Then, it suffices to add to these address values delivered by this memory 2970, constants which take into account the channel number and the number of the channel.

 The REPROM memory 2970 is an 8192 x 13 bit memory which delivers the packet number (7 bits) and the byte number NOC in the packet (6 bits) which must be read in the storage RAM 291 (or 292). ) for the Vo channel of Co. This memory contains 8 sectors of which only 5 are used, sectors relating to the 5 rates envisaged in the application. Each sector contains 16 groups of 64 words of 13 bits.

 The sector relating to the bit rate of 9.6 kbit / s delivers the 1024 successive read addresses of the storage RAM.

 The bit rate sector at 4.8 kbit / s delivers the 512 successive read addresses of the storage RAM. It delivers the same address for the Vo channel and the V1 channel: for this reason each of the 16 groups in the sector contains 32 words, each word being repeated twice.

The 2.4 kbit / s rate sector delivers the 256 successive read addresses of the storage RAM. It delivers the same address for Vo, V1,
V2, V3: for this, each of the 16 groups in the sector contains 16 words, each word being repeated 4 times.

 The sector relating to the bit rate at 1.2 kbit / s delivers the 128 successive read addresses of the storage RAM. It delivers the same address for the channels Vo to V7 for that each of the 16 groups of the sector contains 8 words, each word being repeated 8 times.

 The sector relating to the bit rate at 600 bit / s delivers the 64 successive read addresses of the storage RAM. It delivers the same address for the Vo to V15 channels so that each of the 16 groups contains 4 words, each word being repeated 16 times.

This REPROM memory 2970 giving the read addresses for the Vo channel of the channel Co is read from address coming from two origins
the word addresses NM and of group NG come respectively from the divider by 64 296c and from the divider by 16 296d, from the time base 296.

- the address of the sector NS comes from vine memory
RAM 2971 of 128 words of 7 bits, in which there are only 80 words used. For each of the 80 bytes of the X 50 frame, this memory delivers on 3 bits the sector of the REPROM memory 2970 to be used, that is to say the reference of the transported bit rate. This memory 2971 is read from the 296a divider indicating the number of the NC channel and the 16 296b divider indicating the channel number NV.

At the packet number NP delivered by the memory 2970 it is necessary to add a constant which depends on the NC channel number and the channel number NV 'relative to the byte of the frame X 50. The rule for obtaining the NPAC address of the package to read is to add the NP value 8 NV '+ NC where
NV 'represents the number of the voic and NC the number of the channel. The value NC comes, as previously described, from the divider 296a which addresses the memory 2971, while the value NV 'comes from the contents of the memory 2971 which delivers this value NV' on 4 bits for each byte of the frame X 50 .

 The NPAC packet number to be read is therefore obtained by means of an adder circuit 2972 in which, at the packet number NP delivered by the REPROM memory 2970, the value of NC and 8 NV 'is added (it is sufficient for this to use the 4 bits of NV 'in heavy weight).

 By proceeding in this manner, it is sufficient for the computer 25 (FIG. 5) to write (POS signal) 80 words in the RAM 2971 to configure the reading order of the storage memory 291 (or 292). . In the RAM 2971, the computer must write for each byte of the frame X 50, the indication of the transported bit rate (3 bits) and the number of the channel in the frame (4 bits).

The rule to get the address of the package to read
NPAC adding to NP, the value of NC + 8NV 'is detailed, for the value NC + 8NV', in the following table

#### SEP> 1
<tb> NV '
<tb> | 0 <SEP> | <SEP> O <SEP> | <SEP> 1 <SEP> 1 <SEP> 2 <SEP> 1 <SEP> 3 <SEP> 1 <SEP> 4 <SEP> 1
<tb><SEP> 1 <SEP> 8 <SEP> 9 <SEP> 10 <SEP> 11 <SEP> 12
<tb> 12 <SEP> 16 <SEP> 1 <SEP> 17 <SEP> 1 <SEP> 18 <SEP> 1 <SEP> 19 <SEP> 1 <SEP> 20 <SEP> 1
<tb><SEP> J <SEP> 1 <SEP> 24 <SEP> 1 <SEP> 25 <SEP> 1 <SEP> 26 <SEP> 1 <SEP> 27 <SEP> 1 <SEP> 28
<tb><SEP> 33 <SEP> 34 <SEP> 35 <SEP> 36
<tb> | 4 <SEP> 1 <SEP> 32 <SEP> 1 <SEP> 33 <SEP> 1 <SEP> 34 <SEP> 1 <SEP> 35 <SEP> 1 <SEP> 36 | <September>
<tb> 5 <SEP> 40 <SEP> 41 <SEP> 42 <SEP> 43 <SEP> 44
<tb> | 5 <SEP> 1 <SEP> 40 <SEP> 1 <SEP> 41 <SEP> 1 <SEP> 42 <SEP> 1 <SEP> 43 <SEP> 1 <SEP> 44 <SEP> | <September>
<tb> 6 <SEP> 48 <SEP> 49 <SEP> 50 <SEP> 51 <SEP> 52
<tb><SEP> 7 <SEP> 56 <SEP> 57 <SEP> 58 <SEP> 59 <SEP> 60
<tb> 18 <SEP> 1 <SEP> 64 <SEP> 1 <SEP> 65 <SEP> 1 <SEP> 66 <SEP> 1 <SEP> 67 <SEP> 1 <SEP> 68
<tb> 19 <SEP> 1 <SEP> 72 <SEP> 1 <SEP> 73 <SEP> 1 <SEP> 74 <SEP> 1 <SEP> 75 <SEP> | <SEP> 76
<tb>#<SEP> I <SEP> I <SEP> I <SEP> I <SEP> I
<tb> | 10 <SEP> | <SEP> | <SEP> 80 <SEP> 1 <SEP> 81 <SEP> 1 <SEP> 82 <SEP> 1 <SEP> 83 <SEP> 1 <SEP> 84
<tb><SEP> 11 <SEP> ss <SEP> 88 <SEP> d <SEP> 89 <SEP> 1 <SEP> 90 <SEP> 1 <SEP> 91 <SEP> 1 <SEP> 92
<tb> 12 <SEP> 96 <SEP> 97 <SEP> 98 <SEP> 99 <SEP> 100
<tb> 112 <SEP> 1 <SEP> 96 <SEP> 1 <SEP> 97 <SEP> 1 <SEP> 98 <SEP> 1 <SEP> 99 <SEP> 1 <SEP> 100
<tb> 13 <SEP> 104 <SEP> 105 <SEP> 106 <SEP> 107 <SEP> 108
<tb> 14 <SEP> 112 <SEP> 113 <SEP> 114 <SEP> 115 <SEP> 116
<tb> 15 <SEP> 120 <SEP> 121 <SEP> 122 <SEP> 123 <SEP> 124
<Tb>
Thus the low-speed data transmission device makes it possible to transmit said data efficiently, using simple means, without reducing the number of circuits available for the retransmission of the speech paths. The choice of a mode of multiplexing according to the advice X 50, although not limiting, is advantageous because the equipment related to this multiplexing mode are frequently present in the stations, which is still in the sense of simplicity.

 In addition, according to another characteristic of the invention, when the low-rate data transmission device uses a multiplexing mode in accordance with the recommendation X 50 of the CCITT which imposes a multiframe of 80 frames and so a maximum number of secondary stations equal to 80, to advantageously increase the number of stations, it consists of multiframes n times 80 frames.

Claims (5)

1. A low-speed data transmission device for an information transmission system using in a transmission direction the so-called TDMA principle, a transmission system consisting of a network comprising a main station and secondary stations including among others a transmission control memory, characterized in that it comprises on the one hand in each secondary station means MTFD low bit rate data transmission associated with the transmission control memory reorganized for this specifically to transmit said data, a time slot of the TDMA frame being shared and allocated to the different MTFD means that can be in different secondary stations by arranging the successive frames in a multiframe for allocating a time slot according to the bit rate to be transmitted and secondly in the main station MRT means to re constituting according to a predetermined frame the low bit rate data transmissions present in the shared time slots. 2. Low-speed data transmission device according to claim 1, characterized in that, preferably, for the sharing and allocation of time slots it uses a type of multiframe of the lead type that the multiplexing recommended in the opinion X 50 of the CCITT. 3. Low-speed data transmission device according to one of claims 1 to 2, characterized in that, in each secondary station for transmitting said data and for controlling the transmission of said data, it exploits the control memory of transmission which preferably contains two useful zones, a first useful zone indicating whether a time slot is assigned to a maximum rate data transmission or a low rate data transmission, a second useful zone indicating, for the latter case, if the frame under consideration is assigned to this low bit rate transmission. 4. Low-speed data transmission device according to one of claims 1 to 3, characterized in that, at the main station, the means for reconstituting, according to a predetermined frame composed of channels V and channels C, the low-speed data transmissions comprise, inter alia, an addressing device consisting mainly of  a fixed memory in which are memorized the read addresses for the channel Vo of the channel Co of the predetermined frame and this for all the different bit rates,  a random access memory for firstly addressing the sector of the frozen memory to be read and, secondly, indicating the number of the channel concerned,  an adder circuit for adding to the address values delivered by the frozen memory constants relating to the channel V and to the channel C concerned. 5. Device for low bit rate data transmission according to one of claims 1 to 4, characterized in that, when the multiplexing mode adopted is consistent with that recommended in the X 50 opinion of the CCITT which imposes a multiframe of 80 frames and thus a maximum number of secondary stations equal to 80, to increase the number of stations, it consists of multiframes n times 80 frames.