EP0480506A1 - TDM - information transmission system with a variable structure - Google Patents

Abstract

This system for transmitting information according to time-division multiplexing has a variable structure using at least one frequency channel to transmit, per second, to subscriber devices, NT transmission packets which are formed of nt binary elements and which are allotted to subscriber devices themselves providing, per second, 1/TS information packets of ns binary elements, a system including at least, on the one hand, this time-division multiplexing circuit (10) for multiplexing the information coming from the subscriber devices (from SPA1, CIA2, ..., SPAm...) and for forming the said time-division multiplex and, on the other hand, a demultiplexing circuit (28) for distributing the information from a time-division multiplex to the subscriber devices. In this system there is provision for interlacing means coupled with the multiplexing circuit for placing in an allotted transmission packet binary elements of various information packets allotted to the same subscriber device and deinterlacing means coupled with the demultiplexing circuit in order to effect the inverse operation to the interlacing means. …<??>Application : private radio networks. …<IMAGE>…

Description

The present invention relates to an information transmission system according to a time multiplex having a variable structure using at least one frequency channel to transmit, per second, to subscriber devices, N _T transmission packets which are formed of n _t elements bits and which are allocated to subscriber devices supplying them, per second, 1 / T _s information packets of n _s binary elements, system comprising at least, on the one hand, a time multiplexing circuit for multiplexing information from the subscriber devices and to form said time multiplex and on the other hand, a demultiplexing circuit for distributing the information of a time multiplex to the subscriber devices.

Such a system is described in patent application EP-A O 261 127. This known system makes it possible to transmit information packets of different formats. It is therefore possible to adapt to the different information packet formats of speech codec that are currently found on the market.

The invention proposes a system of this kind which also offers the possibility of adapting to the bit rate of the different speech coder-decoders and which also makes it possible to transmit data at variable bit rates on the same frame without thereby requiring a lot of means. .

For this, such a system is remarkable in that it is provided with interleaving means coupled with the multiplexing circuit for putting in an allocated transmission packet binary elements of different information packets allocated to the same subscriber device and deinterleaving means coupled with the demultiplexing circuit to perform the reverse operation of the interleaving means.

An important advantage of the invention is that a packet of errors occurring on a transmission packet is spread due to the interleaving on several information packets, as these are coded by means of correction codes of errors, the information can then be more easily reconstructed since the errors are spread out, therefore uncorrelated. The error correcting coding on each packet is therefore more efficient.

The following description, accompanied by the appended drawings, all given by way of nonlimiting example, will make it clear how the invention can be implemented.

• Figure 1 shows an information transmission system according to the invention.
• Figure 2 shows frequency spectra used by the TDMA multiplex.
• Figure 3 shows the organization of the TDMA multiplex.
• FIG. 4 shows the distribution of the channels used for the transmission of the transmission packets.
• Figure 5 shows the detail of the multiplexing circuit.
• FIG. 6 shows how the interleaving of the packets is carried out.
• Figure 7 shows how interleaving of binary elements by packet is achieved.
• Figure 8 shows how the address circuit for packet interleaving is designed.
• Figure 9 shows how the address circuit for interleaving binary elements in a packet is designed.

In Figure 1, there is shown a transmission system according to the invention. For reasons of simplicity, three transmission-reception devices have been shown, referenced by 1, 2 and 3 respectively, while in practice a plurality of such devices can be part of such a system. The devices 2 and 3 are considered in this example as mobiles while the device 1 is considered as a fixed or base station.

These three devices communicate with each other by a bidirectional link, of the radio type for example, which connects on the one hand the device 1 to the device 2 and the device 1 to the device 3 in the direction indicated by the arrow A and on the other hand the device 2 to device 1 and device 3 to device 1 according to arrow R.

A number of subscriber units SA1, SA2, ..., SAm for device 1 and SB1, SB3, (not shown) ..., SBn for device 2 and SB2 for the device 3. These subscriber organs can be telephone handsets, in the case of the organs SA1, SAm, SB2 and SBn, and they are connected to the devices 1 to 3 by speech coder-decoders SPA1, SPAm, SPB2 and SPBn respectively , or else facsimile transmission devices, etc., SA2, SB2 connected to devices 1 and 2 by circuits with interfaces CIA2 and CIB1. But whatever the subscriber unit, the data supplied at their output are of the binary type, so that the transmission between the devices 1 to 3 can be carried out according to a digital time multiplexing of the TDMA type, each of the devices being provided with means for incorporating or for taking information from the multiplex.

This multiplexing is carried out by the multiplexing circuit 10, which is part of the device 1, which multiplexes the information coming from the coder-decoders of the interface circuit SPA1, CIA2, ..., SPAm. To the multiplexed data, bits are added for managing the packet and the multiplex by means of an insertion circuit 12. Then the bits provided by the circuit 12 are used by a modulator 14 which emits a symbol for two binary elements (case of modulation with two binary elements per symbol). A transmitter 15 transmits these symbols in space by means of a transmission antenna 17 in the direction of the device 2 in the direction A.

The information coming from the device 2 propagating in the direction R is picked up by the reception antenna 20. A receiver circuit 22 connected to this antenna supplies signals to a demodulator 24. The binary elements reconstructed by this demodulator are processed by a circuit of withdrawal 26 which removes the management binary elements. A demultiplexer 28 distributes the information to the various decoders and interface circuit SPA1, CIA2, ..., SPAm. To be transmitted by radio, the TDMA multiplex requires frequency channels centered around a carrier frequency.

In addition, provision has been made for device 1, a switch of the PABX 29 type which makes it possible to establish communications between the mobiles, here, devices 2 and 3.

In Figure 2 there are shown frequency channels centered around two carrier frequencies FPA and FPR, each being assigned to a direction of transmission A and R respectively. The bandwidth BP envisaged above around these carrier frequencies is 25 kHz. The carrier frequencies are approximately in the 400 MHz-900 MHz band.

FIG. 3 shows the organization of this TDMA multiplex, composed of a multiframe MTR formed of M frames TR, each composed on the one hand of T time intervals TCHi (i = 1 ... T) and on the other hand of an XCCH time interval. The XCCH interval is used for organizing the multiplex while the TCHi intervals are used for transmitting useful traffic. Each of these intervals TCH ₁ to TCH _T comprises n _eb binary elements.

• M = 60 trames par multitrame,
• T = 19 intervalles de temps TCH par trame, soit 20 intervalles de temps au total avec l'intervalle XCCH,
• n_eb = 190 éléments binaires dont 46 servent à la récupération des 144 éléments binaires de trafic et à la gestion de la communication (synchronisation, état de l'abonné -décroché ou raccroché...).

For a time multiplex carrying between 1 and 6 channels we will have:

• M = 60 frames per multiframe,
• T = 19 time intervals TCH per frame, i.e. 20 time intervals in total with the XCCH interval,
• n _eb = 190 binary elements of which 46 are used to recover the 144 binary traffic elements and to manage communication (synchronization, subscriber status - off-hook or on-hook ...).

In the context of the example described, with 200 useful traffic time intervals transmitted in 1 second, all of the traffic channels have 28.8 keb / s.

The time multiplex having to adapt to different speech coders (2.4 keb / s, ... 13 keb / s), it is necessary to offer between 1 and 6 traffic channels. Figure 4 shows the organization of this multiplex for a number of channels equal to 4.

The four channels CHO to CH3 each correspond to a subscriber device and are used to transmit a packet of n _eb bits of which 144 are available to the user. The multiframe TR1 consists of 19 time intervals ITO to IT18 and a multiframe comprises 60 frames.

• ITO, IT4, ..., sont alloués au canal CHO,
• IT1, IT5, ..., sont alloués au canal CH1,
• IT3, ..., IT15 sont alloués au canal CH3.

In a frame the time intervals

• ITO, IT4, ..., are allocated to the CHO channel,
• IT1, IT5, ..., are allocated to channel CH1,
• IT3, ..., IT15 are allocated to channel CH3.

The multiplexing circuit 10, shown in detail in FIG. 5 is built around a memory 30 in which the speech packets produced by the speech coders SPA1, ..., SPAm are written. This memory is placed in turn in the write and read position by means of a periodic signal HO produced by a clock 31. The speech packets pass through battery memories LIF1 to LlFm respectively, which store the binary elements a by one and restore them one by one. The outputs of these memories LIF1 to LlFm are connected to the data input of memory 30 by means of a multiplexer 32. The output of memory 30 is connected to circuit 12.

The addressing of this memory is carried out by means of two sets of wires FCH and FBT. The FCH wires transmit a code relating to the channel and therefore relate to the information coming from the encoders. These wires are therefore used, when writing the memory 30, to select these different coders. For this, a decoder 35 is used which, depending on the code transmitted by the set of wires FCH, activates only one of the m wires of its output which respectively transmit the signals RDY1, ..., RDYm. These signals are applied on the one hand to the decoders SPA1 to SPAm to start the next conversion and on the other hand, to a series of AND gates A1 to Am.

The output signals of these doors act on the address pointer of the battery memories LIF1 to LlFm to empty these memories when they are active. To fill these memories, signals coming directly from the coders SPA1 to SPAm are supplied to the address pointer.

To address the memory 30, an addressing circuit 40 is used, the outputs of which are connected to the aforementioned sets of wires FCH and FBT and of which an output BO is connected to a gate 42 inserted between the output of the clock 31 and one of the inputs doors A1 to Am. This signal at the BO output blocks the emptying of the LIF1 0 LIFm battery memories by inhibiting the door assigned to the countdown of the address pointer of the concerned battery memory.

This memory is addressed by a counter 41 counting the pulses of the clock 31.

The invention proposes to adapt this multiplex to the different needs of subscribers.

1 - CASES OF DATA TRANSMISSION

If each binary data element is coded according to a coding rate 1/2 (that is to say that to the binary elements to be transmitted, other binary elements are added to implement a detector and / or corrector coding d 'errors).

• (lx9600) + (kx4800) + (jx2400) + (i×1200)≦14400 eb/s où
• 1 est le nombre de canaux de transmission à 9600 eb/s
• k est le nombre de canaux de transmission à 4800 eb/s
• j est le nombre de canaux de transmission à 2400 eb/s
• i est le nombre de canaux de transmisison à 1200 eb/s

The following formula gives the possible channel distributions:

• (lx9600) + (kx4800) + (jx2400) + (i × 1200) ≦ 14400 eb / s where
• 1 is the number of transmission channels at 9600 eb / s
• k is the number of transmission channels at 4800 eb / s
• j is the number of transmission channels at 2400 eb / s
• i is the number of transmission channels at 1200 eb / s

II - CASE OF THE TRANSMISSION OF CODED SPEECH IN DIGITAL FORM II - 1 Consideration on coders

To transmit speech, various speech coder-decoders are presented on the market. Table 1 below gives the characteristics of a few, referenced from A to K. These coders provide packets of information bits: for example 48 for the codec-decoder A every 20 ms, which represents 2.4 k.eb / s. By way of illustration, type G corresponds to a MATRA production, type J to a MOTOROLA production.

It is interesting to note that within the framework of our example described, it is possible to obtain the following bonds, indicated in Table II, in which DU signifies a duplex bond and H.DU, a bond to the alternation.

The adaptation to the different coders, both in bit rate and in packet structure, to the multiplex is carried out thanks to the combination of the frame structure carrying out the adaptation in terms of bit rate and to the interleaving means carrying out the adaptation in terms package structure.

The addressing of the memory 30 carrying out the adaptation described above is carried out around FCH and FBT whose characteristics are determined by the number of channels and the interleaving diagram.

II - 2 Considerations on the addressing circuit design 1) Determination of the number of channels

• INT( ) = partie entière de la quantité placée à l'intérieur des parenthèses,
• DU = 28,8 keb/s débit des éléments binaires utiles que transmet le multiplex,
• Df = débit utile du codeur de parole avec codage correcteur d'erreurs.

The maximum number of channels is fixed at 6 in the example described, which corresponds to 3 wires for the FCH assembly. The number C of these channels to be used is given by the formula:
C = INT (DU / Df) where

• INT () = whole part of the quantity placed inside the parentheses,
• DU = 28.8 keb / s throughput of useful binary elements transmitted by the multiplex,
• Df = useful rate of the speech coder with error correcting coding.

2) Determination of the interlacing factors

• Df.TS représente le nombre d'éléments binaires du paquet fournis par le codeur,
• NT est le nombre de intervalles de temps par seconde, dans cet exemple décrit, N_T = 200 c'est-à-dire Du/N_T = 144.

The interlacing factors to be determined are m1 and m2. They must respect the following relationship:
(Df.Ts) × m2 / m1 ≦ Du / N _T where

• Df.TS represents the number of binary elements of the packet supplied by the coder,
• NT is the number of time intervals per second, in this example described, N _T = 200, that is to say Du / N _T = 144.

Table III below gives the interleaving factors for different possible coders.

N defines the depth of the interleaving: the larger N, the more the error packets are spread and the more effective the error correcting codes.

Different kinds of interlacing can be envisaged.

III - INTERLACEMENT III - 1 Package interleaving

The principle can be explained using FIG. 6 which represents a table whose different numbered lines from i = 0 to m ₂ -1 contain m ₂ successive information packets supplied by an encoder. Each of these packets is divided into mid sub-packets, as shown in FIG. 5 by the references j = 0, 1, 2, ..., m ₁ -1. Each of these m ₁ subpackets is made up of L binary elements.

The result of the interleaving is a series PPO to PPmi -1 of packets of m ₂ x L binary elements formed from subpackets read in column.

Thus the PPO packet will be formed of the L first binary elements of the m ₂ information packets, the PP1 packet of the binary elements L to 2L-1 of the m ₂ information packets.

The number of bits in the sub-packets must be less than or equal to the number of bits in the transmission packets. Also, in the event of inferiority of bits, jams are inserted in the transmission packets, the signal BO inhibiting gate 42.

III - 2 Binary element-packet interleaving

This is explained with the help of figure 7. Just as for the packet interleaving, a table has been represented in which the different numbered lines i = 0 to m ₂ -1 represent the m ₂ packets of information, each divided into m ₁ sub-packets of L binary elements.

The result of this interleaving is a series of PBO packets with PBm ₁ -1. Only the PBO package is shown in this figure. This packet is formed of the first binary elements taken successively from the packages i = 0, i = 1, i = m ₂ -1, then second binary elements and so on for all the binary elements of the subpacket. The second packet PB1 will be formed in the same way for the L binary elements following the L-1 ^th .

The addressing table can be easily designed based on the considerations below.

There are two phases to consider: a memory write phase and a read phase.

IV - DESIGN OF THE ADDRESSING TABLE IV - 1 Package interleaving (see figure 8) a) Writing phase

Each information packet is written bit by bit in memory, for each of the encoders in use.

• pour i = 0 chaque paquet émanant de SPA1 à SPAn est inscrit, puis
• pour i = 1, on recommence et ainsi de suite...

Thus, referring to FIG. 8, the registration is carried out as follows:

• for i = 0 each packet originating from SPA1 to SPAn is registered, then
• for i = 1, we start again and so on ...

b) Reading phase

This reading phase consists, by reading the memory 30, of filling the transmission packets. The time interval ITO will be successively filled with sub-packets j = 0, packets i = 0, i = 1 and i = m ₂ -1, the whole coming from the coder SPA1, and possibly filled with binary stuffing elements STF . Then, the same operation will be carried out for each coder SPA2 to SPAm. Then, for the time interval ITm, the subpackets j = 1 of the packets i = 0 to i = m ₂ -1 will be inserted there, and so on.

IV - 2 Binary element-package interleaving (see fig. 9) a) Writing phase

It is identical to that described above.

b) Reading phase

All the first binary elements of the m ₂ packets (i = 0, ..., m2-1) are put in the ITO time interval, then the second. Thus, in FIG. 8, all the first binary elements are put in the ITO time slot, then the second binary element of the subpacket (i = 0, ..., m ₂ -1), and this for all the coders SPA1 to SPAm.

Then, to the frame ITm, which is allocated to the binary elements of the coder SPA1, we continue with the second binary element of the subpacket j = 1 and so on.

V - DE-INTERLACEMENT

It is the reverse operation of the interlacing operation and any person skilled in the art is capable of conceiving deinterlacing as a function of what has been said for interlacing.

Claims (4)

1. Information transmission system according to a time multiplex having a variable structure using at least one frequency channel to transmit, per second, to subscriber devices, N _T transmission packets which are formed of n _t binary elements and which are allocated to subscriber devices supplying them, per second, 1 / T _s information packets of n _s binary elements, system comprising at least, on the one hand, a time multiplexing circuit for multiplexing the information coming from the devices of subscribers and to form said time multiplex and on the other hand, a demultiplexing circuit for distributing the information of a time multiplex to subscriber devices, characterized in that interleaving means are provided coupled with the multiplexing circuit for putting in an allocated transmission packet bits of different information packets allocated to the same subscriber device and deinterleaving means coupled with the demultiplexing circuit to perform the reverse operation of the interleaving means. 2. Transmission system according to claim 1, characterized in that the interleaving means are designed to transform m ₂ different information packets made up of mid information sub-packets into mid transmission packets made up of m ₂ sub- different information packages. 3. Transmission system according to claim 1, characterized in that the interleaving means are designed to transform m ₂ different information packets made up of mid information sub-packets into m ₁ transmission packets made up of binary elements of each successive information sub-packet, two successive binary elements of the same information packet being spaced by m ₂ binary elements in the transmission packets. 4. Transmission system according to one of claims 1 to 3, characterized in that so-called stuffing bits can be placed in the transmission packets.

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