GB1336542A - System for tranferring information - Google Patents

System for tranferring information

Info

Publication number
GB1336542A
GB1336542A GB471072A GB471072A GB1336542A GB 1336542 A GB1336542 A GB 1336542A GB 471072 A GB471072 A GB 471072A GB 471072 A GB471072 A GB 471072A GB 1336542 A GB1336542 A GB 1336542A
Authority
GB
United Kingdom
Prior art keywords
word
read
time slot
words
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB471072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1336542A publication Critical patent/GB1336542A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

1336542 Automatic exchange systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 1 Feb 1972 [4 Feb 1971] 4710/72 Heading H4K [Also in Division G4] In a system in which an incoming bit stream is initially synchronized against a local clock and then stored in a data store from which any data word can be read out in a different numbered time slot from that in which it arrived, the act of synchronizing may cause data words to be repeated or deleted and this is overcome according to the invention by reading-out each data word at least three times per frame from the data store and then cancelling all the redundant words. The considered TDM, PCM transit telephone exchange of Fig. 1 comprises groups of eight, 32-channel receive highways 100-1, 100-8 which are each terminated by a synchronizer 101. The latter contains four word storage positions into which the contents of successive channels are written at the bit rate of the incoming stream. The positions are read-out at the bit rate of a local clock on to eight-wire highways 102 whereby each incoming serial-bit word is converted into parallel format and occupies a time slot dictated by the local clock. A signal in the synch. channel of each receive highway is effective to set a modulo 32 counter which provides each word read-out of the synchronizer with an identifying time slot number, this being transmitted over highway 103 to a multiplexer 104. The latter multiplexes the 32 words from each of the eight highways in a group into the first 256 of the 512 slots available within an exchange time frame and causes them to be written into respective locations of a data store 107 under the control of time slot address words accompanying them on highway 106. A cyclic control store 109 is primed with the necessary instructions as to when each location should be read out on to superhighway 108, i.e. a time slot interchange function. A receiver 100 is provided for responding only to data words relating to signalling information, such words occupying a particular time slot in each frame. It is the cancellation or repetition of these words that may give rise to errors and which it is the purpose of the invention to overcome. Synchronization.-Each highway incorporates a synchronizer 101 consisting of four wordstorage positions which are accessed sequentially by incoming words formed by eight serial bits. The words are read-out in similar sequential manner but in eight parallel bit format under local clock control. In view of phase differences between the incoming and local clock bit rates a situation can occur where a same word position is being simultaneously read and written. To prevent this, a word, preferably that in the synch. channel, is deleted if the incoming bit rate exceeds the clock, i.e. read-out, rate and is repeated if the clock rate is the higher. This action has the effect of reducing or prolonging by one time slot the period between successive samples of a same channel in their passage along highways 102 and 105. Such a change is not apparent on highway 108 which means that occasionally words will be skipped over or repeated twice during read-out of store 107. So far as speech is concerned this is of little consequence but it is of importance for signalling. Figs. 2 and 3 illustrate the cases where a frame is effectively prolonged and reduced respectively, utilizing as a model a group of three highways each having four channels that are multiplexed into 12 of 24 subslots of a superhighway wherein the first half of a subslot is used for writing purposes and the second half for reading. The corresponding words of a same channel in successive frames are referenced A, B, C, D. Due to repeated reading of a synch. word in the incoming synchronism, the period between the appearance of successive samples of a same speech channel is increased so that during write-in to store 107, a sample B will occur during the second, and not the first, time slot of a succeeding frame, c.f. Fig. 2a, where sample A occurs in the first subslot of the first time slot 1À1 whereas samples B (and of course C, D &c.) occur in the first subslot of the second time slots 2À1 of subsequent frames. It should be realized that this seeming change in position of a channel within a frame is of no consequence to the communicating parties, i.e. cross-talk does not occur, since the identity of every sample is known by virtue of the accompanying time slot number and thus the entry of the sample into the correct word location of store 107 is assured. During non-destructive read-out from the store, however, it will happen that the considered location will be accessed by control store 109 at exactly the same time in every frame, e.g. in the fifth subslot of the first time slot 1À5, so that in the second frame the same word A will be read-out again as the new word has not yet arrived, c.f. Fig. 2b. In the opposite case, i.e. when a synch. word is deleted, the effect in store 107 will be that a new data sample will be written in before a preceding one is read-out, thus causing loss of the said preceding one, c.f. missing C in Fig. 3b. The Figs. 2c and 3c indicate how this defect is overcome by reading each storage location three times, during the fifth subslots of the first, second and third time slots (remember that it is only the signalling word that is of prime interest so that the effective loss of two channels by such. repeated reading is not of too much importance). In the first case, A is read out four times and B only twice but this is sufficient to ensure that B is not lost and that it is authentic. In the second case, it is sample C that is only read twice but again the point is that it is not lost. A logic circuit (Fig. 4, not shown) incorporates a shift register into which the word samples read-out during the three successive slots 1À5, 2À5, 3À5 are fed and comparators for determining the contents of the stages of the shift register and for ensuring that each word is only applied once and then in its appropriate time slot to the signalling data utilization signal.
GB471072A 1971-02-04 1972-02-01 System for tranferring information Expired GB1336542A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NL7101468A NL7101468A (en) 1971-02-04 1971-02-04
US22123472A 1972-01-27 1972-01-27
US00381755A US3824349A (en) 1971-02-04 1973-07-23 Method of transferring information

Publications (1)

Publication Number Publication Date
GB1336542A true GB1336542A (en) 1973-11-07

Family

ID=27351638

Family Applications (1)

Application Number Title Priority Date Filing Date
GB471072A Expired GB1336542A (en) 1971-02-04 1972-02-01 System for tranferring information

Country Status (7)

Country Link
US (1) US3824349A (en)
AU (1) AU458786B2 (en)
BE (1) BE778878A (en)
CA (1) CA975477A (en)
FR (1) FR2125084A5 (en)
GB (1) GB1336542A (en)
NL (1) NL7101468A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4439786A (en) * 1978-09-29 1984-03-27 The Marconi Company Limited Apparatus and method for processing television picture signals and other information

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1004617B (en) * 1973-10-22 1976-07-20 Oselt Centro Studi E Lab Telec TELEPHONE SIGNAL RECEIVER FOR ELECTRONIC SWITCHING UNITS WITH CENTRALIZED LOGIC TA
FR2394952B1 (en) * 1977-06-13 1985-06-21 Constr Telephoniques SIGNAL TRANSFER SYSTEM FOR TIME SWITCHING CENTER
US4195205A (en) * 1978-06-21 1980-03-25 International Standard Electric Corporation Signal transfer system for time division switching systems
FR2467524A1 (en) * 1979-10-10 1981-04-17 Thomson Csf Mat Tel METHOD OF SWITCHING MULTIPLEX SIGNALS TEMPORALLY AND TRANSMITTED BY A CARRIER WAVE, IN PARTICULAR A LIGHT WAVE, AND DEVICE FOR IMPLEMENTING THE SAME
NL8203110A (en) * 1982-08-05 1984-03-01 Philips Nv FOURTH ORDER DIGITAL MULTIPLEX SYSTEM FOR TRANSMISSION OF A NUMBER OF DIGITAL SIGNALS WITH A NOMINAL BIT SPEED OF 44 736 KBIT / S.
NL8303060A (en) * 1983-09-02 1985-04-01 Philips Nv TELEPHONE CONTROL PANEL PROVIDED WITH PERIPHERAL CONTROL AREAS.
US5119368A (en) * 1990-04-10 1992-06-02 At&T Bell Laboratories High-speed time-division switching system
US7471752B2 (en) * 2004-08-06 2008-12-30 Lattice Semiconductor Corporation Data transmission synchronization

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL157481B (en) * 1968-07-05 1978-07-17 Philips Nv EQUIPMENT FOR A TELECOMMUNICATIONS CENTRAL FOR ESTABLISHING CONNECTIONS BETWEEN N INCOMING TIME MULTIPLE LINES AND N OUTGOING TIME MULTIPLE LINES.
NL7000939A (en) * 1970-01-23 1970-03-23 Philips Nv

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4439786A (en) * 1978-09-29 1984-03-27 The Marconi Company Limited Apparatus and method for processing television picture signals and other information

Also Published As

Publication number Publication date
CA975477A (en) 1975-09-30
AU458786B2 (en) 1975-02-18
AU3848072A (en) 1973-08-02
US3824349A (en) 1974-07-16
BE778878A (en) 1972-08-02
DE2201856B2 (en) 1977-03-24
DE2201856A1 (en) 1972-08-17
FR2125084A5 (en) 1972-09-22
NL7101468A (en) 1972-08-08

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee