FR2546320A1 - DEVICE AND METHOD FOR DATA TRANSFER IN SERIES OF SEVERAL BYTES - Google Patents

Abstract

TO TRANSFER DATA TO LOCATIONS IN A DIRECT ACCESS MEMORY, AND FROM THESE LOCATIONS, THE FOLLOWING OPERATIONS ARE CARRIED OUT: PRODUCE A TIMING PULSE CONSTITUTED OF TIMING SLICES, THE SLICES BEING DEFINED BY THE COUNT VALUES N OF A COUNTER124; GENERATE IN A COUNTER138 AN INITIAL ADDRESS SIGNAL DURING A FIRST CONTIGUOUS TIME SLICE OF THE RATE PULSE, THE INITIAL ADDRESS SIGNAL CONTAINING (IN ITS SEVENTH BIT) A READ-WRITE INSTRUCTION SIGNAL; INCREMENT THE INITIAL ADDRESS SIGNAL TO EACH COUNTER VALUE N OF THE COUNTER TO FORM ADDITIONAL DATA ADDRESS SIGNALS; ACCESS MEMORY LOCATIONS USING THE INITIAL ADDRESS SIGNAL AND ADDITIONAL ADDRESS SIGNALS; AND DELIVER DATA WORDS TO, OR RECEIVE, THE LOCATIONS BEING ASSIGNED BY THE RESPECTIVE DATA ADDRESS SIGNALS IN RESPONSE TO EACH COUNT VALUE N OF THE METER, WHEN THE DATA ADDRESS SIGNALS CONTAIN RESPECTIVE WRITING INSTRUCTION OR A READING INSTRUCTION.

Description

The present invention is directed to the transfer of

  bidirectional data between a memory and a central processing unit and, more specifically, a data transfer device and method that significantly increases the speed of data transfers in series of several bytes. In the prior art, the transfer of a byte of data is usually preceded by an address. It is thus necessary to transfer alternately addresses and data, to

  because of an address for each data transferred.

  According to the invention, a single address byte is generated and delivered to the memory from the processing unit and is followed by several data transfers to the memory or from the memory, without the processing unit having to produce

other addresses.

  The invention provides an improved apparatus and method for use in a data processing system for transferring data to or from a memory.

  random access memory having access word slots

  According to the invention, each of the recurring timing pulses consists of contiguous time slots, each time slot being defined by the n-order count value of a counter; an initial address signal is generated during the time slot appearing first in the timing pulse; the initial address signal is incremented at each counter count value N of the counter to form data address signals, which are used to access respective locations of the memory; and upon the occurrence of each counter count value N of the counter, a data word is written or read in the location to which the address signal has been accessed (incremented). The initial address signal can also be include a read / write instruction signal used to control the direction of word transfer with respect to each memory location accessed during a second portion of

the timing interval.

  The following description, designed to illustrate

  tion of the invention, aims to give a better understanding of its characteristics and advantages; it is based on the accompanying drawings, among which Figure 1 is a block diagram of the device of the invention; Figure 2 shows timing waveforms showing the relationship between the address and data bytes in data transfer methods according to the prior art;

  FIG. 3 represents cadence waveforms.

  showing the relationship between the address and data bytes according to the invention; and FIG. 4 shows other waveforms of

timing according to the invention.

  In the following description, for the sake of brevity,

  the timing waveforms of FIGS. 2, 3 and 4 will be designated as, for example, waveform 2A or waveform 2B instead of waveform A of FIG. 2 or the B waveform of

Figure 3.

  Referring now to FIGS. 1 and 3, the bits forming the address byte 100 of the waveform 3 B which is followed by the data bytes NO 1 to N are delivered in series from a data bus 164 to a buffer 113 of the type in chronological order, then to a shift register 110, and finally,

  via a connection wire 114, to a data shift register 112.

  This bitstream is also delivered to the input of a register to

offset 118.

  Just before the transmission of the address byte 100 of the waveform 3 B, at the instant t 0, a validation pulse 120

  counting (EC, waveform 3 A) goes to its high level under com-

  Means an input-output data control logic circuit 127 (FIG. 1) in order to reposition (R) a flip-flop 122 and, furthermore, to validate a counter 124 by its input VAL. The counter 124 is clocked via its input CLK by a series of clock pulses produced in a logic circuit 128 for producing clock pulses in series and delivered to the counter via an AND gate 109 when the latter is conditioned by the impulse

  High level CE coming from the input control logic circuit 127-

  output This clock pulse train SCK is also delivered via

  the AND gate 109 at an input 130 of the data shift register 112

  and at an input 132 of an AND gate 116.

  Since the AND gate 116 is then conditioned by the repositioned state of the flip-flop 122, the clock pulses from the clock source 128, via the AND gate 116, reach an offset input 135 of a shift register 118 and shift thereto the data that has been supplied to the data input terminal 134 from the shift register 110 via the lead wire 114. At the end of eight clock pulses, the counter 124 returns to its count value of the zero state to position the flip-flop 122 and, thus, to invalidate the AND gate 116 to interrupt

  the offset pulses applied to the input 135 and, consequently,

  Thus, the counting value of the shift register 118 contains only the first received byte (8 bits), which is the byte of address Ce byte, so that other data bits do not enter the shift register 118. address is introduced into a counter 138 when the latter is validated at its terminal VAL via a connection wire 140, during the positioning of the latch 122, and it gives

  access, via the decoding portion 150 'of the memory 150, to the location

  memory stack defined by the address byte then-finding in

the counter 138.

  The content of the seventh bit position of the shift register 118, which corresponds to the last bit of the address byte 100 of the waveform 3 B, determines whether the operation is a read or write operation Si the seventh bit contains a binary O value, then an AND gate 144 is excited to reposition R) a latch 146

  and, therefore, produce a read operation in the media.

  moire 150 (which manifests as an O value on the connection wire

  151) Conversely, if the sixteenth bit position of the decimal register

  lage 118 contains a binary value 1, an AND gate 154 is validated and sets (S) therefore flip-flop 146, so that it is issued a

  write instruction to memory 150 This form

  reading or writing truction remains valid for the entire group of data bytes of waveform 3 B, until the reception of the

  address byte with a new read instruction

  ture-write. Once the reception of the address byte 100 of the waveform 3 B has been completed, the logic circuit lying inside

  of block 142 in broken lines of FIG. 1 remains inactive while waiting

  When receiving the next address byte (not shown in FIG. 3), however, as indicated above, the data bytes received after reception of the address byte 100 are delivered in series, under the SDI designation, to the data shift register 112 from the shift register 110, via the lead wire 114, under control of the clock signals of the source 128 and without producing other address bytes. The counter 124 responds to

  these clock pulses coming from source 128 since it is always

  days validated by the CE pulse present on the wire connection 156

  by going through its counting cycle up to 8 every eight pulses

  In the case of a clock pulse, and outputting an output pulse corresponding to a zero count value on an output lead 158 every eight clock pulses, this zero count value output pulse increments the counter 138 by one. via its CLX input to give access to the next memory location

in the memory 150.

  At the end of the data byte N of the waveform 3B, the pulse CE of the waveform 3A returns to its low level at a time t1, which has the effect of invalidating the counter 124. and, thus, to end the incrementation of the counter 138, so that it is not

  further given access to other memory locations in the memory 150.

  In the case of a reading of data in the memory, the logic circuit inside the interrupted block 142 operates in the same way as in the case of writing in response to the address byte, as for example the address byte 100, except that the instruction applied to the memory 150 is then a read instruction instead of a write instruction. Thus, at each zero crossing of the counter 124, the data shift register 112 operates by receiving data from the memory 150 under control of a load signal which is the trailing edge of the count value

zero of the counter 124.

  The data written in the decoder lc is read therefrom and returned to the shift register 110 via a wire SDO serial data reading 160, the data being readable therein.

  to be transmitted to a buffer register 111 of the chronological order

  and then to the data bus 164 by well-known means. ET 101 and 103 are now considered, whose function is to validate respectively the buffers 111 and 113 obeying the chronological order, according to whether the data are written in the memory 150 or are read there. The AND gates 101 and 103 react to the simultaneous existence of the signal CE delivered by the logic 127 of the input-output control and represented on the waveform 3 A> of the zero count value of the counter 124 on a connection wire 97,

  and the respective output, repositioning signal 153 or

  151, of the flip-flop 146, respectively validating the buffers 113 and 111 via their inputs VAL The above process ensures the synchronization of the count value of the counter 124 with the data bytes read in the shift register 110 to be registered in the data shift register 112, or else read in the data shift register 112 to be registered

  in the data shift register 110.

  More especially> a word will not be read in the drum

  113 to be entered in the shift register 110 before a

  zero count value of the counter 124 is not produced.

  neither will a word be read in shift register 11 O to be written in buffer 111 before a count value

zero of the counter 124 does not occur.

  In summary, the data shift register 112 will be loaded by means of a data word from the memory 150 only in the case of the simultaneous existence of the counter count value 124 and an instruction for reading, these two signals to be delivered to the two inputs of an AND gate 129 As soon as it is enabled by the AND gate 129 via a VAL input, the data shift register 112 loads a word from the memory 150 during the read operation Conversely, a data word will not be read in the data shift register 112 to be written in the memory 150 before the appearance of the trailing edge of a zero count value of the counter 124 applied to a validation input 139 of the memory 150 Since a data word fits completely into the data shift register 112 following a zero count value of the counter 124, it follows that the write of this word in the memory 150 may also occur at the appearance of the trailing edge of the zero count value of the counter 124. The output signal of the clock generator 128 is not transmitted to the data shift register 118, counter 124 and the data shift register 112 after the

  positioning (S) of a rocker 155 by the positive front flank

  oriented direction of the EC pulse from the logic circuit 127 of

  Input-output command At the same time as this positive

  oriented signal of the CE signal, the buffer 113 is validated via its input

  VAL by the output signal of the AND gate 103 so that this

  pon delivers the first word that is the eight-bit address byte to the shift register 110, which then delivers this serial address byte to the data input terminal 134 of the shift register 118

in the manner indicated above.

  At the end of the transfer of the data following the address byte in the memory 150 or out of the memory 150, the negatively oriented rear edge of the pulse CE coming from the logic 127 input-output data control circuit, which is received by a reset input R of the counter 124, has the effect of repositioning (R) the flip-flop 155, which blocks the output signal of the logic circuit 128 generator of clock signals in series and, more, repositions the latch 146 via an OR gate 119

  to prepare for receipt of the next CE pulse.

  More specifically, the repositioning of the

  Gate 146 places the AND gate 103 in a conditioned state so that, upon the appearance of the next EC pulse, the AND gate 103 becomes conductive and validates the buffer 113 to deliver the first byte of the next transfer to the shift register 110. , then, in series, via the connection wire 114, to the shift register 118 of the

as above.

  In Figure 1, the portion 99 surrounded by a line

  interrupted means a central processing unit.

  FIG. 4 shows the relationship between the various timing signals SCK, SDO, CE and SDI shown in FIG. 1. It will be noted that the (positive) oriented front flanks of the clock pulses, which are designated as the pulses of FIG. Clock No. 1, No. 2 and No. 8, appear a time T after the appearance of the data on the wire 114 carrying the SDI input data of Figure 1, as indicated on the waveform 4 D This delay allows the data to be established on the line

  before being introduced in a timed manner into the

  In this case, the data is held on the bus 114 for a duration T 2 after it has been applied to the data bus 112 or the register 118 by the waveform clock pulses 4A.

shift registers 112 and 118.

  Of course, those skilled in the art will be able to

  giner, from the process and the device whose description comes

  to be given as merely illustrative and not limiting, various variants and modifications not outside the scope of the invention.

Claims (4)

R E V E N D I C A T I 0 N S   1 Device for transferring data from a system   data processing system, comprising: a central processing unit;   (99), a random access memory (150) containing locations   memory devices, input-output means (112), means (127) that produce timing pulses (CEs) for marking the occurrence of reappearing time intervals, and means (110)   which transmits memory location address bytes (100) of   adapted to be used by said memory during a first portion of time, which starts at the beginning of each of said reappearing time intervals (CE); characterized in that: the appearance of each address byte is followed,   within the limits of each of those time intervals, by   paritioning more than one byte of data ("byte of data n 1", etc.) within the limits of a second portion of each of said time intervals, where said data bytes are intended to be transferred in some of said memory locations or out of some others, who have been assigned; and further comprising: means (128, 109) for generating clock pulses; first counter means (124) responsive to said clock pulses generating (on 158) a signal indicating the end of each received byte; means (122,116) for setting the duration of said first time portion and said second subsequent portion of each of said time intervals; means (118) for receiving a byte of transmitted address; logic means (122, 138) having a second counter means (138) responsive to each of said memory address bytes e received by setting the count value of said second counter means to a value corresponding to the next memory location in front of be assigned during each of these time slots; means (CLK 138) for incrementing said second counter means in response to the occurrence of each said signal during each given time interval; and means (150 ') for assigning said locations   memory according to the content of said second counter means.   2 Device according to claim 1, characterized in that: in each time interval, the content of a predetermined bit (the seventh) of each of said address bytes constitutes a read or write instruction for the following data bytes within the same time interval; and said logic means further comprises means (144,154,119,146) responsive to the content of said predetermined bit of said address byte by conditioning said memory so that data words are written or read into the memory locations assigned during the second part of time of the reappearing time interval. 3 Device according to claim 2, characterized in that it further comprises data manipulation means (112, 129)   which includes a shift register (112) (a) corresponding to the instruction   reading and said signal from said first counter means by storing said bytes of read data in said direct access memory and (b) which otherwise responds to said write command and said first signal of said first counter means by outputting read words.   data to said input means of the memory.   4 Method for transferring data words consisting of data bits between a direct access memory and a central unit   process, characterized in that it comprises the following operations:   to produce, within each of several recurring timer pulses (CE), a predetermined number of contiguous time slots (100, byte of data n1, etc.), each slice being defined by the count value of order N ("0") of a counter (124) counting to N; generate an initial address signal ("address byte") during the contiguous time slot occurring first in said timing pulse; -   incrementing (in 138) said address signal to each count value of order N of said counter; and transferring, during each of the other time slices, from the second, subsequently appearing during said timing pulse, respective data words to a memory location assigned by said address signal, which has been incremented, or from this location.   Method according to claim 4, characterized in that   said address signal includes a read-write instruction   ture (seventh bit); and that it includes the additional operation   which consists in controlling the direction of transfer of the data bytes   memory of said address signal comprises a write instruction or a read command, so that the data words are written or read in respective memory locations during the transfer operation according to the read-write instruction found in said address signal.